ethernet pcmcia controller + combo transceiver - ic ?· auto media select between aui and utp. ......

Download Ethernet PCMCIA Controller + COMBO Transceiver - IC ?· Auto media select between AUI and UTP. ... IC…

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  • TC3299APreliminary Data Sheet

    PCMCIA BUS Interface Logic and Drivers

    PCMCIA BUS

    TC3299 Transmitand ReceiveControl Logic

    External SRAM

    DMA BufferControl Logic

    Manchester Encoderand Decoder

    AUI interfaceTP Interface

    Physical MediumAuto-MUX

    Block Diagram of TC3299A

    93C56/66 forCIS & Node ID

    ( TC3299A OPTION )

    Ethernet PCMCIA Controller + COMBO Transceiver

    Features

    1/26 August 27, 20003Copyright 2003, IC Plus Corp. TC3299A-DS-R30

    PCMCIA 2.01 bus interface. Use serial EEPROM 93C56/93C66 to store CIS. NE2000 compatible. IEEE 802.3 compatible. NS8390 Register compatible controller. Endec, UTP, AUI, and included. Auto media select between AUI and UTP. LED support for activity and Link. 100-pin LQFP package. Low Power CMOS process. TC3299A for UTP and AUI interface.

    General Description The TC3299A (EPCC) is designed to reduce parts count and cost for easy implementation of PCMCIA CSMA/CD Local Area Networks. The TC3299A is the integration of the entire bus interface for PCMCIA BUS and which it includes Ethernet controller, Manchester Encoder/decoder, 10BaseT function and AUI interface. It complies with

    IEEE 802.3 standards. TC3299A is compatible to NS8390 controller's register and Novell NE2000 industry Ethernet standard. To store CIS, TC3299A needs EEPROM 93C56/66 in PCMCIA LAN CARD to reduce part cost. Physical media 10BaseT, AUI interface are fully automatic detection. LED driver for Link and other activities are also provided.

    TC3299A is designed for conventional PCMCIA LAN CARD with AUI cable connecting to external MAU. TC3299A provides both UTP and AUI interface for maximum flexibility.

    10BaseT functional block includes receiver and transmitter, collision, loopback, jabber and link integrity. The Polarity Detection/Correction blocks are also defined as in the standard.

    TC3299A uses analog Phase Lock Loop method for the Manchester encoding and the decoding method is specified by the IEEE 802.3 specification in the 10Mbit/sec transmission section. A collision detect translator and diagnostic Loopback Capability are also included in the TC3299A.

    Block Diagram

    Confidential.

  • TC3299APreliminary Data Sheet

    Table Of Contents Features ..............................................................................................................................................................1General Description............................................................................................................................................1Block Diagram.....................................................................................................................................................1Table Of Contents ...............................................................................................................................................2Pin Configuration ................................................................................................................................................31 Pin Description ............................................................................................................................................42 Functional Description ................................................................................................................................7

    2.1 Power On Configuration....................................................................................................... 93 Configuration Registers ............................................................................................................................11

    3.1 EPCC Core Registers ........................................................................................................ 124 Absolute Maximum Ratings......................................................................................................................255 Standard Test Conditions..........................................................................................................................256 D.C. Characteristics................................................................................................................................257 Physical Dimensions.................................................................................................................................26

    Confidential. 2/26 August 27, 20003Copyright 2003, IC Plus Corp. TC3299A-DS-R30

  • TC3299APreliminary Data Sheet

    Pin Configuration

    1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25

    81

    82

    8384

    85

    86

    87

    88

    89

    90

    91

    92

    9394

    95

    96

    9798

    99

    100

    WE*

    SA0

    SA1

    SA2

    SA3

    SA4

    SA5

    SA6

    SA7

    SA8

    SA9

    ACLED

    GND

    NC

    DI

    DO

    NC

    NC

    VCC

    CE1*

    IOR*

    IOW*

    OE*

    REG*

    GND

    MA14MA3

    MA2

    MA1

    EECSSD15

    SD14

    SD13SD12SD11

    SD10

    SD9SD8

    GND

    IO16*

    INPACK*

    INT*

    VCC

    NCGND

    51525354555657585960616263646566676869707172737475

    VCOI

    CD+

    26

    27

    28

    29

    30

    31

    32

    33

    34

    35

    36

    37

    38

    39

    40

    41

    42

    43

    44

    45

    WAIT*

    SD0

    SD1

    SD2SD3

    SD4

    SD5

    SD6SD7

    RST

    VCC

    GNDTDLY+

    TD-

    TDLY-

    TD+

    RD+

    RD-AVDD

    RX+46

    47

    48

    49

    50

    RX-

    AGNDTX+

    TX-

    LLED76

    777879

    80

    MA7

    MA6MA5

    MA4

    VCC

    TC3299A100pin LQFP

    CD-

    X1

    MD1

    MA12

    MW*

    MA10

    MA9

    MA8

    MD0

    CS0*

    MR*

    MA0

    MA13

    MA11

    X2

    GND

    VCC

    MD7

    MD6

    MD5

    MD4

    MD3

    MD2

    Confidential. 3/26 August 27, 20003Copyright 2003, IC Plus Corp. TC3299A-DS-R30

  • TC3299APreliminary Data Sheet

    1 Pin Description

    Pin No. Symbol I/O Description ISA Bus Interface Pins 2-11 SA0-SA9 I These address signal lines of PCMCIA Bus are used to select a

    register to be read or written and attribute memory enable. 27-34 93-86

    SD0-SD7 SD8-SD15

    I/O I/O

    Register Access, with DMA inactive, SD0-SD7 pins are used toread/write register data. SD8-SD15 pins are invalid during this state.Remote DMA Bus Cycle, SD0-SD15 pins contain packet data.Direction of transfer is depended on Remote read/write.

    35 RST I Reset pin. RST is active high and placed EPCC in a reset modeimmediately. During falling edge, the EPCC controller loads theconfiguration from MD0-7, MA0-13.

    26 WAIT* O This pin is set low to insert wait states during Remote DMA transfer. 24 REG* I REG* is an active low input used to determine whether a lost access is

    to Attribute memory (The first 1K) or to common memory (above 1K). If REG* is set to low the access is to attribute memory, while REG* isset to high the access is to common memory. REG* is also assertedlow for all accesses to the TC3299A's IO Registers.

    21 IOR* I Read Strobe: Strobe from host to read internal registers or RemoteDMA read.

    22 IOW* I Write Strobe: Strobe from host to write internal registers or RemoteDMA write.

    23 OE* I Host memory read strobe. The attribute memory can be read whenOE* and REG* are both at low state. While for Common memory to be accessed, OE* should be set to lowstate and REG* should set to high state. OE* REG* Attribute Memory Low Low Common Memory Low High

    1 WE* I Host memory write strobe. After Power reset, if TC3299A is configuredto memory write enable, then 2 types of memories are written asdefined below: WE* REG* Attribute Memory Low Low Common Memory Low High

    96 INPACK* O Active low signal, asserted if the host access TC3299A internalregister or Remote DMA read cycle.

    95 IO16* O IO16* is driven by EPCC to support host 16 bits access cycle. 97 INT* O Interrupt:Indicates that the EPCC requires host attention after

    reception, transmission or completion of DMA transfer. 20 CE1* I Card enable 1, are active low signals driven by the host. These signals

    provide a card select based on an address decode (decode by thehost).

    Confidential. 4/26 August 27, 20003Copyright 2003, IC Plus Corp. TC3299A-DS-R30

  • TC3299APreliminary Data Sheet

    Pin No. Symbol I/O Description Memory Interface Pins 65-58 MD0-7 I/O When RST is inactive these pins can be used to access external

    memory. When RST is active configuration is loaded with the datavalue on MD0-MD7 pins.

    79-70 81 82-84, 69

    MA4-13 MA14 MA3-1, MA0

    I/O When RST is inactive These pins drive the memory address busduring DMA access cycle. When RST is active configuration is loadedwith the data value on MA0-MA13 pins.

    68 MR* O Memory Bus Read: Strobes data from the buffer memory into theEPCC via the memory data bus.

    67 MW* O Memory Bus Write: Strobes data from the EPCC into the externalbuffer memory via the memory data bus.

    66 CS0* O Buffer RAM chip select, active low. 85 EECS O EEPROM chip select. It is asserted when to access EEPROM. 16 DO I Connected to EEPROM data output pin. 15 DI O Connected to EEPROM data input pin.

    Pin No. Symbol I/O Description Clock interface Pins 54 X1 I Crystal or External Oscillator Input:20 MHz 55 X2 O Crystal Feedback Output:Used in crystal connection only.

    Pin No. Symbol I/O Description

    Network Interface Pins 41,39 TD+/- O 10BaseT differential transmit drivers. 38,40 TDLY+/- O 10BaseT wave predistortion contro

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