University of the Philippines Los Baños

College of Engineering and Agro-Industrial Technology Department of Electrical Engineering

Tele/Fax: +63 (49) 536-6031

EE 21 Problem Set

Transistor DC Biasing

Instructions: Solve each problem neatly and accurately. State any necessary assumptions (i.e. methods

used). Use yellow pad. Box final answers. Avoid cheating at all costs. Deadline for submission is on Feb. 6,

12nn at your instructor’s pigeon hole @ rm. 305.

1. (15 points) For the combination network to the right,

determine VE, ID, VS, VCE and VDS. Take β = 100 for the

BJT, IDSS = 6 mA and Vp = -6V for the FET.

2. (10 points) An enhancement-type MOSFET connected in

drain-feedback configuration has the following parameters:

VGS(Th) = 4 volts, VGS(on) = 7 V, ID(on) = 5mA. The circuit is

designed with VDD = 22 V, RG = 1MΩ, RD = 1.2kΩ and RS =

0.51kΩ. Determine IDQ, VGSQ, and VDS.

3. (10 points) Design a self-bias network using a JFET

transistor with IDSS = 8mA and VP = -6V to have a Q-point

at IDQ = 4mA using a supply of 14 V. In addition, set RD =

3RS.

4. (10 points) Determine IE, VC, and VCE for the circuit below.

5. (10 points) A BJT transistor inverter is used with a switch input Vi either 10 volts (ON) or 0 (OFF) and

VCC = 10 V. Solve for the required RB and RC to obtain the inversion process if β = 250 and ICsat = 10

mA. Set a saturation base current equal to 1.5 times that of the theoretical base current.

Figure 1. Combination network.