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CSE241: Instruction Level Architecture
• Base CPU/Memory Architecture• Registers• Fetch-Execute Cycle• Instructions• Addressing Modes
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Basic CPU Architecture
CPU
Control Path-instruction fetchand executionsequencing
Data Path-user registers
and ALU
MAR MDR
Memory Data Bus
Memory Address Bus
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CPU Divisions
• Control Path• responsible for instruction fetch and execution
sequencing
• responsible for operand fetch
• responsible for saving results
• Data Path• contains user registers
• contains ALU
• “executes” instructions
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Control Path Registers
• PC Program Counter
– points to the next instruction to be executed
– thus, it contains a memory address
• MAR Memory Address Register
– contains the address of the memory location for the current memory operation
• MDR Memory Data Register
– contains the data to be written to or the data read from the memory location in the current memory operation
• IR Instruction Register
– contains the current instruction being executed
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Memory OrganizationData is stored as sequences of bits
--basic grouping is the byte -- 8 bits
Bytes are grouped into words--words may be 2 (older), 4 (current) or 8+ (modern)bytes long
The byte is the basic unit for addressing memory.However, our life will be simplified if we adopt the wordas the basic unit.The size of memory (almost always in bytes) is usually given by
S = 2p, where p = word size of machine(but this may be machine dependent)
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Memory Organization
• Word size = 16, memory size = 65536 (64KB)• Word size = 20, memory size = 1048576 (1MB)• Word size = 32, memory size = 4294967296
(4GB)• Word size = 64, memory size = 1.844674407x1019
this is ? bytes?
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Memory Organization
MAR
MDR
512Recall:MAR contains the address of thememory location addressed
MDR either contains data to bewritten to that address, or dataread from that address
Memoryis viewedas an arrayof bytes.
Addressesstart at 0 andincrease by 1up to maximumsize
01
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Memory operations
• Memory Read
– Place address of memory location to be read into MAR
– Issue a Memory_Read command to memory
– Data read from memory is placed into MDR automatically (by control logic)
• Memory Write
– Place address of memory location to be written to into MAR
– Place data to be written into MDR
– Issue Memory_Write command to memory
– Data in MDR is written to memory automatically (by control logic)
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Fetch-Execute Cycle
• Basic machine cycle; repeats indefinitely• Do until halted
– Fetch instruction to be executed
– (Decode instruction)
– Fetch operands
– Point PC to next instruction to be executed
– Execute instruction
– Save result operand
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Instruction Types
• There are 4 basic instruction types (3 basic)– Data movement instructions
• these move but do not alter data
– ALU instructions
• these alter (operate upon) data
– Flow of Control instructions
• these sequence instructions
– Input-Output instructions
• these transfer data to and from the real world
• note that these may get classed as Data movement
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Operands
• Operands are the entities operated upon by instructions
• Operands may be stored in memory• Operands may be stored in CPU registers• Both memory and CPU registers have addresses• Specifying the address of an operand in an
instruction is called an addressing mode
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Instruction Types by Function (Examples)
• data movement– mov a,b a = b;
• ALU– add a,b a = a + b;
• sequencing– jsr label jump to the subroutine which starts at
label
• I/O– in r5, port read from io port “port” to register 5
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Instruction Types by Operands• As well as being distinguished by type, instructions can be distinguished by
the number of operands they have• Typically, instructions may have 3,2,1 or 0 operands• 3-operand instructions are almost always instructions which implement
binary operations e.g.,– add a,b,c a = b + c
• 2-operand instructions are like 3-operand instructions, but one operand serves as both a source and a destination, e.g.
– add a,b a = a+b• 1-operand instructions are instructions which only require one operand
– clr a a = 0• 0-operand instructions do not operate on operands e.g.
– hlt halt the computer
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Source and Destination Operands• An operand is called a source operand if
– it appears on the right-hand side of an expression
• e.g., add a,b meaning a = a + b– b is a source operand, as is a
• An operand is called a destination operand if– it appears on the left-hand side of an expression
• e.g., add a,b meaning a = a + b– a is a destination operand
• Some operands may be both source and destination operands (a above)
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Data encoding• Data (strings of bits) in a machine may represent
• unsigned integers
• signed integers
• instructions
• character data
• floating point data
• abstract data etc.
• addresses
• What any particular string of bits “means” depends on how that string of bits gets interpreted
• The same string of bits is interpreted as an address by the MAR, an instruction by the IR, or a floating-point number by the FPU.
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Instruction Encoding
• An instruction must encode– the instruction itself
– the (or a partial) address of its operand(s)
– the addressing mode used to generate the address of its operand(s)
• Instructions can be encoded in– a variable number of bytes
– a constant number of bytes
• this is machine-dependent
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Instruction-level architecture
• the architecture of the machine at this level consists of
– the instructions and addressing modes
– the user registers
• this is the “level” of the machine that an assembly-language programmer sees.
• It is the first “obvious” place where different machines can be seen to clearly differ
• Compare this to the “application program” architecture, as seen by (say) a C++ programmer; how different is a Pentium to a PowerPC at this level (discount the different OSs)
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Basic Addressing Modes• There are five basic addressing modes
– Immediate addressing• the instruction contains the operand itself
– Register addressing• the instruction refers to a register which contains the operand
– Direct addressing• the instruction contains the address of the operand
– Indirect addressing• the instruction contains the address of the address of the
operand– Indexed addressing
• the instruction contains a value to be added to an index register to give the address of the operand
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Simple Model
• Suppose we consider only 1-operand instructions
• Suppose each instruction occupies 2 32-bit words
• The first word identifies the instruction (and addressing mode)
• The second word gives the operand address
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Direct AddressingBefore After
clear344786
97344786 0value in secondword is direct addressof operand; value inlocation 344786 isoperand
344786
memory
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Indirect Addressing
clear344786
96344786 96value in secondword is indirect addressof operand; value inlocation 344786 is addressof operand
344786
memory
96 96-182 0
Before After
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Indexed Addressing
clear indexed R3100
R3
51296 0
+=612
612 612
Before After
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Mixed modes? Indexed indirect?
• It is possible to mix addressing modes• We could define an indexed indirect• But note that we could have two ways of
implementing this• indexing before indirection
• indexing after indirection
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Indirect Indexed mode (preindexing)
clear indexed R3100
R3
51296 96
+=612
612 612
96 323 96 0
this is the address of theaddress of the operand
Before After
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Indirect Indexed Mode (postindexing)
clear indexed R3100
R3
512
+=1024
this is the address of the operand
100
1024
512
-192
512
0
Before After
