Microcontroller multi-core Architecture: A real world device solving real world problems.
NXP Microcontrollers ARM User Conference Birmingham, UK 16 May , 2012
NXP is a leader in ARM Flash MCUs
Clear strategy: 100% focus on ARM
Top performance through leading technology & architecture
Design flexibility through pin- and software-compatible solutions
– Scalable memory sizes – Widest range of peripherals
Unlimited choice through complete families for multiple cores
Cortex
M4 Cortex
M3 Cortex
M0
ARM7
ARM9
8051
32-bit
16-bit
8-bit
NXP Changing Microcontroller Landscape
DSP
cost performance
Very low-end 8b e.g. 6-8 pin not planned
High-end DSP/MPU not
planned
ARM Cortex-M Continuum
Cortex-M4 Cortex-M3 Cortex-M0
Breaking through traditional boundaries of 8b, 16b, 32b and DSP
The ONLY vendor that offers the full range of ARM Cortex-M microcontroller families
Binary and tool compatible
Cortex-M Processors: Binary Compatible
COMPANY CONFIDENTIAL
Cortex-M0 Up to 50MHz
Cortex-M3 Up to 180MHz
Cortex-M4 Up to 204MHz
Rapidly growing family of Cortex-M microcontrollers For more information: www.nxp.com/microcontrollers
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LPC1100
LPC1200
LPC1300
LPC1700
LPC1800
LPC4300
Best-in-class dynamic power consumption
Memory options up to 128k flash
USB solution, incl. on-chip USB drivers
High-performance with USB, Ethernet, LCD, and more
Memory options up to 1MB flash, 200k SRAM
High performance M4/M0 DSC with advanced peripherals
LPC40xx High-performance M4 with USB, Ethernet, LCD, and more
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LPC4300 Dual-Core MCU
Introduction to NXP and Cortex-M4 based LPC4300
More than one processor why? – Symmetric – Asymentric
Asymmetric topologies – Bus infrastructure – Resources
Communication – Hardware – Software
Asymmetric Applications
Debugging
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NXP Microcontrollers
Cortex-M4, LPC4300 NXP Cortex-M4, introducing multi-core processing to microcontroller and DSP applications
– Cortex-M4 based Digital Signal Controller featuring a highly flexible Cortex-M0 subsystem
– Unique configurable peripherals especially suitable for motor control, solar inverter, digital power and audio applications
+ = LPC4300
Processing Application
Audio/Image Processing
Control Algorithm+ = Solution!
Real Time Control
Peripheral Control
Protocol Emulation
Cortex-M0Cortex-M4
Digital Multicore award for NXP LPC4000 dual
core microcontroller design
Pin/Peripheral Compatible
Introducing the LPC4300 Family
Cortex-M4 based Digital Signal Controller
Cortex-M0 peripheral sub-system with dedicated configurable ‘smart’ I/O and event handling
Up to 1 MB Flash – Dual-Bank Flash provides safe in-
application programming (IAP)
Large SRAM: up to 264 KB SRAM
SPI Flash Interface with four lanes and up to 40MB/s data transfer rate.
State Configurable Timer Subsystem
Serial GPIO (SGPIO)
Two High-speed USB 2.0 interfaces. An on-chip High-speed PHY
– 10/100 Ethernet MAC – LCD panel controller (up to 1024H × 768V) – Two 10-bit ADCs and 10-bit DAC at 400ksps – Eight-channel General-Purpose DMA
(GPDMA) controller – Motor Control PWM – Quadrature Encoder Interface – 4x UARTs, 2x I2C, 2x I2S, CAN 2.0B, 3x
SSP/SPI – Smart card interface – Up to 146 general purpose I/O pins
LPC4300
Cortex-M4 LPC1800 Cortex-M3
LPC4300
LPC4300 Part Numbers
Part# Flash Total Flash A Flash B SRAM LCD Ethnt
HS USB
Max Freq Package
LPC4350 0 KB 0 KB 0 KB 264 KB Y Y 2 204 BGA256, BGA180, LQFP208 LPC4330 0 KB 0 KB 0 KB 264 KB Y 2 204 BGA256, BGA180, BGA100, LQFP144 LPC4320 0 KB 0 KB 0 KB 200 KB 1 204 BGA100, LQFP144 LPC4310 0 KB 0 KB 0 KB 168 KB 204 BGA100, LQFP144
Part# Flash Total Flash A Flash B SRAM LCD Ethnt
HS USB
Max Freq Package
LPC4357 1 MB 512 KB 512 KB 136 KB Y Y 2 204 BGA256, BGA180, LQFP208 LPC4353 512 KB 256 KB 256 KB 136 KB Y Y 2 204 BGA256, BGA180, LQFP208 LPC4337 1 MB 512 KB 512 KB 136 KB Y 2 204 BGA256, BGA180, BGA100, LQFP144 LPC4333 512 KB 256 KB 256 KB 136 KB Y 2 204 BGA256, BGA180, BGA100, LQFP144 LPC4327 1 MB 512 KB 512 KB 136 KB 1 204 BGA100, LQFP144 LPC4325 768 KB 384 KB 384 KB 136 KB 1 204 BGA100, LQFP144 LPC4323 512 KB 256 KB 256 KB 104 KB 1 204 BGA100, LQFP144 LPC4322 512 KB 512 KB 0 KB 104 KB 1 204 BGA100, LQFP144 LPC4317 1 MB 512 KB 512 KB 136 KB 204 BGA100, LQFP144 LPC4315 768 KB 384 KB 384 KB 136 KB 204 BGA100, LQFP144 LPC4313 512 KB 256 KB 256 KB 104 KB 204 BGA100, LQFP144 LPC4312 512 KB 512 KB 0 KB 104KB 204 BGA100, LQFP144
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Asymmetrical Dual Core
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Symmetric processing
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Core 1
Cache
Core 2
Cache
Improved processing performance by distributing work load across N processors of the same type
Complex – Cache Coherency – Requires OS support
Amdahl's law ( can’t get 1/N speed up)
Communication limitations as the number of cores increase
– Hardware – Software
Program Memory
Asymmetric processing
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Core 1 Core 2
Not intended to distribute 1 task over multiple cores
Intended to process different applications
Separate program resource per core
Specialized OS not required
Simple hardware for processor communication
Program Memory Program Memory
M series microcontroller cores
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Cortex M4
Cortex M3
Cortex M0
Thumb Only No hardware divide 0.9 DMIPS/MHz
Thumb 2 Hardware Divide 1.25 DMIPS/MHz
Thumb 2 DSP support 1.25 DMIPS/MHz
Asymmetric Implementation
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Cortex M4 Cortex M0
Cortex M4 with DSP extensions Including FPU for computation
Cortex M0 for control and communication
Program Memory Program Memory
Simple IPC (inter-processor communication)
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SRAM
HOST_MSG_BUFFER
Cortex M4 Cortex M0
Read Pointer
Write Pointer
Write Pointer
Read Pointer
SRAM
HOST_CMD_BUFFER
Interrupt
Interrupt
AHB
TXEV
TXEV
CREG
CREG
NVIC
NVIC
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AHB master regs
AHB Matrix
EMUL
ATIO
N TR
ACE
MODU
LE
ARM Cortex-M4 or M3
TEST/DEBUG INTERFACE USB2.0
HS Host/Device
Ethernet 10/100 MAC
S-bus
AHB slaves
SPIFI
SRAM 72kB
ROM64kB
I-bus
LCD controller
ETM
c1c4
SDIO controller
D-bus
c2c3
USB2.0 HS OTG/
Host/Device
DMA controller
2x
M0 sub-system
adap
ter
adapterAPB
slaves4
adapterAPB
slaves5
adapterAPB
slaves3
adap
ter
adapter
SRAM 128kB
SRAM 32kB
SRAM 32kB
State Cfg Timer
External Memory controller
adapterAPB
slaves2
adapterAPB
slaves1
Adapter
Bus Master
Bus Slave
Memory
VBATVDD
VSS
Clock Generation, Power Control,
and otherSystem Functions
Clocks and Controls
RS
T
Xta
lin
Xta
lout
X32
kin
X32
kout
VDDA
JTAG interface Debug Port
Ethernet PHY
interfaceUSB
interface
LCD interface SDIO
interfaceULPI
USB FS
HS GPIO
12b ADC
FPU ARM
Cortex M0
AES
VSSA
LPC4300 Bus Matrix
Contiguous Mode
LPC4300 Flash Banks
Two 512K byte banks of flash memory.
Can be used as a single 1M byte memory area.
Enhanced memory controller and 256-bit wide interface allows operation at up to 204MHz.
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Flash B
Flash A
Dual Mode
Flash B
Flash A
LPC4300 Memory Model
M4 and M0 can execute from FLASH without contention
M0 can execute from its own RAM (4 options)
ROM written in thumb mode means both M4 and M0 can use ROM code
M4 MPU can be used to protect M0 code space.
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Cortex-M0 Subsystem: Bus Matrix Connections AH
B Ma
trix
CORTEX-M4 204MHz
CORTEX
-M0 204MHz
SRAM 128 KB
ROM S I D
72 KB
External Memory Ctrl
32 KB
16 KB + 16 KB
Maximum performance is obtained when the code for each processor is located in different memories.
• Cortex-M4 1.25 DMIPS/MHz
• Cortex-M0 0.9 DMIPS/MHz
Both Cortex-M4 & Cortex-M0 can run at 204 MHz
LPC4300
LPC4300 Boot sequence
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ROM M0
FLASH Asd
M4 Starts up first
FLASH A M0 prep
code
M4 code execution
from flash A
M0 IPC Loaded
Reset
M0 code Execution
from flash B Optional RAM execution
Application Code
Boot Code
LPC4300
Cortex-M0 Subsystem: Audio Processing
Cortex-M4: Full power devoted to Audio processing
Cortex-M0: Handles the hardware control – I2S & USB
Cortex-M4 Cortex-M0
I2S
USB
LPC4300
Cortex-M0 Subsystem: Audio Processing AH
B Ma
trix
CORTEX-M4 204MHz
CORTEX
-M0 204MHz
GPDMA
SRAM 128 KB
ROM S I D
72 KB
Ethernet
USB0 USB1
HS PHY FS PHY + ULPI
External Memory Ctrl
LCD SD/ MMC
0 1
32 KB
16 KB + 16 KB
AHB Peripherals
APB Peripherals
LPC4300
Cortex-M0 Subsystem: Motor Control
LPC4300
Cortex-M4 Cortex-M0
Cortex-M4: Single shunt Field Oriented Control (FOC)
Cortex-M0: Receives control commands via CAN interface
SCT CAN Command
LPC4300
Cortex-M0 Subsystem: Motor Control AH
B Ma
trix
CORTEX-M4 204MHz
CORTEX
-M0 204MHz
GPDMA
SRAM 128 KB
ROM S I D
72 KB
Ethernet
USB0 USB1
HS PHY FS PHY + ULPI
External Memory Ctrl
LCD SD/ MMC
0 1
32 KB
16 KB + 16 KB
AHB Peripherals
APB Peripherals
LPC4300
LPC4300 Debug view
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Both cores are on the same JTAG chain
Treated as separate cores
Full Trace for M4
www.lpcware.com