Transcript
Page 1: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

Introductory Digital and Analogue Electronics A collection of examination problems 1991 - 2010

Magnus Danielsen (Ed.)

Contributions:

Magnus Danielsen 1991-2010 Benadikt Joensen 2008-2010

NVDRit 2010:08

Page 2: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

Heiti / Title Introductory Digital and Analogue Electronics A collection of examination problems 1991 - 2010

Høvundar / Authors Magnus Danielsen (Ed.) Contributions: Magnus Danielsen 1991-2010 Benadikt Joensen 2008-2010

Ritslag / Report Type Teaching Material/Undirvísingartilfar

NVDRit 2010:08 © Náttúruvísindadeildin og høvundurin

ISSN 1601-9741 Útgevari / Publisher Náttúruvísindadeildin, Fróðskaparsetur Føroya

ústaður / Address Nóatún 3, FO 100 Tórshavn, Føroyar (Faroe Islands) Postrúm / P.O. box 2109, FO 165 Argir, Føroyar (Faroe Islands)

@ +298 352550 +298 352551 [email protected]

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Contents: Digital Electronics and Microprocessors:

March 2009 Electronics :

December 2008 Digital Electronics (incl. basic analogue electronics):

January 2006 January 2005 January 2003 July 2002 August 2001 January 2001 January 1999 January 1997 July 1995 January 1995 Maj 1993 January 1993 April 1991

Abstract, English Introductory Digital and Analogue Electronics A collection of examination problems 1991 – 2010 The problems have been used for examinations in the courses “Digital Electronics” (incl. basic analogue electronics), “Electronics”, and “Digital Electronics and Microprocessors” for students in BSc Electrical Engineering, and in BSc ICT-Engineering. Abstract, Faroese Innleiðandi digitalur og analogur elektronikkur Savn av próvtøkuuppgávum 1991-2010 Uppgávurnar hava verið settar til próvtøku í skeiðunumm í ”Digitalur elektronikkur”(ið eisini umfatar grundleggjandi analogan elektronikk), ”Elektronikkur” og “Digitalur elektronikkur og mikroprosessorar” fyri studentum í BSc ravmagnsverkfrøði, og í BSc KT-verkfrøði.

Page 4: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

FRÓÐSKAPARSETUR FØROYA Page 1 of 5 pages (University of the Faroe Islands) Examination: Friday 13 March 2009, time: 9.00 – 13.00 Subject: Digital electronics and microprocessors (Digitalur elektronikkur og mikroteldur) Helping material permitted: All usual, including books. Assessment: The solutions will be assessed as a whole Problem 1. A computer delivers a string of hexadecimal digits representing two commands in a programme: 424547494E 454EC4 The contents of each pair of hexadecimal digits in the strings were intended to represent ASCII codes expanded with a leading zero. However one of the strings contains an error. 1.1 Determine which of the two strings contains an error, and explain why. Translate the correct string to the corresponding alphanumeric equivalent. Give a good suggestion for the intended alphanumeric equivalent of the erroneous string. Table 1: ASCII codes MSB LSB

000 001 010 011 100 101 110 111

0000 NUL DLE SP 0 @ P ` p 0001 SOH DC1 ! 1 A Q a q 0010 STX DC2 “ 2 B R b r 0011 ETX DC3 # 3 C S c s 0100 EOT DC4 $ 4 D T d t 0101 ENQ NAK % 5 E U e u 0110 ACK SYN & 6 F V f v 0111 BEL ETB ‘ 7 G W g w 1000 BS CAN ( 8 H X h x 1001 HT EM ) 9 I Y i y 1010 LF SUB * : J Z j z 1011 VT ESC + ; K [ k 1100 FF FS , < L \ l | 1101 CR GS - = M ] m 1110 SO RS . > N ↑ N ~ 1111 SI US / ? O – o DEL

Continues next page

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Page 2 of 5 pages Problem 2. In fig. 2.1 is shown a VHDL programme of a state machine. Analyse this state machine answering the following questions: 2.1 How many states are in the machine, and mention their names.

Mention all input signals. Explain their function and significance for the state machine. Draw a state diagram, including indications of the control inputs.

Modify the state machine, adding a new control input y, so that the machine can be directed to run in either the original sequence, when y=0, or in the reverse sequence, when y=1. For this purpose answer the following questions: 2.2 Write additional statements to the VHDL programme, and show where in the programme

they shall be placed, so that the state machine can run in the original or the reverse sequence.

2.3 Redraw the state diagram for the modified state machine. (Hint: this question don’t require solution of question 2.2)

Continues next page

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Page 3 of 5 pages Problem 3. The logic signals from two BCD logic circuits (BCD1 Logic and BCD2 Logic) are given as shown in fig. 3.1, and goes through a 74244 octal tri-state buffer to a D/A-converter. The 74244 is controlled from a 7400 logic gate. The actual BCD logics output values are shown in the figure. (Hint: BCD logic circuits refers to that the code on the output terminals are Binary Coded Decimal numbers) 3.1 Calculate the voltage at the output, Vout when the input control signal C is “High” and

“Low” respectively with the actual BCD logics output values as shown in the figure (BCD1 = 1001, and BCD2 = 0011) . Explain shortly what the function of the circuit is.

The 74244 is considered to be replaced by a 74LS244, a 74HC244 or a 74HCT244. 3.2 Explain some advantages with these replacements.

Explain the disadvantages with these replacements, if any.

Continues next page

− 15V

5V

R1 =5kΩ

R2= 5kΩ

Ref (+) Ref (−)

DAC 0808 or MC1408

VEE

MSB A1 A2 A3 A4 A5 A6 A7 A8 LSB

5V VCC

− +

R3 =16kΩ

Fig. 3.1

Vout

7400 C

BCD2 Logic 74LS90

MSB LSB

”0” ”0” ”1” ”1”

74244 __ __

OEa OEb

Ib3 Ib2 Ib1 Ib0

BCD1 Logic 74LS90

”1” ”0” ”0” ”1”

Ia3 Ia2 Ia1 Ia0

MSB LSB

Ya3 Ya2 Ya1 Ya0

Yb3 Yb2 Yb1 Yb0

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Page 4 of 5 pages

Problem 4.

In fig. 4 a device is shown, which converts a BCD-number (Binary Coded Decimal number) with the bits ABCD, where A is the MSB (most significant bit), to a 2421-code with the bits UVXY (the weights of the bits for this code are 2,4,2,1). The non-occurring combinations of the ABCD bits are supposed to result in don’t care. The 2421-code is given in the table:

Decimal integer

BCD- code word

2421- code word

A B C D U V X Y 0 0 0 0 0 0 0 0 0 1 0 0 0 1 0 0 0 1 2 0 0 1 0 0 0 1 0 3 0 0 1 1 0 0 1 1 4 0 1 0 0 0 1 0 0 5 0 1 0 1 1 0 1 1 6 0 1 1 0 1 1 0 0 7 0 1 1 1 1 1 0 1 8 1 0 0 0 1 1 1 0 9 1 0 0 1 1 1 1 1

4.1 Find logical minimum sum of products expressions for U, V, X, and Y as functions of

A, B, C, and D. Draw logical circuits diagrams. 4.2 Find logical minimum product of sums expressions for U, V, X, and Y as functions of

A, B, C, and D. Draw logical circuit diagrams. (Hint: use Karnaugh maps)

Continues next page

MSB LSB

A B C D

U V X Y

Fig. 4

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Problem 5. Page 5 of 5 pages A synchronous sequence machine shown in fig. 5.1 consists of 3 D flip-flops with clear and set signals D0 D1 D2R , R , R , and D0 D1 D2S ,S ,S respectively, and a clock signal CLK inputs. In addition the circuit contains 2 XOR gates, and 1 AND gate. The outputs Q2 Q1 Q0 run freely through a sequence of values interpreted as binary numbers (Q0 is LSB), starting with Q2 Q1 Q0 = 000. 5.1 Write up a time sequence for the inputs 2 1 0D , D , and D , the outputs 2 1 0Q ,Q , and Q , and

the output X of the AND gate. (Use e.g. a table shown in fig. 5.3). Which type of counter is it, and how many states are in a period. Which values must D0 D1 D2R , R , R , and

D0 D1 D2S ,S ,S have for free running flip-flops. Now the counter shall be modified using a combinational circuit as shown in fig. 5.2, so that it will run through the five binary states 2 – 6, corresponding to 2 1 0Q ,Q ,Q 010 011 100 101 110= . Notice: If question 5.1 was not answered, its result to be used in the next question can be taken to be a usual binary up-counter. 5.2 Determine the logic equations for D0 D1 D2R , R , R , and D0 D1 D2S ,S ,S as a function of the

D flip-flop outputs 2 2 1 1 0 0Q , Q , Q , Q , Q , and Q . Draw the corresponding logic circuit. Does the machine have glitches.

END

0Q 0

1Q 0

2Q 0 X

1D

2D

0D Fig. 5.3Fig.5.2

__ RD0

__ SD2

Combinational Logic Circuit

Q0 Q1 Q2 __ Q0

__ Q1

__Q2

__ RD2

__ RD1

__ SD0

__ SD1

Q0Q1 Q2

Fig.5.1

CLK

D0 D1 D2

X

__Q0

__ Q1

__Q2

__ SD0

__ SD1

__ SD2

__ RD0

__ RD1

__ RD2

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FRÓÐSKAPARSETUR FØROYA Page 1 of 6 pages (University of the Faroe Islands) Examination: Friday 19 December 2008, time: 9.00 – 13.00 Subject: Electronics (Elektronikkur) Helping material permitted: All usual, including books. Assessment: The solutions will be assessed as a whole

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Problem 2

A B C D g0 0 0 0 00 0 0 1 00 0 1 0 10 0 1 1 10 1 0 0 10 1 0 1 10 1 1 0 10 1 1 1 01 0 0 0 11 0 0 1 11 0 1 0 X1 0 1 1 X1 1 0 0 X1 1 0 1 X1 1 1 0 X1 1 1 1 X

The table is the truth table for the g-segment in aBCD-to-7-segment decoder.

2.1 Draw a Karnaugh map for the truth table andfind the minimal sum of products expression andthe minimal product of sums expression for theg segment.

2.2 Draw a circuit with only NOT- and NAND-gates that will realize the truth table.

2.3 Draw a circuit with only NOT- and NOR-gatesthat will realize the truth table.

Page 2 of 6 pages

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Problem 3.

In fig. 3.1 a sequential circuit is shown composed of four D-flip-flops, one exclusive OR gate, and one exclusive NOR gate. The D-flip-flops are clocked synchronously with the clock frequency f = 1 Hz. The initial condition of the circuit is Q3 Q2 Q1 Q0 = 0 0 0 0. 3.1 Draw a time sequence of Q3 Q2 Q1 Q0 as a function of time.

Determine the number of states in the period of the sequence, and the states (i.e. combination of Q3 Q2 Q1 Q0) that are not present in the sequence.

(Use the sheet in the appendix to problem 3).

Fig. 3.1

Q0 Q1 Q2 Q3 D0 D1 D2 D3

X

Page 3 of 6 pages

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Appendix to problem 3

CLK

X

Q0

Q1

Q2

Q3

time

D0

Page 4 of 6 pages

magnusd
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Problem 4.

In fig.4.1 the pulsed output volage Uin from a digital control circuit IC controls a motor M using a bipolar transistor as a switch. The motor M has an equivalent resistance R=10Ω in series with an equivalent inductance L=2H. The time variation of Uin is shown in fig.4.2. The power supply voltage is E = 12 volt. The bipolar transistor functions as a perfect switch, being open circuit for the base voltage UBE < 0.7 V, and short circuit for UBE > 0.7 V. The diode shown is taken to be perfect, having zero voltage across the terminals when forward biased, and conducting zero current when reverse biased. 4.1 Determine the time constants involved in the intervals of times when Uin is low

(2V) and when Uin is high (12V) respectively. Explain, what is the condition for the time constants and switching intervals to give a nearly constant current in the motor.

4.2 Draw a curve of the voltage U across the motor as a function of time, using the

time variation of the control voltage Uin as shown in fig.4.2. 4.3 Calculate the average current in the motor. 4.4 Taking R2 = 1 kΩ, calculate the range of values (minimum and maximum) for R1

necessary for the transistor to function as a perfect switch.

time (ms)

Uin 12 V 2V

0 1 2 3 4 5 6 7

Fig.4.2

L=2H

+ U −

R=10Ω

IC

Fig.4.1

M

+ Uin −

+ UBE −

R1

R2

Page 5 of 6 pages

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Page 2 of 6 pages

Page 6 of 6 pages

Page 15: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

FRÓÐSKAPARSETUR FØROYA Page 1 of 3 pages (UNVERSITAS FÆROENSIS) Examination: Wednesday 4 January 2006, time: 9.00 – 13.00 Subject: Digital electronics (Digitalur elektronikkur) Helping material permitted: All usual, including books Assessment: The solutions will be assessed as a whole Problem 1. The following three numbers X, Y and Z are given as hexadecimal numbers: X = X16 = F3.B Y = Y16 = 2A9.E Z = Z16 = D3B.5 1.1 Translate X16 ,Y16 and Z16 to binary numbers X2 ,Y2 and Z2 1.2 Calculate, using binary two complement representation for the numbers the results of

V = X2 + Y2 + Z2 , U = X2 + Y2 − Z2 , and W = X2 − Y2 − Z2 , and determine the minimum number of bits necessary in each case to avoid overflow in calculating V and U. Problem 2. V X Y Z

0 0

0 1

1 1

1 0

0 0

1

d

1

1

01

d

d

0

0

1 1

0

0

0

1

1 0

1

1

0

1

Fig.2 Fig.2 shows a Karnaughmap for a logic expression G filled out with logic 0’s (zeros), logic 1’s (ones), and d’s (don’t care) values for the input variables V,X,Y, and Z. 2.1 Show that the minimal sum of product expression for G = G1, using don’t care

combinations most efficiently can be written as 1G V' Z' Y ' Z ' V X ' Y= + +i i i i

Draw a logic circuit for the logic expression G1, using AND-, OR-, and NOT-gates. (Continues next page)

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Page 2 of 3 pages

2.2 Show that static-1 hazard(s) exixts for the minimal sum of product G1. Draw the

additional logic circuit which removes the static-1 hazard(s) 2.3 Find a minimal product of sum expression for G = G2, using don’t care combinations

most efficiently. 2.4 Explain whether the two expressions G1 and G2 are identical or not, and why this is so

(give reasons for the answer). Problem 3. R1

Fig. 3

I

t = 0 R2

R4 R5

C

R3

+ −

E

+

V(t) −

The circuit in fig.3 has a switch, a voltage generator E, a capacitance C, and five resistors R1, R2, R3, R4, and R5 with the values E = 10 V C = 5 µF R1 = 400 Ω R2 = 1 kΩ R3 = 600 Ω R4 = 750 Ω R5 = 1 kΩ The switch is open for t < 0, but is closed for all times t ≥ 0. 3.1 Determine the current I in the resistor R5 for all times t. 3.2 Determine the value of the voltage V(t) across the capacitance C

at the times t = 0−, t = 0+ , and t = ∞. 3.3 Determine the time constant τ for the circuit. 3.4 Draw a sketch of V(t) as a function of time t.

(Continues next page)

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Page 3 of 3 pages

Problem 4.

State memory Next state logic

Fig.4

A digital clocked synchronous state – machine is intended to shift in two different sequences of states with periodic cycles of different lengths, one created when the input parameter X = 0 and the other is created, when X = 1. A designer has designed a circuit as a Moore Machine as shown in the figure 4. The function of the circuit remains to be checked by an analysis. The logic circuit contains three D flip-flops (“state memory”), and a combinational logic circuit (“next state logic”) containing a number of AND-, OR-, and NOR-gates. 4.1 Determine the excitation equations for the next state logic, i.e. D0, D1, and D2. Show that D0 can be expressed by ( )0 0 1D X Q ' X ' Q Q= +i i 2

2

(Hint: Q is the exclusive NOR function.) 1 Q 4.2 Write up a transition table.

Define state names, and write up the corresponding state table. 4.3 Draw the state diagram for the circuit. Identify the states in the two periodic cycles, and determine the length of the two periodic cycles. . END

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FRÓÐSKAPARSETUR FØROYA Page 1 of 4 pages (UNVERSITAS FÆROENSIS) Examination: Wednesday 5 January 2005, time: 9.00 – 13.00 Subject: Digital electronics (Digitalur elektronikkur) Helping material permitted: All usual, including books Assessment: The solutions will be assessed as a whole Problem 1 The logic expression F is given as a function of the logic variables V, X, Y and Z by

F = ΣΣ V,X,Y,Z (1,3,4,5,7,9,12) + d(6,13,14) In the following questions the don’t care states shall be exploited most efficiently (hint: use a Karnaughmap). 1.1 Find a minimum sum of products expression for F=F1. 1.2 Find a minimum product of sums expression for F=F2. 1.3 Draw a logic circuit of one of the logic expression for F, using AND-gates, OR-

gates, and NOT-gates, and using V,X,Y,Z as input variables.

(Continues next page)

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Page 2 of 4 pages Problem 2

In fig.2.1 a CMOS circuit is shown with 4 inputs A,B,C and D, and one output Z. 2.1 Write up the function table for the states of the transistors Q1, Q2, Q3, Q4, Q5, Q6, Q7, and

Q8, together with the output value Z as a function of the inputs. 2.2 Determine the logic function for Z = Z(A,B,C,D)

(Continues next page)

Z

A B C D

Q2

Q1

Q3

Q5 Q7

Q4 Q6

Q8

5 volt

0 volt Fig.2.1

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Page 3 of 4 pages Problem 3 In fig.3.1 a logic circuit is given consisting of three D flip-flops (“state memory”), and a combinational logic circuit (“next state logic”) containing AND-, OR-, NOT-, NAND-, NOR-, and Exclusive-OR-gates. There is one external input variable X (The circuit is a Moore machine with no output logic.) 3.1 Determine the excitation equations for the next state logic, i.e. D2, D1, and D0. 3.2 Write up a transition table.

Define state names, and write up the corresponding state table. 3.3 Draw the state diagram for the circuit.

Starting in the state Q2 Q1 Q0 = 0 0 0, find, e.g. from the state diagram, the lengths of the periods (i.e. number of states in a period) in the two cases defined by X=0, and X=1, respectively. Determine the missing states in each case. .

(Continues next page)

Q0 Q1 Q2

D0 D1 D2

State memory Next state logic

Fig.3.1

CLK

X

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Page 4 of 4 pages Problem 4 In figure 4.1, a CMOS inverter has the input voltage Vin(t). The input is considered low for Vin(t) ≤ 1.5 volt, and high for Vin(t) > 1.5 volt (this is an idealized case for a CMOS). Further it is given for the used MOS – FET transistors in the CMOS inverter that For the n-channel transistor: the “on resistance” is Rn,on = 2 kiloohm (kΩ), and the “off-resistance Rn,off = 600 kiloohm (kΩ) For the p-channel transistor: the “on resistance” is Rp,on = 1 kiloohm (kΩ), and the “off-resistance Rp,off = 500 kiloohm (kΩ) The output voltage V(t) of the CMOS inverter is used as input to a digital load circuit shown in the figure 4.1 as a “dashed box”. The input of the digital load circuit is considered low for V(t) ≤ 1.5 volt, and high for V(t) > 1.5 volt. The digital load circuit seen from the input is equivalent with a RC circuit, also shown in the figure, consisting of a resistance R, and a capitance C in parallel. It is given that: R = 10 kiloohm (kΩ) and C = 100 nanofarad (nF) It is now given that the input signal varies with time t as

≥<

=0tforvolt0

0tforvolt4)t(Vin

Caused by this event the digital load circuit switches to a new state at the time t = td. 4.1 Determine the time constant ττ , the voltage V(0-), V(0+), and V(∞). 4.2 Determine an expression for V(t), and sketch V(t) as a function of the time t.

Calculate the time td (delay), when the digital load circuit switches to the new state. END

+ V(t) −

R C

Fig.4.1

+ Vin(t) −

5 volt

Digital load circuit

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FRÓÐSKAPARSETUR FØROYA Page 1 of 4 pages (UNVERSITAS FÆROENSIS) Examination: Friday 3 January 2003, time: 9.00 – 13.00 Subject: Digital electronics (Digitalur elektronikkur) Helping material permitted: All usual, including books Assessment: The solutions will be assessed as a whole

Problem 1 A logic expression G depending on the logic variables V, X, Y and Z is given by

G = ΠΠV,X,Y,Z (1,3,4,5,6,7,9,12) + d(13,14) In the following questions the don’t care states shall be exploited most efficiently (hint: use a Karnaughmap). 1.1 Find a minimum sum of products expression for G=G1. 1.2 Find a minimum product of sums expression for G=G2. 1.3 Draw a logic circuit of one of the logic expression for G, using AND-gates, OR-

gates, and NOT-gates, using V,X,Y,Z as input variables. 1.4 Determine whether G1 and G2 are equal and give identical results for all values of

the input variables V,X,Y,Z (give an explanation for the reasons for your answer). Do static 1-Hazard og static 0-Hazard exist in the two expressions found for G (give reasons for the answer)

(Continues next page)

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Page 2 of 4 pages

Problem 2

In fig.2. a logic circuit is given consisting of three D flip-flops (“state memory”), and a combinational logic circuit (“next state logic”) containing AND-gates and OR-gates. (The circuit is a Moore machine with no external input variable, and no output logic present.) 2.1 Determine the excitation equations for the next state logic, i.e. D0, D1, and D2. 2.2 Write up a transition table.

Define state names, and write up the corresponding state table. 2.3 Draw the state diagram for the circuit. . 2.4 In a time diagramme, where at the starting point Q0 Q1 Q2 = 0 0 0, draw the time

variation for Q0 Q1 Q2 ,and D0 D1 D2. How long is the periodic cycle, and which states are missing in the period. Starting with the missing states, draw the time variations for the Q0 Q1 Q2 . (Use the sheet in the appendix for the drawing.)

(Continues next page)

Q0 Q0’ Q1 Q1’ Q2 Q2’

D0 D1 D2

State memory Next state logic

Fig.2

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Page 3 of 4 pages

Problem 3

In fig.3.1 is shown a circuit with an npn transistor with the collector current IC, the base current IB, the base-emitter voltage VBE, and the collector-emitter voltage VCE. The parameters for the transistor are given by:

− The base-emittervoltage VBE for the transistor in the conducting state (active or saturated) is taken to be VBE(on) = 0.6 volt .

− the current amplification factor β = 500 − the saturation resistance rC,sat = 40 ohm

Further it is given that The supply voltage ECC = 18 volt The resistance R1 = 500 ohm The resistance R2 = 2 kohm 3.1 Determine the maximum value for IB for which the transistor is active (it is for the

transistor being on the border between active and saturated state). Determine the corresponding value for the input voltage VB.

(Continues next page)

+

_ VBE

ECC

Fig.3.1

+

_ VCE

IB

IC

R1

IB

+ VB _

R2

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Page 4 of 4 pages Problem 4

In fig. 4.1 the operational amplifier in the circuit shown is ideal. The resistances and the capacitance are given by: R1 = 1 kiloohm R2 = 2 kiloohm R3 = 3 kiloohm R4 = 4 kiloohm C = 5 mikrofarad The ideal voltage generator E varies as a function of time as: E = -5 volt for t < 0 E = 5 volt for t õ0 4.1 Determine the values of the output voltage V(t) for the times t = 0 − , t = 0 + , and t = ∞.

Find the time constant ττ . 4.2 Find an expression for the output voltage V(t), and draw V(t) as a function of time t in

the interval - ∞ < t < + ∞. END

Fig.4.1

C

Page 26: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

Appendix

Clock Q0 Q1 Q2 D0 D1 D2

Page 27: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

FRÓÐSKAPARSETUR FØROYA Page 1 of 4 pages (UNVERSITAS FÆROENSIS) Examination: Monday 15 July 2002, time: 9.00 – 13.00 Subject: Digital electronics Helping material permitted: All usual, including books Assessment: The solutions will be assessed as a whole

Problem 1 A logic expression H depending on the logic variables A, B, C and D is given by

H = (A’+B’+C) ⋅⋅ (A+C+D’) ⋅⋅ (A+B’+C’) ⋅⋅ (A’+C’+D’) 1.1 Draw a logic circuit of the logic expression H. 1.2 Fill out a Karnaughmap for the logic expression H.

Show that “static-0 hazards”are found in the function H, and indicate in the Karnaughmap, where they are found.

1.3 Add factors to the logic expression H such that all “static-0 hazards” are removed, and draw a logic circuit of the modified function.

(Continues next page)

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Page 2 of 4 pages

Problem 2 In fig.2.1 two D flip-flops, and a combinational logic circuit (“next state logic”) are used to construct a synchronous “3-counter” . The D flip-flops have the outputs Q1, and Q0 and their inverse. These are the same variables as the inputs to the “next state logic”. The counter is controled by an extra input logic variable X to the next state logic. When X=1 the counter outputs Q1, Q0 result in the following counting sequence Q1 Q0 = 00, 01,10, 00, 01, 10, 00 … with three independent states. When X=0, the counter outputs is reset to the state Q1 Q0 = 00. If the counter outputs have the values Q1 Q0 = 11 at the start of a sequence or by an accidential failure, it shall fall back to Q1 Q0 = 00 after the first coming clock pulse, and then continue its cycle as described above. 2.1 Construct the transition table for the counting sequences.

2.2 Draw a state diagram for the counter system in fig.2.1. . 2.3 Find the excitation equations for the “next state logic”, i.e. D1 , og D0 as functions

of Q1, Q1’ Q0, Q0

’, and X.

2.4 Draw a logic circuit diagram, for the “next state logic” that realizes D1, D0 , taking all the logic variables X, Q1 and Q0 , and their inverted values as given available on the input.

(Continues next page)

CLOCK

D0

D1

Fig.2.1

Q

Q

PR

CLR

CLK

D

Q1'

Q1

O

Q

Q

PR

CLR

CLK D

Q0'

Q 0

O

Q0'

Q0

Q1

Q1'

Next state logic X

State memory

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Page 3 of 4 pages

Problem 3

In fig.3.1 is shown a circuit with an npn transistor with the collector current IC, the base current IB, the base-emitter voltage VBE, and the collector-emitter voltage VCE. The parameters for the transistor are given by:

− The base-emittervoltage VBE for the transistor in the conducting state (activ or saturated) is taken to be VBE(on) = 0.6 volt .

− the current amplification factor β = 300 − the saturation resistance rC,sat = 0

Further it is given that The supply voltage ECC = 12 volt The resistance R1 = 500 kohm The resistance R2 = 1 kohm The resistance R3 = 1 kohm 3.1 Determine the values of IB , IC , and VCE .

(Continues next page)

+

_ VBE

+

_

VCE

R1

ECC

R2

Fig.3.1

IB

IC

R3

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Page 4 of 4 pages Problem 4

In fig. 4.1 the operational amplifier in the circuit shown is ideal. The resistances and the capacitance are given by: R1 = 3 kiloohm R2 = 6 kiloohm R3 = 6 kiloohm R4 = 5 kiloohm R5 = 50 kiloohm C = 2 mikrofarad The ideal voltage generator E varies as a function of time as: E = 0 volt for t < 0 E = 1 volt for t õ0 4.1 Determine the values of the output voltage V(t) for the times t = 0 − , t = 0 + , and t

= ∞. Find the time constant ττ . 4.2 Find an expression for the output voltage V(t), and

draw V(t) as a function of time t in the interval - ∞ < t < + ∞. END

Fig.4.1

C = 2µµF

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FRÓÐSKAPARSETUR FØROYA Page 1 of 4 pages (UNVERSITAS FÆROENSIS) Examination: Monday 20 August 2001, time: 9.00 – 13.00 Subject: Digital electronics Helping material permitted: All usual, including books Assessment: The solutions will be assessed as a whole Problem 1 In fig.1 the inputs and outputs of a combinational logic circuit are shown.The four input variables are A, B, C, and D, and denote binary number digits with A as the most significant bit (MSB), and D as the least significant bit (LSB) in the binary number ABCD. The input binary number ABCD is allowed to take on all values corresponding to the BCD-code (Binary-Coded Digital), i.e. all numbers in the range 0 to 9. A control output R = 1 indicates, whether ABCD exceedes the value 9. Otherwise R = 0. The circuit has 9 outputs indicating the level Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, and Q9, in addition to the control output R. The circuit is constructed with the intention to be a level indicator giving the logic value = 1 on a number of Q-output terminals equal to the value of the input number ABCD.

(Continues next page)

A B C D

Q1

Q2

Q3

Q4

Q5

Q6

Q7

Q8

Q9

R

Fig.1

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Page 2 of 4 pages

These requirements are more exactly described by: For all allowed numbers ABCD ≤≤ 9, we have : Qn = 0 for ABCD < n Qn = 1 for 1 ≤≤ n ≤≤ABCD R = 0 indicating, that the circuit receives allowed values at the inputs. For not allowed numbers, occationally occurring by a failure, ABCD > 9, we have: Qn = d (don’t care) R = 1 indicating that the circuit receives non-allowed values at the inputs. 1.1 Write up the truth table for the output variables Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9,

and R for all combination of input variables A, B, C, and D 1.2 Determine the minimized logic expressions (minimal product of sums, or minimal

sum of products) for Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, and R as functions of A, B, C, and D. (It is recommended to use Karnaugh map.)

1.3 Draw logic circuits resulting in Q1, Q2, Q3, Q4, Q5, Q6, Q7, Q8, Q9, and R as output

variables with A, B, C, and D as input variables.

Continues next page)

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Page 3 of 4 pages

Problem 2 Fig.2 shows a synchronous state-machine constructed by two D flip-flops, and a combinational logic circuit (“next state logic”). The D flip-flops have the outputs Q0, and Q1 and their inverse. The next state logic of the state-machine has the input variables Q0, and Q1, and their inverse Q0’, and Q1’, and in addition an extra input logic variable X. The logic variable X can have the values 0 or 1. 2.1 Determine the excitation equations and the transition equations for the circuit. 2.2 Construct the transition table, and the corresponding state table for the circuit. 2.3 Draw a state diagram for the circuit. 2.4 Draw a timing diagram for Q1, and Q0 as a function of time for the two sequences

corresponding to the values X = 0, and X = 1 respectively. It is given, that at the starting time t = 0, Q1 = Q0 = 0 (Use the attached sheet in appendix for the drawing).

(Continues next page)

0D

1D

0Q

'0Q

1Q

'1Q

Fig.2

Clock

X

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Page 4 of 4 pages

Problem 3 In fig.3 a circuit is given, where the voltage generator is constant E = 10 volt. For t = 0 the switch K opens, and stays open for all t > 0. The values of the resistors are R1 = 3 kohm, R2 = 2 kohm, R3 = 5 kohm. The capacitance is given by C = 2 µF. 3.1 Determine the values for the voltage v(0-) for t = 0-, v(0+) for t = 0+,

and v(∞) for t = ∞. Determine the time constant ττ .

3.2 Determine an expression for the voltage v(t) as a function of time t, and draw this function v(t) versus time t, for − ∞ < t < ∞.

END

Fig.3

+ v(t) −

+ E −

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Appendix for problem 2 X = 0 Clock Q0 Q1 D0 D1

X = 1 Clock Q0 Q1 D0 D1

Page 36: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

FRÓÐSKAPARSETUR FØROYA Page 1 of 4 pages (UNVERSITAS FÆROENSIS) Examination: Monday 29 January 2001, time: 9.00 – 13.00 Subject: Digital electronics Helping material permitted: All usual, including books Assessment: The solutions will be assessed as a whole

Problem 1 A logic expression F depending on the logic variables V,X,Y, and Z is given by

F = ΠΠV,X,Y,Z (2,4,8,10,12,14,15) + d(0,1,9) 1.1 Fill in a Karnaughmap with 0 and 1 and don’t care (d) input combinations for

the logic expression F. 1.2 Find a minimal product of sum expression for F, using don’t care

combinations most efficiently. 1.3 Find a minimal sum of product expression for F, using don’t care

combinations most efficiently.

(Continues next page)

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Page 2 of 4 pages

Problem 2

Fig.2.1 shows a synchronous counter constructed by 3 D flip-flops, and a combinational logic circuit (“next state logic”). The D flip-flops have the outputs Q2, Q1, and Q0 and their inverse. These are the same variables as the inputs to the next state logic (the connecting wires are not shown in order to simplify the drawing). The counter is controled by an extra input logic variable X to the next state logic. When X=0, the counter outputs Q2, Q1, Q0 result in a counting sequence according to numbers with the binary code. (Q2 is the most significant bit (MSB)). When X=1 the counter outputs Q2, Q1, Q0 result in a counting sequence according to numbers with the Gray code. The binary code and the Gray code are shown in fig.2.2. The state names of the counter are defined according to the table of fig.2.3 2.1 Construct the state table, and the corresponding transition table for the

counting sequences described for the binary and Gray-codes. 2.2 Show that one of the excitation equations can be described as

D0 = X’ ⋅⋅ Q0’ + X ⋅⋅ Q1’ $$ Q2’ + X ⋅⋅ Q1$$ Q2 Find also the maximally reduced excitation equations for D2 og D1. (Use of Karnaughmap is recommended).

2.3 Draw a logic circuit diagram that realizes D0 , taking all the logic variables X, Q2, Q1 and Q0 , and their inverted values as given available on the input.

2.4 Using the given statenames mentioned in fig.2.3, draw a state diagram for the

binary-code/Gray-code counter. (Continues next page)

Decimal number

Binary code Q 2 Q1 Q0

Gray code Q2 Q1 Q0

0 0 0 0 0 0 0 1 0 0 1 0 0 1 2 0 1 0 0 1 1 3 0 1 1 0 1 0 4 1 0 0 1 1 0 5 1 0 1 1 1 1 6 1 1 0 1 0 1 7 1 1 1 1 0 0

Fig.2.2

State name Q 2 Q1 Q 0 A 0 0 0 B 0 0 1 C 0 1 0 D 0 1 1 E 1 0 0 F 1 0 1 G 1 1 0 H 1 1 1

Fig.2.3

CLOCK

D0

D1

D2

Fig.2.1

Q

Q

PR

CLR CLK D

Q2'

Q2

O

Q

Q

PR

CLR

CLK D

Q1'

Q1

O

Q

Q

PR

CLR

CLK D

Q0'

Q0

O

Q0'

Q0

Q1

Q1'

Q2

Q2'

Next state logic

X

State memory

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Page 3 of 4 pages

Problem 3

In fig.3.1 is shown a circuit with an npn transistor with a data sheet as given in fig.3.2, showing the output characteristic of the collector current IC as a function of the collector-emitter voltage VCE , and the base current IB as a parameter. The base-emittervoltage VBE for the transistor in the conducting state (activ or saturated) is taken to be VBE(on)= 0.6 volt . Further it is given that The supply voltage ECC = 12 volt The resistance R1 = 200 kohm The resistance R2 = 1 kohm 3.1 Determine the values of the current amplification factor β,

and the saturation resistance rC,sat. Draw the loadline (arbeiðslinja) into the output characteristic, and determine the value of IB , IC , and VCE . (Use the attached sheet for the drawing given in the appendix).

(Continues next page)

Fig.3.2 0 5 10 (volt)

IC (mA)

VCE

IB= 125 µA 100 µA 75 µA 50 µA 25 µA

20 18 16 14 12 10 8 6 4 2 0

+

_ VBE

+

_

VCE

R1

ECC

R2

+

_

V

Fig.3.1

IB

IC

Page 39: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

Page 4 of 4 pages Problem 4 The operational amplifier in the circuit shown in fig. 4.1 is ideal. The resistances and the capacitance have the following values: R1 = 5 kiloohm R2 = 4 kiloohm R3 = 8 kiloohm C = 2 mikrofarad The ideal voltage generator E varies as a function of time as: E = 0 volt for t < 0 E = 5volt for t õ0 4.1 Determine the values of the output voltage V(t) for the times t = 0 − , t = 0 + ,

and t = ∞. Find the time constant ττ . 4.2 Find an expression for the output voltage V(t), and draw V(t) as a function of

time t in the interval - ∞ < t < + ∞. END

Fig.4.1

+ −

C= 2µµF

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Appendix Sheet for problem 3

Fig.3.2 0 5 10 (volt)

IC (mA)

VCE

IB= 125 µA 100 µA 75 µA 50 µA 25 µA

20 18 16 14 12 10 8 6 4 2 0

Page 41: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

FRÓÐSKAPARSETUR FØROYA Side 1 af 4 sider (UNVERSITAS FÆROENSIS) Eksamen fredag 29.januar 1999, kl. 9.00 – 13.00 Fag: Digitalelektronik Tilladte hjælpemidler: Alle sædvanlige Vægtning: Opgavesættet vægtes som en helhed Opgave 1 Der er opgivet en logisk funktion F = ΣV,X,Y,Z (0,2,6,8,10,11,12) + d(1,4,5) 1.1 Udfyld et Karnaughkort med 0 og 1 og ligegyldighedsværdier (don’t care) for

funktionen F. Opgave 2 V X Y Z

0 0

0 1

1 1

1 0

0 0

1

1

0

1

01

0

0

0

1

1 1

1

0

d

d

1 0

1

0

d

1

Fig.2.1 I fig.2.1 er vist et Karnaughkort for en logisk funktion G. 2.1 Udled et minimalt sum af produkt udtryk for G, hvor ligegyldighedsværdierne

(don’t care) d udnyttes bedst muligt. 2.2 Udled et minimalt produkt af sum udtryk for G, hvor ligegyldighedsværdierne

(don’t care) d udnyttes bedst muligt. (Fortsættes næste side)

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Side 2 af 4 sider Opgave 3 En logisk funktion H af de uafhængige variable A, B, C og D er givet ved H = ABC’ + A’C’D + A’BC + ACD 3.1 Vis (f.eks.med hjælp af et Karnaughkort), at der findes “static-1 hazard” i

funktionen H, og angiv disse. Tilføj led, der fjerner alle “static- 1 hazard”, og tegn et logisk kredsløb af denne modificerede funktion. (Det antages, at alle værdier A, A’, B, B’, C, C’, D og D’ er tilgængelige som indgangssignaler).

Opgave 4 Fig.4.1 Fig.4.1 viser en synkron tæller, der ønskes opbygget af D flip-flop og et kombinatorisk kredsløb (“next state logic”) således, at flip-floppernes udgange Q3, Q2, Q1, Q0 er bittene i en BCD kode, hvor Q3 er mest betydende bit (“most significant bit = MSB). Konstruer tælleren således, at såfremt Q3, Q2, Q1, Q0 , f.eks. på grund af et støjsignal er blevet overdekadisk (d.v.s. 10, 11, 12, 13, 14 eller 15), bliver tilstanden efter næste klokkepuls Q3*, Q2*, Q1*, Q0* = 0,0,0,0 .

(Fortsættes næste side)

Q

Q

PR

CLR

CK

D Q

QCLR

CK

D

Q

Q

PR

CLR

CK

D Q

Q

PR

CLR

CK

D

Q

Q

PR

CLR

CK

D Q

Q

PR

CLR

CK

D

Q0'

Q0

Q1

Q1'

Q2

Q2'

Q3

Q3'

Q3'

Q3

Q2'

Q2

Q1'

Q1

Q

Q

PR

CLR

CK

D Q

Q

PR

CLR

CK

D

Q0'

Q0

CK

O–—

O–—

O–—

O–—

PR

D0

D1

D2

D3

.

.

.

"Next state logic"

Page 43: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

Side 3 af 4 sider 4.1 Opskriv sandhedstabellen for D3, D2, D1, D0. 4.2 Vis, at D3 = Q3’Q2Q1Q0 + Q3Q2’Q1’Q0’

Find desuden maksimalt reducerede udtryk for produkt af sumudtryk for D2, D1 og D0 (evt. med hjælp af Karnaughkort).

4.3 Tegn et kredsløbsdiagram, der realiserer D3 ved anvendelse af NAND-porte (NAND-gates)

4.4 Navngiv hver af de 16 tilstande (incl. de overdekadiske tilstande), som

tælleren kan være i med et bogstav A,B,C,D, ........P. Tegn under anvendelse af disse navne et tilstandsdiagram for tælleren.

Opgave 5

Fig. 5.1 I fig.5.1 er vist et kredsløb med en npn transistor, om hvilken det er gældende, at strømforstærkningsfaktoren β = 300, mætningsmodstanden rC,sat = 25 ohm, basis-emitterspændingen i ledende (aktiv eller mættet) tilstand VBE(on)= 0.6 volt . Desuden er opgivet, at ECC = 10 volt R1 = 500 kohm R2 = 2 kohm R3 = 3 kohm 5.1 Bestem spændingen V, og

angiv, om transistoren er afskåret, aktiv eller mættet (der skal gives en begrundelse for resultatet).

(Fortsættes næste side)

+

_V BE

+

_

VCE

R

RR

3

21

E CC

.

.

.

.

+

_

V

Page 44: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth

Side 4 af 4 sider Opgave 6 Fig.6.1 I fig.6.1 er vist et kredsløb med en ideel operationsforstærker. Komponentværdierne i kredsløbet har følgende værdier: R1 = 1 kiloohm R2 = 4 kiloohm R3 = 50 kiloohm C = 1.25 mikrofarad Den ideelle spændingsgenerators spænding E varierer med tiden t som følger: E = 0 volt for t < 0 E = 0.1 volt for t ∞0 6.1 Bestem talværdierne for udgangsspændingen V=V(t) for tidspunkterne t = 0-, t = 0+ og t = ∞. Bestem tidskonstanten τ. Skitser herudfra forløbet af V(t) for -∞ < t < +∞. SLUT

+-+

_E

+

_V

+15 V

-15 V

R3

R2

C

R1.

.

..

.

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Page 57: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth
Page 58: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth
Page 59: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth
Page 60: Introductory Digital and Analogue Electronics · Introductory Digital and Analogue Electronics ... and goes through a 74244 octal tri-state buffer to a D/A ... The table is the truth
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