Download - Giao Trinh Kien Truc May Tinh 8891
GIO TRNH KIN TRC MY TNH
GIO TRNH KIN TRC MY TNH
GIO TRNH KIN TRC MY TNH
CHNG I. GII THIU CHUNG V KIN TRC MY TNH.
I. Khi nim v kin trc my tnh
Kin trc my tnh (Computer architecture) l mt khi nim tru tng ca mt h thng tnh ton di quan im ca ngi lp trnh hoc ngi vit chng trnh dch.
Ni cch khc, kin trc my tnh c xem xt theo kha cnh m ngi lp trnh c th can thip vo mi mc c quyn, bao gm cc thanh ghi, nh cc ngt ... c th c thm nhp thng qua cc lnh.
II. Lch s pht trin ca my tnh.
Chic my tnh in t u tin l ENIAC c ra i nm 1946, c ch to t nhng n in t, rle in t v cc chuyn mch c kh.
Lch s pht trin ca my tnh in t c th chia lm bn th h nh sau:
- Th h 1: (1945-1955). My tnh c xy dng trn c s n in t m mi n tng trng cho 1 bit nh phn. Do my c khi lng rt ln, tc chm v tiu th in nng ln. Nh my ENIAC c khi lng 30 tn, tiu th cng sut 140KW.
- Th h th 2: (1955-1965). My tnh c xy dng trn c s l cc n bn dn (transistor), my tnh u tin th h ny c tnl TX-0 (transistorized experimental computer 0).
- Th h th ba: (1965-1980). My tnh c xy dng trn cc vi mch c nh (SSI) v c va (MSI), in hnh l th h my System/360 ca IBM. Th h my tnh ny c nhng bc t ph mi nh sau:
- Tnh tng thch cao: Cc my tnh trong cng mt h c kh nng chy cc chng trnh, phn mm ca nhau.
- c tnh a chng trnh: Ti mt thi im c th c vi chng trnh nm trong b nh v mt trong s c cho chy trong khi cc chng trnh khc ch hon thnh cc thao tc vo/ra.
- Khng gian a ch rt ln.
- Th h th t: (1980- ). My tnh c xy dng trn cc vi mch c ln (LSI) v cc ln (VLSI).
y l th h my tnh s ngy nay, nh cng ngh bn dn pht trin vt bc, m ngi ta c th ch to cc mch t hp mc cc ln. Nh my tnh ngy cng nh hn, nh hn, mnh hn v gi thnh r hn. My tnh c nhn bt u xut hin v pht trin trong thi k ny.
Da vo kch thc vt l, hiu sut v lnh vc s dng, hin nay ngi ta thng chia my tnh s th h th t thnh 5 loi chnh, cc loi c th trm ln nhau mt phn:
- Microcomputer: Cn gi l PC (personal computer), l nhng my tnh nh, c 1 chip vi x l v mt s thit b ngoi vi. Thng dng cho mt ngi, c th dng c lp hoc dng trong mng my tnh.
- Minicomputer: L nhng my tnh c trung bnh, kch thc thng ln hn PC. N c th thc hin c cc ng dngm my tnh c ln thc hin. N c kh nng h tr hng chc n hng trm ngi lm vic. Minicomputer c s dng rng ri trong cc ng dng thi gian thc, v d trong iu khin hng khng, trong t ng ho sn xut.
- Supermini: L nhng my Minicomputer c tc x l nhanh nht trong h Mini nhng thi im nht nh. Supermini thng c dng trong cc h thng phn chia thi gian, v d cc my qun gia ca mng.
- Mainframe: L nhng my tnh c ln, c kh nng h tr cho hng trm n hng ngn ngi s dng. Thng c s dng trong ch cc cng vic sp xp theo l ln (Large-Batch-Job) hoc x l cc giao dch (Transaction Processing), v d trong ngn hng.
- Supercomputer: y l nhng siu my tnh, c thit k c bit t tc thc hin cc php tnh du phy ng cao nht c th c. Chng thng c kin trc song song, ch hot ng hiu qu cao trong mt s lnh vc.
Da vo kin trc ca my tnh ngi ta cng phn my tnh ra cc loi khc nhau nh sau:
- Kin trc SISD (single instruction - single data, n dng lnh - n dng d liu), s nh hnh 1-1.
Hnh 1-1: Kin trc my tnh SISD.
- Kin trc CIMD (Single Instruction Multiple Data, n dng lnh- a d liu), s nh hnh 1-2.
Hnh 1-2: Kin trc SIMD.
- Kin trc MIMD (Multiple Instruction Multiple Data, a dng lnh- a d liu), s nh hnh 1-3.
Hnh 1-3: Kin trc MIMD.
CHNG II. BIU DIN THNG TIN TRONG MY TNH
I. H nh phn (Binary)
I.1. Khi nim:
H nh phn hay h m c s 2 ch c hai con s 0 v 1. l h m da theo v tr. Gi tr ca mt s bt k no tu thuc vo v tr ca n. Cc v tr c trng s bng bc lu tha ca c s 2. Chm c s c gi l chm nh phn trong h m c s 2. Mi mt con s nh phn c gi l mt bit (BInary digiT). Bit ngoi cng bn tri l bit c trng s ln nht (MSB, Most Significant Bit) v bit ngoi cng bn phi l bit c trng s nh nht (LSB, Least Significant Bit) nh di y:
23 22 21 20 2-1 2-2
MSB1 0 1 0 . 1 1 LSB
Chm nh phn
S nh phn (1010.11)2 c th biu din thnh:
(1010.11)2 = 1*23 + 0*22 + 1*21 + 0*20 + 1*2-1 + 1*2-2 = (10.75)10.
Ch : dng du ngoc n v ch s di k hiu c s ca h m.
I.2. Bin i t nh phn sang thp phn
V d : Bin i s nh phn (11001)2 thnh s thp phn:
Trng s v tr: 24 23 22 21 20
Gi tr v tr: 16 8 4 2 1
S nh phn: 1 1 0 0 1
S thp phn: 1*24 + 1*23 + 0*22 + 0*21 + 1*20 = (25)10
I.3. Bin i thp phn thnh nh phn
thc hin vic i t thp phn sang nh phn, ta p dng phng php chia lp nh sau: ly s thp phn chia cho c s thu c mt thng s v s d. S d c ghi li lm mt thnh t ca s nh phn. Sau , s thng li c chia cho c s mt ln na c thng s th 2 v s d th 2. S d th hai l con s nh phn th hai. Qu trnh tip din cho n khi s thng bng 0.
V d 1: Bin i s thp phn (29)10 thnh nh phn:
29/2 = 14 + 1(LSB)
14/2 = 7 + 0
7/2 = 3 + 1
3/2 = 1 + 1
1/2 = 0 + 1(MSB)
Vy (29)10 = (1101)2 .
i vi phn l ca cc s thp phn, s l c nhn vi c s v s nh c ghi li lm mt s nh phn. Trong qu trnh bin i, s nh u chnh l bit MSB v s nh cui l bit LSB.
V d 2: Bin i s thp phn (0.625)10 thnh nh phn:
0.625*2 = 1.250. S nh l 1, l bit MSB.
0.250*2 = 0.500. S nh l 0
0.500*2 = 1.000. S nh l 1, l bit LSB.
Vy : (0.625)10 = (0.101)2.
II. H thp lc phn (Hexadecima).II.1. Khi nim:
Cc h my tnh hin i thng dng mt h m khc l h thp lc phn.
H thp lc phn l h m da vo v tr vi c s l 16. H ny dng cc con s t 0 n 9 v cc k t t A n F nh trong bng sau:
Bng 2.1 H thp lc phn:
Thp lc phnThp phnNh phn
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
150000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
II.2.Bin i thp lc phn thnh thp phn.
Cc s thp lc phn c th c bin i thnh thp phn bng cch tnh tng ca cc con s nhn vi gi tr v tr ca n.
V d : Bin i cc s a.(5B)16. b. (2AF)16 thnh thp phn.
a. S thp lc phn: 5 B
Trng s v tr: 161 160
Gi tr v tr : 16 1
S thp phn: 5*16 + B*1 = (91)10.
b. S thp lc phn: 2 A F
Trng s v tr: 162 161 160
Gi tr v tr : 256 16 1
S thp phn: 2*256 + A*16 + F*1 = (687)10.
II.3.Bin i thp phn thnh thp lc phn.
bin i cc s thp phn thnh thp lc phn, ta s dng phng php chia lp, vi c s 16.
V d : Bin i (1776)10 thnh thp lc phn.
1776/16 = 111 + 0 (LSB).
111/16 = 6 + 15 hoc F.
6/16 = 0 + 6 (MSB).
S thp lc phn: (6F0)16.
II.4. Bin i thp lc phn thnh nh phn.
Cc s thp lc phn rt d i thnh nh phn. Thc ra cc s thp lc phn cng ch l mt cch biu din cc s nh phn thun li hn m thi (bng 2-1). i cc s thp lc phn thnh nh phn, ch cn thay th mt cch n gin tng con s thp lc phn bng bn bit nh phn tng ng ca n.
V d: i s thp lc (DF6)16 thnh nh phn:
D F 6
1101 1111 0110
(DF6)16 = (110111110110)2.
II.5. Bin i nh phn thnh thp lc phn.
bin i mt s nh phn thnh s thp lc phn tng ng th ch cn gp li thnh tng nhm gm 4 bit nh phn, bt u t du chm nh phn.
V d: Bin i s nh phn (1111101000010000)2 thnh thp lc phn.
1111 1010 0001 0000
F A 1 0 S thp lc phn: (FA10)16.
III. H BCD (Binary Code decimal).
Gia h thp phn v h nh phn cn tn ti mt h lai: h BCD cho cc s h thp phn m ho bng h nh phn, rt thch hp cho cc thit b o c thm phn hin th s u ra dng cc loi n hin s khc nhau. y dng bn s h nh phn (bn bit) m ho mt s h thp phn c gi tr nm trong khong t 0..9. Nh vy y ta khng dng ht cc t hp c th c ca 4 bit; v tm quan trng ca cc s BCD nn cc b vi x l thng c cc lnh thao tc vi chng.
V d: (35)10 = (00110101)2.
IV. Bng m ASCII.(American Standard Code for Information Interchange).
Ngi ta xy dng b m biu din cho cc k t cng nh cc con s V cc k hiu c bit khc. Cc m gi l b m k t v s. Bng m ASCII l m 7 bit c dng ph bin trong cc h my tnh hin nay. Vi m 7 bit nn c 27 = 128 t hp m. Mi k t (ch hoa v ch thng) cng nh cc con s thp phn t 0..9 v cc k hiu c bit khc u c biu din bng mt m s nh bng 2-2.
Vic bin i thnh ASCII v cc m k t s khc, tt nht l s dng m tng ng trong bng.
V d: i cc k t BILL thnh m ASCII:
K t B I L L
ASCII 1000010 1001001 1001100 1001100
HEXA 42 49 4C 4C
Bng 2-2: M ASCII.
Column bits(B7B6B5)
Bits(row)
000 001 010 011 100 101 110 111
R
O
WB4B3B2B101234567
00000NULDLESP0@P\p
10001SOHDC1!1AQaq
20010STXDC22BRbr
30011ETXDC3#3CScs
40100EOTDC4$4DTdt
50101ENQNAK%5EUeu
60110ACKSYN&6FVfv
70111BELETB7GWgw
81000BSCAN(8HXhx
91001HTEM)9IYiy
A1010LFSUB*:JZjz
B1011VTESC+;K[k{
C1100FFFS-N^n~
F1111SIUS/?O_oDEL
Control characters:
NUL = Null; DLE = Data link escape; SOH = Start Of Heading;
DC1 = Device control 1; DC2 = Device control 2; DC3 = Device control 3.
DC4 = Device control 4; STX = Start of text; ETX = End of text;
EOT = End of transmission; ENQ = Enquiry; NAK = Negative acknowlege.
ACK = Acknowlege; SYN = Synidle; BEL = Bell.
ETB = End od transmission block; BS = Backspace; CAN = Cancel.
HT = Horizontal tab; EM = End of medium; LF = Line feed; SUB = Substitute.
VT = Vertical tab; ESC = Escape; FF = From feed; FS = File separator.
SO = Shift out; RS = Record separator; SI = Shift in; US = Unit separator.V. Biu din gi tr s trong my tnh.
V.I. Biu din s nguyn.a. Biu din s nguyn khng du:
Tt c cc s cng nh cc m ... trong my vi tnh u c biu din bng cc ch s nh phn. biu din cc s nguyn khng du, ngi ta dng n bit. Tng ng vi di ca s bit c s dng, ta c cc khong gi tr xc nh nh sau:
S bit
Khong gi tr
n bit: 0.. 2n - 1
8 bit 0.. 255 Byte
16 bit
0.. 65535 Word
b. Biu din s nguyn c du:
Ngi ta s dng bit cao nht biu din du; bit du c gi tr 0 tng ng vi s nguyn dng, bit du c gi tr 1 biu din s m. Nh vy khong gi tr s c biu din s c tnh nh sau:
S bit
Khong gi tr:
n bit
2n-1-1
8 bit
-128.. 127 Short integer
16 bit
-32768.. 32767 Integer
32 bit -231.. 231-1 (-2147483648.. 2147483647) Long integer
V.2. Biu din s thc(s c du chm (phy) ng).
C hai cch biu din s thc trong mt h nh phn: s c du chm c nh (fed point number) v s c du chm ng (floating point number). Cch th nht c dng trong nhng b VXL(micro processor) hay nhng b vi iu khin (micro controller) c. Cch th 2 hay c dng hin nay c chnh xc cao. i vi cch biu din s thc du chm ng c kh nng hiu chnh theo gi tr ca s thc. Cch biu din chung cho mi h m nh sau:
R = m.Be.
Trong m l phn nh tr, trong h thp phn gi tr tuyt i ca n phi lun nh hn 1. S e l phn m v B l c s ca h m.
C hai chun nh dng du chm ng quan trng l: chun MSBIN ca Microsoft v chun IEEE. C hai chun ny u dng h m nh phn.
Thng dng l theo tiu chun biu din s thc ca IEEE 754-1985(Institute of Electric & Electronic Engineers), l chun c mi hng chp nhn v c dng trong b x l ton hc ca Intel. Bit du nm ti v tr cao nht; kch thc phn m v khun dng phn nh tr thay i theo tng loi s thc.
Gi tr s thc IEEE c tnh nh sau:
R = (-1)S*(1+M1*2-1 + ... +Mn*2-n)*2E 7...E 0 -127.
Ch : gi tr u tin M0 lun mc nh l 1.
- Dng 32 bit biu din s thc, c s thc ngn: -3,4.1038 < R < 3,4.1038
31 30 23 22
0
SE7 - E0|nh tr (M1 - M23)
- Dng 64 bit biu din s thc, c s thc di: -1,7.10308 < R < 1,7.10308
63 62 52 51
0
S E10 - E0nh tr (M1 - M52)
V d tnh s thc:
0100 0010 1000 1100 1110 1001 1111 1100
Phn nh tr: 2-4+2-5+2-8+2-9+2-10+2-12+2-15+
+2-16+2-17+2-18+2-19+2-20+2-21 = 0,1008906.
Gi tr ngm nh l: 1,1008906.
Phn m: 28+22+20 =133
Gi tr thc (bit cao nht l bit du): 133-128=6.
Du: 0 = s dng
Gi tr s thc l: R = 1,1008906.26 = 70,457.Phng php i s thc sang s du phy ng 32 bit:
- i s thp phn thnh s nh phn.
- Biu din s nh phn di dng (1, xxxBy (B: c s 2).
- Bit cao nht 31: ly gi tr 0 vi s dng, 1 vi s m.
- Phn m y i sang m excess -127 ca y, c xc nh bng cch: y + (7F)16.
- Phn xxx l phn nh tr, c a vo t bit 22..0.
V d: Biu din s thc (9,75)10 di dng du phy ng.
Ta i sang dng nh phn: (9,75)10 = (1001.11)2 = 1,00111B3.
Bit du: bit 31 = 0.
M excess - 127 ca 3 l: 7F + 3 = (82)16 = 82H = (10000010)2. c a vo cc bit tip theo: t bit 30 n bit 23.
Bit 22 lun mc nh l 0.
Cui cng s thc (9,75)10 c biu din di dng du phy ng 32 bit nh sau:
0100 0001 0001 1100 0000 0000 0000 0000
bit |31|30 23|22 0|
CHNG III. CC KHI C BN CA MY TNH
I. Gii thiu s lc cu trc ca my vi tnh.
So vi t khi ra i, cu trc c s ca cc my vi tnh ngy nay khng thay i my. Mi my tnh s u c th coi nh c hnh thnh t su phn chnh (nh hnh 3-1):
Hnh 3-1: Gii thiu s khi tng qut ca my tnh s
Trong s ny, cc khi chc nng chnh ca my tnh s gm:
- Khi x l trung tm (central processing unit, CPU),
- B nh trong (memory), nh RAM, ROM
- B nh ngoi, nh cc loi a, bng t
- Khi phi ghp vi cc thit b ngoi vi (vo/ra)
- Cc b phn u vo, nh bn phm, chut, my qut ... .
- Cc b phn u ra, nh mn hnh, my in ... .
Bn khi chc nng u lin h vi nhau thng qua tp cc ng dy truyn tn hiu, gi chung l bus h thng. Bus h thng bao gm 3 bus thnh phn; ng vi cc tn hiu xc lp a ch t CPU n cc n v thnh phn ta c bus a ch; vi cc d liu c lin h gia cc khi qua bus d liu (data bus); cc tn hiu iu khin bao gm cc lnh, cc p ng, cc trng thi ca cc khi c xc lp qua bus iu khin.
S khc bit quan trng nht ca cc h my tnh l kch thc v tc , cc my tnh nh hn v nhanh, mnh hn theo tng nm. S pht trin khng ngng ca cc th h my tnh nh vo hai yu t quan trng, l s pht trin ca cng ngh ch to IC v cng ngh ch to b nh.
II. B nh trong.II.1. C s v b nh.
Cc b nh c th chia lm hai loi tng qut, ROM v RAM. ROM l Read-only Memory(b nh ch c) v RAM l Random-access Memory (b nh truy xut ngu nhin). Ni chung ROM cha cc d liu mt cch c nh v khng th thay i. Cn RAM c th c ra v c th ghi vo.
Khi nim truy xut ngu nhin c ngha l bt k mt v tr nh no cng c th c m ra hoc c gi ra bt k lc no, cc thng tin khng cn phi c ra hay ghi vo mt cch tun t. V thc cht, c RAM v ROM u l truy xut ngu nhin. Ch c iu khc nhau c bn l ROM ch cho php c m khng th ghi vo n, cn RAM l b nh c th c v ghi, v th RAM c gi l b nh c/ghi.
Cu trc b nh
Hnh 2-2 trnh by s khi ca mt mch nh. Mch nh c ni vi cc b phn khc trong my tnh thng qua cc ng y a ch v cc ng dy d liu ca n. Kim sot mch nh bng ng dy cho php (enable), ring i vi RAM cn c thm ng dy kim sot c/ghi (Read/write).
Cc mch nh ni chung c t chc di dng ma trn, gm nhng hng v nhng ct xc nh v tr hay a ch nh. Mi trong ma trn gi l mt phn t (cell) hay v tr nh (memory location). V tr hay phn t nh c d tm bng cch chn a ch nh mch gii m a ch. Mch ny gm hai phn: mch chn a ch hng RAS (row-address selector) v mch chn a ch ct CAS (Column-address selector). Cc ng dy a ch s chn a ch hng v ct. ng dy enable dng m cc mch in li ra b nh theo ba trng thi. Cn ng dy Read/write quyt nh dng thao tc s thc hin.
B nh hoc l c t chc bit hoc l loi c t chc li (word organized). B nh t chc bit c th lu gi mt bit n trong mi v tr a ch. B nh t chc li s c la chn c mt nhm phn t nh cng mt lc vi mi v tr a ch. Mi nhm phn t nh thng l mt byte (8 bit), hoc mt li (16 bit).
S ng dy a ch ca mch nh s quyt nh s v tr nh cc i tnh theo cng thc sau:
S v tr nh cc i = 2N.
trong , N l s lng cc ng a ch.
a. Mch nh c bn (basic memory device)
b. S khi (Block diagram)
Hnh 2-2 Mch nh.II.2. ROM-BIOS.
Bt c h my tnh no cng c mt vi mch ROM. vi mch ny cha chng trnh ca h iu hnh vo ra c s BIOS (basic input/output system). Nhng chng trnh ny cn thit khi ng my v ci t ch lm vic c s cho cc thit b ngoi vi.
Ni chung, c th chia ROM thnh bn loi. ROM mt n (maskable ROM) l loi ROM do nh sn xut np sn d liu, khi d liu khng th thay i c na. ROM c th np chng trnh (PROM - programable ROM) l loi mch m ngi dng c th np d liu vo thng qua thit b t PROM. Khi np th cc d liu trong PROM cng khng th thay i. PROM c th xo, cn gi l EPROM (erasable PROM) l loi ROM m ngi dng c th np d liu vo v cc d liu c th xo hoc thay i bng mt thit b c bit. EPROM c th xo bng in (electric EPROM) l loi ROM c th np v xo d liu bng in c m khng phi s dng tia cc tms nh vi EPROM.
Trong cc my tnh hin i, ngi ta thng s dng Flash BIOS dng EEPROM. Nh vy ni dung BIOS ca my tnh c th c thay i tng thch vi nhng m rng v nng cp h thng, m iu ny l khng th thc hin i vi nhng my tnh th h c s dng BIOS dng PROM hoc EPROM.
BIOS gm nhiu chng trnh v hm. Phn u ca chng trnh BIOS kim tra h thng my tnh, qu trnh ny gi l POST. Nu h thng s dng cc Card (th cm) Plug and Play th giai on ny chnh l lc my tnh truy nhp tham s ca th. BIOS no cng c chng trnh Setup BIOS ngi dng t chnh tham s cc thit b ngoi vi.
II.3. RAM.
C th chia RAM thnh hai hoi, RAM tnh (SRAM), c kh nng lu gi s liu mi mi nu nh khng mt ngun nui. V RAM ng (DRAM), l loi RAM phi c lm ti (refresh) tc l phi np li d liu ang c lu tr theo tng chu k. Lm ti bng cch thc hin thao tc c hoc ghi nhc li. Cng c th lm ti bng nhng thao tc c bit khc. Loi DRAM c mt phn t nh cao nn gi thnh kh r so vi SRAM. Cc mch nh DRAM c dng ph bin trong cc th h my tnh hin nay.
tit kim s ng a ch v gim s chn trn IC, hu ht cc loi DRAM u dng phng php a ch multiplex. Trong qu trnh c hay ghi cc ng a ch u tin cha cc thng tin v hng ri tip sau mang thng tin v ct. kim sot thao tc ny, ngi ta dng ng dy v nh trn hnh 2-3. Khi thp th thng tin trn cc ng a ch s c m thng qua mch cht a ch hng (row-address latch). Khi thp th thng tin trn cc ng a ch s c m thng qua mch cht a ch ct (column-address latch).
Vic lm ti bng d liu c, d liu ghi hoc bng cc thao tc ring. Mch iu khin lm ti phi chn tun t tng hng cc phn t nh, c mi hng mt ln, cho n khi tt c cc hng u c lm ti. l phng php lm ti tng t. Trong qu trnh khng c c hay ghi d liu vo b nh cho n khi kt thc qu trnh. Mt cch khc l lm ti tng hng trong cc chu k ri rc v gi l lm ti theo chu k n.
Row Column
Address lines A0 to A6 A7 to A13
Row address
valid
Column address
valid
Chip selected
Address latching timing
Hnh 2-3. S khi DRAM 16.384 bits(16Kb).
III. B x l trung tm CPU.
B x l trung tm CPU l ct li ca mt my vi tnh. CPU thc hin mi tnh ton v x l ca h thng -- ngoi tr x l tng cng tnh ton c bit trong nhng h thng c mt chip n v ng x l ton, m chip ny cng c tch hp ngay trong cc CPU hin nay. Tt c nhng my tnh IBM v tng thch IBM s dng nhng b x l h Intel hoc tng thch vi b x l h Intel, d chnh nhng b x l c th c nhiu cng ty khc nhau thit k v sn xut, gm AMD, IBM, Cyric... .
Mt trong nhng b x l in hnh thuc h 80x86 ca Intel l b x l 8088. y l b vi x l kh n gin v v vy vic tm hiu n l tng i d i vi nhng ngi bt u thm nhp vo lnh vc vi x l, mt khc vic nm vng cc vn k thut ca b vi x l 8088 s l c s nm bt c cc k thut ca cc b x l khc trong h 80x86 ca Intel, ca cc h khc v ca cc b x l hin i ngy nay.
III.1. Gii thiu cu trc bn trong ca b vi x l 8088.
Trn hnh 3-1 l s khi cu trc bn trong ca b vi x l 8088.
III.3. n v giao din bus (BIU).Theo s khi trn hnh 3-1 ta thy bn trong CPU 8088 c hai khi chnh: khi phi ghp bus (bus interface unit, BIU) v khi thc hin lnh (execution unit, EU). Vic chia CPU thnh hai phn ng thi c lin h vi nhau qua m lnh lm tng ng k tc x l ca CPU. Cc bus bn trong CPU c nhim v chuyn ti tn hiu ca cc khi khc. Trong s cc bus c bus d liu 16 bit ca ALU, bus cc tn hiu iu khin EU v bus trong ca h thng BIU. Trc khi i ra bus ngoi hoc i vo bus trong ca b vi x l, cc tn hiu truyn trn bus thng c cho i qua cc b m nng cao tnh tng thch cho ni ghp hoc nng cao kh nng phi ghp.
BIU bao gm cc thanh ghi on (segment registers: CS, DS, SS, ES), con tr lnh IP (instruction pointer) v b iu khin logic bus (bus control logic, BCL). n v giao din BIU cn c b nh m cho m lnh. B nh ny c chiu di 4 byte (trong 8088) v 6 byte (trong 8086). B nh m m lnh c ni vi khi iu khn CB (control block) ca n v thc hin lnh EU. B nh ny lu tr tm thi m lnh trong mt dy gi l hng i lnh. Hng i lnh cho php b vi x l c kh nng x l xen k lin tc dng m lnh (pipelining). Hot ng ca b CPU c chia lm ba giai on: c m lnh (operation code fetching), gii m lnh (decording) v thc hin lnh (execution).
BIU a ra a ch, c m lnh t b nh, c/ghi d liu t cc cng vo hoc b nh. Ni cch khc BIU chu trch nhim a a ch ra bus v trao i d liu vi bus.
III.3. n v thc hin lnh (EU).Trong EU c khi iu khin (control unit, CU). Chnh ti bn trong khi iu khin ny c mch gii m lnh. M lnh c vo t b nh c a n u vo ca b gii m, cc thng tin thu c t u ra ca n s c a n mch to xung iu khin, kt qu thu c l cc dy xung khc nhau tu theo m lnh, iu khin hot ng ca cc b phn bn trong v bn ngoi CPU.
Trong EU c khi s hc v lgic (arithmatic and logic unit, ALU) chuyn thc hin cc php tnh s hc v logic m ton t ca n nm trong cc thanh ghi a nng. Kt qu thng c t v thanh ghi AX.
Ngoi ra trong EU cn c cc thanh ghi a nng (registers: AX, BX, CX, DX, SP, BP, SI, DI), thanh ghi c FR (flag register) m cng dng ca chng s oc cp n trong phn sau.
Tm li, khi CPU hot ng EU s cung cp thng tin v a ch cho BIU khi ny c lnh v d liu, cn bn thn n th gii m v thc hin lnh.
III.4. Cc thanh ghi.Cc thanh ghi a nng (general registers)C nhim v ghi tham s cho m lnh, y cng l ni lnh tr kt qu v sau khi c thc hin. Nhng thanh ghi a nng ca vi x l 16 bit l:
- AX (accumulator) rng 16 bit, c chia lm hai phn: 1 byte cao AH v 1 byte thp AL. y l thanh ghi quan trng nht v chuyn c dng cha kt qu cc thao tc lnh. C ba cch vit AX, AH, AL u c th s dng nh nng thanh ghi ring bit.
- BX (base) thanh ghi c s, rng 16 bit, cng c chia ra lm BH v BL. y l thanh ghi thng dng cha a ch c s ca mt bng dng trong lnh XLAT, C ba cch vit BX, BH, BL u c th s dng nh nhng thanh ghi ring bit.
- CX (count) b m, rng 16 bit. c chia ra lm CH v CL. Thanh ghi CX c ng ch s ln lp trong trng hp cc lnh LOOP. Thanh ghi thp CL c dng cha (nh) s ln quay hoc dch ca cc lnh quay (rotate) v dch (shift).
- DX (data) thanh ghi d liu, rng 16 bit. Thanh ghi ny cng thanh ghi AX tham gia vo cc thao tc ca php nhn hoc chia cc s 16 bit. DX cn dng cha a ch 16 bit ca cc cng cng (di hn 8 bit) trong cc lnh truy nhp cc cng ngoi vi (I/O port).
Cc thanh ghi on (segment registers) dng ghi a ch mt on b nh. Vi mch 8088/8086 c 20 ng dy trn bus a ch. Do cc thanh ghi con tr c thanh ghi ch s ch rng 16 bit nn khng th nh a ch cho ton b nh vt l ca my tnh l (220 = 1.048.576 = 1Mbyte). V vy trong ch thc (real mode) b nh c chia lm nhiu on mt thanh ghi con tr 16 bit c th qun l c. Cc thanh ghi on 16 bit s ch ra a ch u ca 4 on trong b nh, dung lng ln nht ca mi on nh s di 216 = 64 Kbyte v ti mt thi im nht nh b vi x l ch lm vic c vi 4 on nh 64Kbyte ny. Vic thay i gi tr ca cc thanh ghi on lm cho cc on c th dch chuyn linh hot trong khng gian 1 Mbyte, v vy cc on c th nm cch nhau khi thng tin cn lu trong chng i hi dung lng 64 Kbyte hoc cng c th nm trm nhau do c nhng on khng dng ht di 64 Kbyte v v th cc on khc c th bt u ni tip ngay sau . a ch ca nh nm u on c ghi trong mt thanh ghi on 16 bit, a ch ny gi l a ch c s. Mi su bit ny tng ng vi cc ng dy a ch t A4 n A20. Nh vy gi tr vt l ca a ch on l gi tr trong thanh ghi on dch sang tri 4 v tr. iu ny tng ng vi php nhn vi 24 = 16. a ch ca cc nh khc nm trong on tnh c bng cch cng thm vo a ch c s mt gi tr gi l a ch lch hay lch (offset), gi nh th v n ng vi khong lch ca to mt nh c th no so vi u on. lch ny c xc nh bi cc thanh ghi 16 bit khc ng vai tr thanh ghi lch (offset register). Nguyn tc ny dn n cng thc tnh a ch vt l (physical address) t a ch on (segment) trong thanh ghi on v a ch lch (offset) trong thanh ghi con tr nh sau:
Vic dng hai thanh ghi nh thng tin v a ch thc cht to ra mt loi a ch gi l a ch logic v c k hiu nh sau:
Thanh ghi on : Thanh ghi lch hay segment:offset.
a ch kiu segment : offset l logic v n tn ti di dng gi tr ca cc thanh ghi c th bn trong CPU v khi cn thit truy nhp nh no th n phi i ra a ch vt l ri a ln bus a ch. Vic chuyn i ny do mt b to a ch thc hin (phn t ( trn hnh 3-1).
Vi x l 16 bit c 4 thanh ghi on nh sau:
- CS (code segment) l thanh ghi on m 16 bit. thanh ghi ny phi hp vi con tr lnh IP ghi a ch m lnh trong b nh. a ch y l CS:IP.
- DS (data segment) l thanh ghi on 16 bit cho mt on d liu. Thanh ghi ny phi hp vi hai thanh ghi ch s SI v DI nh a ch cho d liu. a ch y cho d liu cn c vo l DS:SI, cho d liu cn ghi ra l DS:DI.
- SS (stack segment) l thanh ghi on 16 bit cho mt ngn xp. a ch nh ca ngn xp c biu din cng vi con tr ngn xp SP l SS:SP.
- ES (extra segment) l thanh ghi d liu ph c chiu di 16 bit. Thng uc dng nh a ch mt chui. ES:DI l a ch chui cn vit n (chui ch) v DS:SI l a ch chi c vo (chui ngun).
Cc thanh ghi con tr v ch s c th c dng nh mt thanh ghi a nng 16 bit. Vi mch 8088 c tt c ba thanh ghi con tr l (IP, BP, SP) v hai thanh ghi ch s (SI, DI). Nhim v ca tng thanh ghi nh sau:
- IP (instruction pointer) l con tr ch ti lnh my tip theo. Lnh ny nm trong b nh m a ch on c ghi trong CS. Nh vy a ch ca m k=lnh ny l CS:IP.
- BP (base pointer) l con tr c s tr v d liu b nh m a ch on c ghi trong SS. a ch y s l SS:BP.
- SP (stack pointer) l con tr ngn xp lun tr vo nh ngn xp m a ch on c ghi trong SS. a ch y ca d liu l DS:SP.
- SI (source index) l ch s ngun, tr vo d liu m a ch on c ghi trong DS. a ch y ca d liu l DS:SI.
- DI (destination index) l ch s ch, cng tr vo on d liu m a ch on ghi trong DS. a ch y ca on d liu l DS:SI.
Thanh ghi c FR (flag register) y l thanh ghi kh c bit trong CPU, dng ghi trng thi kt qu cc php x l trong n v s hc v logic ALU hoc mt trng thi hot nh ca EU. Da vo cc c ny ngi lp trnh c th c cc lnh thch hp tip theo cho b vi x l (cc lenh nhy c iu kin). Thanh ghi ny l mt thanh ghi 16 bit trong 8088/8086. Nhng ch c 9 bit trong thanh ghi c nh ngha v s dng, l:
xxxxODITSZxAxPxC
x: bit khng c nh ngha.
Hnh 3-2. S thanh ghi c ca b vi x l 8086/8088.- Bit 0: CF (carry flag) c nh, CF=1 khi c nh hoc mn t MSB.
- Bit 2: PF (parity flag) c parity, PF phn nh tnh chn (parity) ca tng s bit 1 c trong kt qu. C PF =1 khi tng s bit 1 trong kt qu l chn (even parity, parity chn).
- Bit 4: AF (auxliary carry flag) c nh ph dng cho cc php tnh vi m BCD. AF = 1 khi c nh hoc mn t mt s BCD thp (4 bit thp) sang mt s BCD cao (4 bit cao).
- Bit 6: ZF (zero flag) c rng, ZF = 1 khi kt qu bng 0.
- Bit 7: SF (sing flag) c du, SF = 1 khi kt qu m.
- Bit 8: TF (trap flag) c by, TF = 1 khi vi x l trong ch chy tng lnh (ch ny dng khi cn tm li trong mt chng trnh).
- Bit 9: IF (interrupt enable flag) c cho php ngt, IF = 1 cho php cc yu cu ngt che c (maskable interrupt) c tc ng.
- Bit A: DF (direction flag) c hng. DF = 1 khi CPU lm vic vi chui k t theo th t t phi sang tri (li).
- Bit B: OF (overflow) c trn, OF =1 khi kt qu vt ra ngoi gii hn, xy ra i vi php tnh c du.
CHNG IV . LNH V CH A CH
I. Cu trc m lnh
Quy trnh thc hin mt lnh trong b vi x l c chia lm ba giai on: Ly lnh (feeching), gii m lnh (decording) v x l lnh (excution). Nhng b VXL c in 8 bit tin hnh ba giai on trn mt cch tun t. T cc b VXL 16 bit tr i, b VXL dng pipeline (xen k dng lnh) tit kim thi gian x l. M lnh dnh cho VXL c vit di dng m nh phn. con ngi c th lp trnh v hiu c VXL, ngi ta dng hp ng (assembly language) miu t cc lnh my bng t hp cc k t gi nh (mnemonic).
Mt lnh m t bng m nh phn c th di t 1 n 6 byte. Cu trc chung ca mt m lnh bao gm:
- Prefix i trc m lnh.
- M ton (operation code) phn bit l lnh g, v d vi lnh dch chuyn MOV c m ton l 100010.
- Ton hng (operand) cho bit ci g c x l (ni dung ca thanh ghi hay b nh).
- a ch trc tip (2 byte).
Ni dung ca m lnh c quy nh kh cht ch. hnh 4-1 di y cho thy cu trc nh phn ca mt lnh dch chuyn MOV ch, ngun dng chuyn d liu gia 2 thanh ghi hoc gia nh v thanh ghi.
100010a ch
phn thpa ch
phn cao
M lnhDWMODREGM/R
Byte 1
Byte 2
Byte 3
Byte 4
Hnh 4-1: Cu trc m lnh
- Bit D (direction) ch hng cho thanh ghi REG. D=1 ch d liu i n REG; D=0 th ch d liu i t REG.
- Bit W (Word) ch xem thanh ghi c dng l 8 bit hay 16 bit (1 word). W=1 c ngha l thanh ghi 16 bit c dng. Bng 4-1 cho thy cch m ho cc thanh ghi trong b VXL:
- Hai bit MOD (mode, ch ) v ba bit R/M (register/memory, thanh ghi/b nh) to ra 5 bit, dng ch ch a ch ca lnh. Nhng ch ny c quy nh trong bng 4-1. Bng 4-2 cho thy cch m ho cc ch a ch (cch tm ra cc ton hng) bng cc bit ny.
Bng 4-1: Cch m ho cc thanh ghi trong b VXL.
Thanh ghi
W=1Thanh ghi
W=0M REGThanh ghi onM
AX
BX
CX
DX
SP
DI
BP
SIAL
BL
CL
DL
AH
BH
CH
DH000
011
001
010
100
111
101
110ES
CS
SS
DS00
01
10
11
Bng 4-2: Phi hp MOD v R/M to ra cc ch a ch.
MOD
R/M00011011
W=0 W=1
000[BX] + [SI][BX] + [SI] + d8[BX] + [SI] + d16AL AX
001[BX] + [DI][BX] + [DI] + d8[BX] + [DI] + d16CL CX
010[BP] + [SI][BP] + [SI] + d8[BP] + [SI] + d16DL DX
011[BP] + [DI][BP] + [DI] + d8[BP] + [DI] + d16BL BX
100[SI][SI] + d8[SI] + d16AH SP
101[DI][DI] + d8[DI] + d16CH BP
110
d16
(a ch trc tip)[BP] + d8[BP] + d16DH SI
111[BX][BX] + d8[BX] + d16BH DI
Ch b nh
Ch thanh ghi
Ghi ch: - d8: disp. 8 bit, d16: disp. 16 bit.
- Cc ga tr cho trong cc ct 2, 3, 4 l cc a ch hiu dng (EA) s c cng vi DS to ra a ch vt l (ring BP phi c cng vi SP).
V d 1: M ho cc lnh: a. MOV CL,[BX]; b. MOV 0F3H[SI],CL.
a. MOV CL, [BX]
1000101000001111
Cc bit m ho CL; nh c a ch DS:BX;
Chuyn 1 bite; Opcode. Chuyn ti thanh ghi
b. MOV 0F3H[SI], CL
100010000100110011110011
Cc bit m ho CL; nh c a ch DS:SI; chuyn 1 bite;
Opcode. Chuyn t thanh ghi; d8 = F3H.
II. Tp lnh ca b vi x l.
Mi b vi x l c mt tp lnh xc nh, cc b vi x l th h sau thng c tp lnh c b sung, m rng hn so vi cc b vi x l th h trc n, iu c ngha cc b vi x l th h sau c th chy c cc chng trnh vit cho cc b vi x l trc. Nhng ngc li th khng hon ton ng.
Nh ni trn y, chng ta ly b vi x l Intel 8088 lm c s nghin cu nhng vn k thut ca cc b vi x l khc. V vy y chng ta cng s nghin cu tp lnh ca chnh b vi x l ny.
Tp lnh ca 8086/8088 gm hn 100 k hiu gi nh (mnemonic) ca lnh ngn ng assembler c s, quy nh cho b vi x l phi lm g. Mi lnh c s c th c nhiu bin cch. V d c ti 28 bin cch khc nhau cho lnh dch chuyn c s (MOV) ... . Tuy nhin trong chng trnh mn hc ny, chng ta ch xem xt mt s lnh cn thit theo mc tiu ca mn hc. Cc lnh m chng ta s nghin cu c chia lm 6 nhm:
1. Nhm lnh truyn d liu.
2. Nhm lnh s hc.
3. Nhm lnh logic.
4. Nhm lnh so snh.
5. Nhm lnh iu khin chng trnh.
6. Cc lnh c bit.
II.1 . Nhm lnh truyn d liu (khng nh hng n cc c).
MOV lnh di chuyn d lu c bn . Lnh ny cth s dng di chuyn byte (8 bit) hoc li (16 bit) ca d liu. Cu trc lnh :
MOV ch, ngun.
Trong ton hng ch v gc c th tm theo cc a ch khc nhau, nhng phi c cng di v khng c php ng thi l 2 nh hoc 2 thanh ghi on.
Cc v d cho trong bng 4-3:
Bng 4-3 cc v d v lnh MOV.
chNgunV dGii thch
1 B nh
2 Thanh ghi
3 Thanh ghi
4 Thanh ghi
Thanh ghi
B nh
Thanh ghi
Tc thiMOV 100H, AX
MOV AX, MEM1
MOV AX, BX
MOV AX, 0FFFFH- chuyn ni dung trong AX vo v tr nh 100H.
- Chuyn ni dung trong v tr nh do nhn MEM1 ch ra vo thanh ghi AX.
- Chuyn ni dung trong BX vo thanh ghi AX.
- Chuyn gi tr hng s FFFFH vo thanh ghi AX; s 0 u c dng phn bit v ch r FFFFH l mt gi tr hng ch khng phi l mt nhn.
XCHG -exchange two operands (hon i ni dung 2 ton hng).
Vit lnh:
XCHG ch, Ngun
Trong ton hng ch v ngun c th tm c theo cc ch a ch khc nhau, nhng phi c cng di v khng c php ng thi l 2 nhv cng khng c l thanh ghi on.
V d:
XCHG AH, AL; tro ni dung AH v AL.
XCHG AL, [BX]; tro ni dung AL vi nh c a ch DS:BX.
IN- Input data from a port (c d liu t cng vo thanh Acc)
Vit lnh:
IN Acc, Port
Port l a ch 8 bit ca cng, n c th c gi tr trong khong 00H..FFH.
Nu Acc l AL th d liu 8 bit c a vo t cng Port.
Nu Acc l AX th d liu 16 bit c a vo t cng Port v Port+1.
C th biu din a ch cng thng qua thanh ghi DX v nh vy a ch cng c a ch ho linh hot hn. Lc ny a ch cng nm trong di 0000H..FFFFH v lnh c vit nh sau:
IN Acc, DX
Trong DX phi c gn t trc gi tr ng vi cng.
OUT- Output a byte or word to a port ( a d liu ra cng t Acc).
Vit lnh:
OUT Port, Acc
Nu Acc l AL th d liu 8 bit c a ra cng Por
Nu Acc l AH th d liu 16 bit c a ra cng Port v cng Port+1.
Tng t vi lnh IN, y cng c th dng thanh ghi DX cha a ch cng. Khi lnh c vit nh sau:
OUT DX, Acc.
Thanh ghi DX phi c np a ch cng t trc.
LEA (load effective address). Lnh np a ch hiu dng vo thanh ghi, n khng di chuyn ni dung cha trong a ch . y l lnh tnh a ch lch hoc a ch ca nh chn lm gc ri np vo thanh ghi chn.
Vit lnh:
LEA ch, ngun.
trong :
- ch thng l mt trong cc thanh ghi BX, CX, DX, BP, SI, DI.
- Ngun l tn bin trong on DS c ch r trong lnh hoc nh c th.
V d:
LEA DX, MSG ; Np a ch lch ca bn tin MSG vo DX.
LEA CX, [BX] [DI] ; Np vo CX a ch hiu dng do
; BX v DI ch ra: EA=BX+DI.
PUSH/POP Thanh ghi ngn xp l ni rt thun tin ct gi tm d liu v cc ton hng cn nh ca chng trnh. V d, mt chng trnh c th mun ct li cc ni dung trong thanh ghi AX dng trong mt s thao tc sau ny. thc hin nhim v c th dng cc lnh PUSH v POP.
- PUSH Ct d liu vo ngn xp.Vit lnh:
PUSH ngun
M t:
SP (SP - 2
Ngun ( {SP}.
trong ton hng gc c th tm c theo cc ch a ch khc nhau: c th l cc thanh ghi a nng, thanh ghi on hoc nh. Lnh ny thng dng vi lnh POP nh mt cp i ngu x l cc d liu v trng thi ca chung trnh chnh khi vo/ra chng trnh con.
V d:
PUSH BX
; ct BX vo ngn xp, ti v tr do SP ch ra.
PUSH Table[BX] ; ct 2 byte ca vng d liu DS
; c a ch u ti (Table+BX).
- POP Ly d liu t ngn xp.Vit lnh:
POP ch
M t:
ch ( {SP}.
SP (SP + 2
trong ton hng gc c th tm c theo cc ch a ch khc nhau: c th l cc thanh ghi a nng, thanh ghi on (nhng khng c l thanh ghi o m CS) hoc nh.D liu ti ngn xp khng thay i. Gi tr ca SS khng thay i. V d:
POP DX
; ly 2 byte t nh ngn xp, a vo DX.
PUSH Table[BX] ; ly 2 byte nh ngn xp ri ti vng DS
; c a ch u ti (Table+BX).
PUSHF/POPF Cc ni dung ca thanh ghi c c th c gi vo hay ly ra khi ngn xp bng cc lnh PUSPF v POPF.
- PUSHF Ct ni dung thanh ghi c vo ngn xp.
Vit lnh:
PUSHF
M t:
SP (SP - 2
RF ( {SP}.
D liu ti thanh ghi c khng thay i. SS khng thay i.
- POPF Ly 1 t, t nh ngn xp a vo thanh ghi c.
Vit lnh:
POPF
M t:
RF ( {SP}.
SP (SP + 2
Sau lnh ny d liu ti ngn xp khng thay i. SS khng thay i.
II.2. Nhm lnh s hc (l nhm lnh c nh hng n c).
Cc lnh s hc bao gm bn php tnh s hc c bn l cng, tr , nhn, chia v o du ton hng.
ADD/SUB Dng tng qut ca cc lnh cng (add) v tr (subtract) l:
ADD ch, ngun
SUB ch, ngun
M t:ADD: ch ( ch + Ngun
SUB : ch ( ch -Ngun
trong cc ton hng ch, ngun c th tm c theo cc a ch khc nhau, nhng phi cha d liu c cng di v khng c php ng thi l hai nh v cng khng c l thanh ghi on.
Bng 4-4 tm tt cc loi khc nhau ca cc ton hng ch v ngun dng trong cc lnh cng v tr:
Bng 4-4. cc dng ton hng trong lnh ADD/SUB:
ch (ni n)Ngun (gc)
Thanh ghi
Thanh ghi
B nh
B nh
Thanh ghiThanh ghi
B nh
Thanh ghi
Tc thi (hng s)
Tc thi(hng s)
V d 1:
ADD AX, BX
; AX ( AX+BX
ADD AL, 74H
; AX ( AX+ 74H
SUB CL, AL
; CL ( CL - AL
SUB AX, 0405H
; AX ( AX - 0405H.
V d 2: Vit on chng trnh ngn ng assembly cng 5H vi 3H, dng cc thanh ghi AL, BL.
MOV AL, 05H; AL ( 05H
MOV BL, 03H; BL ( 03H
ADD AL, BL; AL ( 05H+03H =08H
MOV 100H, AL; Di chuyn kt qu t AL vo v tr nh DS:100H.
MUL/DIV Dng tng qut ca lnh nhn (multiply, MUL) v chia (divide, DIV) l:
MUL s nhn ngun
DIV s chia ngun
trong s nhn ngun (ton hng gc) c th tm c theo cc ch a ch khc nhau. Khi dng lnh nhn, s c nhn phi c chuyn vo thanh ghi AX hoc AL. Cn s nhn th c th chuyn vo thanh ghi khc bt k hoc mt a ch nh.
V d 2:
MUL BX
; s nhn nm trong thanh ghi BX
MUL MEM1; s nhn nm trong a ch nh mang nhn MEM1
Khi hai byte nhn vi nhau th kt qu c gi lu vo thanh ghi AX.
V d 3. Vit on chng trnh nhn 5H vi 3H, dng thanh ghi CL.
MOV AL, 05H; AL ( 05H (s c nhn)
MOV CL, 03H; CL ( 03H (s nhn)
MUL CL
; AL ( 0FH (kt qu)
MOV MEM1, AL; chuyn kt qu (0FH)
; t AL vo v tr nh c nhn MEM1.
Khi nhn hai li (16 bit) vi nhau th s c nhn phi chuyn vo thanh ghi AX, cn s nhn c th trong mt thanh ghi khc bt k hoc trong v tr nh 16 bite. kt qu s l con s 32 bit (hoc hai li) v c cha trong cc thanh ghi DX v AX. Li c trng s ln s trong thanh ghi DX v li c trng s nh s trong thanh ghi AX.
V d 4. Vit on chng trnh nhn 3A62H vi 2B14H.
MOV AX, 3A62H
; AX ( 3A62H
MOV CX, 2B14H
; CX ( 2B14H
MUL CX
; DXAX ( tch = 289C63A8H
Cc lnh chia, v c bn, cng ging nh cc lnh nhn. Trong php chia c byte, s chia l mt byte c th trong mt thanh ghi hoc mt v tr nh. S b chia phi l mt s khng du 16 bit cha trong thanh ghi AX. Kt qu thng s s trong thanh ghi AL, cn s d th trong thanh ghi AH. i vi php chia c li th s chia 16 bit c th t trong thanh ghi hoc mt v tr nh. Cn s b chia phi l mt s khng du 32 bit c t trong cc thanh ghi DX v AX. Thanh ghi DX s gi li c trng s cao, thanh ghi AX s gi li c trng s thp. Kt qu thng t trong thanh ghi AX, cn s d t trong thanh ghi DX.
V d 5: Vit on chng trnh chia 6H cho 3H, dng thanh ghi CL.
MOV AX, 0006H
; AX ( 6H
MOV CL, 03H
; CL ( 3H
DIV CL
; AHAL ( 00H (s d), 02H (thng s)
Ch : 6H c a vo thnh 0006H lp y ton b thanh ghi AX. Nh vy cc byte trng s cao ca AX s b xo trnh b li.
V d 6: Vit on chng trnh chia 1A034H cho 1002H, dng thanh ghi BX
MOV AX, 0A034H; AX ( 0A034H
MOV DX, 0001H
; DX ( 0001H
MOV BX, 1002H
; BX ( 1002H
DIV BX
; DXAX ( 00H (s d)1AH (thng s)
INC/DEC y l lnh tng (increment) v gim (decrement). Lnh tng s cng thm mt n v vo ton hng, cn lnh gim s tr mt n v vo ton hng. Cc lnh ny rt cn i vi thao tc m. Dng tng qut ca cc lnh INC v DEC l:
INC ch M t: ch ( ch +1
DEC ch M t: ch ( ch -1
Ton hng ch c th l mt thanh ghi hoc mt v tr nh bt k, c th l 1 li 16 bit hoc 1 byte; c th tm c theo cc ch a ch khc nhau.
Ch :
- Trong lnh tng, nu ch = FFH (hoc FFFFH) th ch + 1 = 00H (hoc 0000H) m khng nh hng n c nh. Lnh ny cho kt qu tng ng nh lnh ADD ch, 1 nhng chy nhanh hn.
- Trong lnh gim, nu ch l 00H (hoc 0000H) th ch -1 = FFH (hoc FFFFH) m khng nh hng n c nh CF. Lnh ny cho kt qu tng ng vi lnh SUB ch, 1 nhng chy nhanh hn.
NEG- Negative a Operand (ly b 2 ca mt ton hng hay o du ton hng).
Vit lnh:NEG ch
V d:
NEG AH
; AH ( 0 - (AH)
NEG BYTE PTR[BX]; ly b 2 ca nh do BX ch ra trong DS.
II.3. Nhm lnh logic (c nh hng n c).
Cc lnh logic nhm thc hin cc php tnh Boolean NOT, AND v OR. Lnh NOT th o tt c cc bit trong ton hng (byte boc li). Cc lnh AND/OR thc hin cc php tnh AND/OR i vi mt i bit trong ton hng ngun v ton hng ch. Cc lnh ny c th dng vi cc ton hng c li hoc c byte.
NOT Ly b ca mt ton hng, o bit ca mt ton hng.
Vit lnh: NOT ch.
M t: ch ( (ch)trong ton hng ch c th tm c theo cc ch a ch khc nhau.
Lnh ny khng tc ng n c.
V d 1: Xc nh kt qu ca on chng trnh sau:
MOV BL, 00110011B
NOT BL
MOV MEM1, BL
Ni dung ca thanh ghi BL c np vo l 00110011B. Sau khi thc hin php NOT th ni dung ca thanh ghi BL l 11001100B v gi tr ny c a va v tr nh c ch ra bi nhn MEM1.
AND/OR: V/Hoc hai ton hng. dng tng qut ca lnh AND/OR l:
AND ch, Ngun
OR ch, Ngun
trong ton hng ch v ngun c th tm c theo cc ch a ch khc nhau, nhng phi cha d liu cng di v khng c php ng thi l hai nh v cng khng c l thanh ghi on.
AND/OR s thc hin php tnh Boolean i vi cc ton hng ngun v ch. Php AND thng dng che i/gi li mt vi bit no ca mt ton hng bng cch nhn logic ton hng vi ton hng tc thi c cc bit 0/1 ti cc v tr cn che/gi li tng ng. Php OR thng dng lp mt vi bit no ca ton hng bng cch cng lgic ton hng vi ton hng tc thi c cc bit 1 ti cc v tr tng ng cn thit lp (ton hng tc thi trong nhng trng hp ny cn c gi l mt n).
V d 2 :
AND AL, BL ; ni dung thanh ghi BL c giao vi ni dung trong
; thanh ghi AL v kt qu c lu trong thanh ghi
; AL(AX). Nu con s trong AL l 00001101B v
; trong BL l 00110011B th kt qu trong thanh ghi
; AL sau php AND l: AL 0000001B.
OR AL, BL ; ni dung thanh ghi BL c hp vi ni dung trong
; thanh ghi AL tng bit mt v kt qu c lu trong
;thanh ghi AL(AX). Nu con s trong AL l
; 00001101B v trong BL l 00110011B th kt qu
;trong thanh ghi AL sau php AND l: AL 0011111B.
V d 3:
AND BL, 0FH ; che 4 bit cao ca BL.
OR BL, 30H ; lp 4 bit b4 v b5 ca BL ln 1.
SAL- Shift arithmetically Left (Dch tri s hc)/ SHL- Shift (Logically) Left (Dch tri logic).
Vit lnh:SAL ch, CL
SHL ch, CL
M t:
Mi ln dch MSB s c a qua c CF v 0 c a vo LSB. Thao tc kiu ny c gi l dch logic. CL phi c cha sn s ln dch mong mun. Thc cht mi ln dch tri tng ng vi mt ln lm php nhn vi 2 ca s khng du. V vy ta c th lm php nhn s b nhn khng du vi 2i bng cch dch tri s hc s b nhn i ln. Chnh v vy thao tc ny cn c gi l dch tri s hc.
Sau lnh SAL/SHL, c CF mang gi tr c ca MSB, v vy lnh ny c dng to c CF t gi tr ca MSB lm iu kin cho cc lnh nhy c iu kin. Cn c OF ( 1 nu sau khi dch 1 ln m bit MSB b thay i so vi trc khi dch, c ny khng c xc nh sau nhiu ln dch.
Lnh ny cp nht cc c SF, ZF, PF. Trong PF ch c ngha khi ton hng l 8 bit; c AF khng xc nh.
SAR - Shift Arithmetically Right (Dch phi s hc).
Vit lnh:SAR ch, CL
M t:
Sau mi ln dch phi, MSB c gi nguyn (nu y l bit du th du lun khng i sau cc ln dch. Cn LSB c a vo c CF, CL phi c cha sn s ln dch mong mun. Kiu dch ny tng ng vi mt ln chia cho 2ca s c du. V vy c th thay php chia cho 2
ROL - Rotate All Bit to the Left (Quay vng sang tri).
Vit lnh:ROL ch, CL
M t:
Lnh ny dng quay ton hng sang tri, MSB s c a qua c CF v LSB. CL phi cha s ln quay mong mun.
Sau lnh ROL c CF mang gi tr c ca MSB, v vy lnh ny c dng to c CF t gi tr ca MSB lm iu kin cho cc lnh nhy c iu kin. Cn c OF ( 1 nu sau khi dch 1 ln m bit MSB b thay i so vi trc khi dch, c ny khng c xc nh sau nhiu ln dch. Lnh ny tc ng vo cc c CF, OF.
V d:
ROL BX, 1
; quay vng sang tri thanh ghi BX.
MOV CL, 4
; t s ln quay vo thanh ghi CL.
ROL AL, CL; quay vng sang tri thanh ghi AL 4 ln.
ROR - Rotate All Bit to the Right (Quay vng sang phi).
Vit lnh:ROR ch, CL
M t:
Lnh ny dng quay ton hng sang phi, LSB s c a qua c CF v MSB. CL phi cha s ln quay mong mun.
II.4. Nhm lnh so snh.
CMP - Compare Byte or Word (so snh 2 byte hay 2 t).
Vit lnh:
CMP ch, Gc.
Trong ton hng ch v gc c th tm c theo cc ch a ch khc nhau, nhng phi cha d liu c cng di v khng c php ng thi l 2 nh.
Lnh ny ch to cc c, khng lu kt qu so snh; sau lnh so snh, cc ton hng khng b thay i. lnh ny thng c dng to c cho cc lnh nhy c iu kin.
Cc c chnh theo quan h ch v ngun khi so snh 2 s khng du:
CF
ZF
ch = Ngun0
1
ch > Ngun0
0
ch < Ngun1
0.
TEST - And Operands to Update Flag (v 2 ton hng to c).
Vit lnh:
TEST ch, Ngun
Trong ton hng ch v ngun c th tm c theo cc ch a ch khc nhau, nhng phi cha d liu cng di v khng c php ng thi l 2 nh v cng khng c l thanh ghi on. Sau lnh ny cc ton hng khng b thay i v kt qu khng c lu gi. Cc c c to ra s c dng lm iu kin cho cc lnh nhy c iu kin. Lnh ny cng c tc dng che nh mt mt n.
Tc ng: Xo: CF, OF
Cp nht: PF, SF, ZF (PF ch lin quan n 8 bit thp)
Khng xc nh: AF.
V d:
TEST AH, AL
; V AH vi AL to c.
TEST AH, 01H
; Bit 0 ca AH = 0?
TEST BP, [BX][DI]; V BP vi nh DS:BX+DI.
II.5 Cc lnh iu khin chng trnh.
- Lnh nhy khng iu kin: Lnh ny khin b vi x l bt u thc hin mt lnh mi ti a ch c m t trong lnh.
Vit lnh:
JMP Nhn
Lnh mi bt u ti a ch ng vi nhn. Chng trnh dch s cn c vo v tr nhn xc nh gi tr dch chuyn.
- Lnh nhy c iu kin: Lnh ny biu din thao tc: nhy (c iu kin) ti nhn, tc l ch thc hin nhy ti nhn nu iu kin ch ra ng. Nhn phi nm cch xa (dch i mt khong) -128.. +127 byte so vi lnh tip theo sau lnh nhy c iu kin. Chng trnh dch s cn c vo v tr ca nhn xc nh gi tr dch chuyn.
Cc lnh ny khng tc ng n c.
Ngi ta phn bit cc kiu nhy c iu kin:
+ Nhy theo kiu khng du:
JA/JNBE - Jump if Above/ Jump if Not Below or Equal.
Vit lnh: JA Nhn
JNBE Nhn
JAE/JNB- Jump if Above or Equal/ Jump if Not Below.
Vit lnh:JAE Nhn
JNB Nhn
JB/JNAE- Jump if Below/ Jump if Not Above or Equal.
Vit lnh:JB Nhn
JNAE Nhn.
V d 1:
CMP AL, 10H; so snh AL vi 10H.
JA MEM1
; nhy n nhn MEM1 nu AL cao hn 10H.
JB MEM2
;nhy n nhn MEM2 nu AL thp hn 10H.
+ Nhy theo kiu c du:
JG/JNLE- Jump if Greater than/ Jump if Not Less than or Equal.
Vit lnh:JG Nhn
JNLE Nhn.
JGE/JNL- Jump if Greater than or Equal/ Jump if Not Less than.
Vit lnh:JGE Nhn
JNL Nhn.
JL/JNGE- Jump if Less than/ Jump if Not Greater than or Equal.
JLE/JNG- Jump if Less than or Equal/ Jump if Not Greater than.
+ Nhy theo kiu n.
JE/JZ- Jump if Equal/ Jump if Zero.
JNE/JNZ- Jump if Not Equal/ Jump if Not Zero.
JC- Jump if Carry
JNC- Jump if Not Carry
JO- Jump if Overflow
JNO- Jump if Not Overflow
JS- Jump if Sign
JNS- Jump if Not Sign
JP/JPE- Jump if Parity/ Jump if Parity Even
JNP/JPO- Jump if Not Parity/ Jump if Parity Odd
- Lnh lp: Lnh ny dng lp li on chng trnh (bao gm cc lnh nm trong khong t nhn n ht lnh LOOP Nhn cho n khi s ln lp CX=0. iu ny c ngha l trc khi vo vng lp, ta phi a s ln lp mong mun vo thanh ghi CX v sau mi ln thc hin lnh LOOP Nhn th CX t ng gim i 1.
Nhn phi nm cch xa (dch mt khong) -128 byte so vi lnh tip theo sau lnh LOOP.
Lnh ny khng tc ng n c.
Vit lnh:
LOOP Nhn
V d:
XOR AL, Al; xo AL
MOV CX, 16; s ln lp a vo CX
Lap: INC AL
; tng AL ln 1
LOOP Lap
; lp li 16 ln, AL =16.
- Lnh JCXZ- Jump if CX is Zero (nhy nu CX = 0).
Vit lnh: JCXZ Nhn
y l lnh nhy c iu kin ti nhn nu ni dung thanh m bng 0 v khng c lin h g vi c ZF. Nhn phi nm cch xa (dch i mt khong) -128.. +127 byte so vi lnh tip theo sau lnh JCXZ. Chng trnh dch s cn c vo v tr nhn xc nh gi tr dch chuyn.
- Lnh gi chng trnh con CALL: Lnh ny dng chuyn hot ng ca b vi x l t chng trnh chnh (CTC) sang chng trnh con (ctc). Nu ctc cng mt on m vi CTC th ta c gi gn. Nu CTC v ctc nm trong hai on m khc nhau th ta c gi xa. Gi gn v gi xa khc nhau v cch to a ch tr v. a ch tr v l a ch tip theo ngay sau lnh CALL. Khi gi gn th ch cn ct IP ca a ch tr v, khi gi xa th phi ct c CS v IP ca a ch tr v. a ch tr v c t ng ct vo ngn xp khi bt u thuc hin lnh gi v c t ng ly ra khi gp lnh tr v RET.
-RET - Return from Procedure to Calling Program (Tr v CTC t ctc).
Vit lnh:RET
Khi gp lnh tr v RET, vi x l kt thc ctc ly li a ch tr v, bao gm a ch IP (trng hp gi gn) hoc IP v CS (trong trng hp gi xa) ca lnh tip theo sau lnh CALL, c t trong ngn xp.
- INT - Interrupt Program Excution (Ngt, gin on chng trnh ang chy). Vit lnh:INT N, N = 0.. FFH
M t: Cc thao tc ca b vi x l khi chy lnh INT :
1. SP ( SP - 2. {SP} ( FR
2. IF ( 0 (cm cc ngt khc tc ng), TF ( 0 (chy sut).
3. SP ( SP - 2, {SP} ( CS.
4. SP ( SP - 2, {SP} ( IP.
5. {N x 4} ( IP, {5N x 4 + 2} ( CS.
Mi lnh ngt ng vi mt chng trnh phc v ngt khc nhau c a ch ly t bng vc t ngt. Bng ny gmg 256 vec t, cha a ch ca cc chng trnh phc v ngt tng ng v chim 1 Kb RAM c a ch thp nht.
V d nh cc chng trnh phc v ngt ca BIOS, ca DOS nh IO.SYS, MSDOS.SYS.
V d:
INT 21H
III. Cc ch a ch
Nhng phng php nh a ch hay cn gi l ch a ch (addressing mod) c dng vi x l tm ra (nh v, addressing) cc ton hng cn thit cho mt lnh no . Mt b vi x l c th c nhiu ch a ch, cc ch a ch ny c xc nh ngay t khi ch to b vi x l v sau ny khng th thay i c. H vi x l Intel c by ch a ch nh sau:
1. Ch a ch thanh ghi
2. Ch a ch tc th
3. Ch a ch trc tip
4. Ch a ch gin tip thanh ghi
5. Ch a ch tng i c s
6. Ch a ch tng i ch s
7. Ch a ch tng i ch s c s
III.1. Ch a ch thanh ghi (register addressing).
Trong ch a ch ny ngi ta dng cc thanh ghi bn trong CPU nh l cc ton hng cha d liu cn thao tc. V vy khi thc hin lnh c th t tc truy nhp cao hn so vi cc lnh c truy nhp n b nh.
V d:
MOV AX, BX ; chuyn ni dung BX vo AX.
ADD DS, DL; cng ni dung AL v DL , kt qu gi trong AL.
III.2. Ch a ch tc th (immediate addressing)
Trong ch a ch ny ton hng ch l mt thanh ghi hay mt nh, cn ton hng ngun l mt hng s v ta c th tm thy ton hng ny ngay sau m lnh (chnh v vy ch a ch ny gi l ch a ch tc th). Ta c th dng ch ny np d liu cn thao tc vo bt k thanh ghi no (tr cc thanh ghi on v cc thanh ghi c) hoc vo bt k nh no trong on d liu DS.
V d:
MOV AX, 4EH
; chuyn gi tr 4EH vo thanh ghi AX.
MOV AX, 0FFOH ; chuyn 0FF0H vo thanh ghi AX
MOV DS, AX
; a vo DS.
MOV [BX], 4EH
; chuyn 4EH vo a ch nh DS:BX
III.3. Ch a ch trc tip (direct addresssing mode)
Trong ch a ch ny mt ton hng cha a ch lch ca nh dng cha d liu, cn ton hng kia ch c th l mt thanh ghi m khng th l mt v tr nh.
Nu so snh vi ch a ch tc th ta thy y ngay sau m lnh khng phi l mt ton hng m l mt a ch lch ca ton hng. Xt v phng din a ch th l a ch trc tip.
V d:
MOV AL, [1234H]; chuyn ni dung nh DS:1234H vo AL.
MOV [4321H], CX; chuyn ni dung CX vo 2 v tr nh
; lin tip l DS:4321 v DS:4322.
III.4. Ch a ch gin tip qua thanh ghi (register indirect addressing).
Trong ch a ch ny mt ton hng l mt thanh ghi c s dng cha a ch lch ca nh cha d liu, cn ton hng kia ch c th l mt thanh ghi m khng c l nh.
V d:
MOV AL, [BX]
; chuyn ni dung ti nh DS:BX vo AL.
MOV [SI], CL
; chuyn ni dung CL vo nh DS:SI.
III.5. Ch a ch tng i c s (based relative addresing).
Trong ch ny cc thanh ghi c s nh BX v BP v cc hng s biu din cc gi tr dch chuyn (displacement values) c dng tnh a ch hiu dng ca ton hng trong cc vng nh DS v SS. S c mt ca cc gi tr dich chuyn xc nh tnh tng i (so vi c s) ca a ch.
V d:
MOV CL, [BX] + 10; chuyn ni dung 2 nh lin tip c a
; ch DS:(BX+10) v DS:(BX+11) vo CX.
MOV CX, [BX +10]; tng t nh lnh trn.
MOV AL, [BP] + 10; chuyn ni dung nh SS:(BP+10) vo AL
III. 6. Ch a ch tng i ch s (indexed relative addressing).
Trong ch a ch ny cc thanh ghi ch s nh SI v DI v cc hng s biu din cc gi tr dch chuyn (displacement values) c dng tnh a ch ca ton hng trong vng nh DS.
V d:
MOV AL, [SI]+10
; chuyn ni dung nh DS:(SI+10) vo AL.
MOV AL, [SI+10]
; tng t nh trn.
III.7. Ch a ch tng i ch s c s (based indexed relative addressing).
Kt hp hai ch a ch ch s v c s ta c ch a ch ch s c s. Trong ch a ch ny ta dng c thanh ghi c s v thanh ghi ch s tnh a ch ca ton hng. Nu ta dng thm c thnh phn biu din s dch chuyn ca a ch th ta c ch a ch phc hp cho ch a ch ho cc mng hai chiu.
V d:
MOV AL, [BP][SI]+10; chuyn ni dung DS:(BX+SI+10) vo AL.
MOV AL, [BP+SI+10]; tng t nh trn.
Khi dng thanh ghi ch s , thanh ghi c s v thanh ghi con tr th nhng cp a ch on v a ch lch sau s c nh ngha trc:
CS:IP, DS:SI, DS:DI, DS:BX, ES:DI, SS:SP, SS:BP.
Mun loi b gi tr ngm nh cho BX trong thanh ghi on DS v dng gi tr trong thanh ghi on ES ta cn vit:
MOV AL, ES:[BX]; chuyn ni dung ES:BX vo AL.
CHNG V. CC BUS TRONG VI X L V MY VI TNH
I. Chc nng v thng s ca BUS
Mt trong nhng hot ng v chc nng c bn ca my tnh l truyn s liu (data transfer). S hot ng ca my tnh do cc b vi x l iu khin. B vi x l v cc chip h tr khc n lt mnh cng thng xuyn phi truyn s liu gia cc khi, b phn trong v ngoi chng vi nhau.
V c rt nhiu cc b phn , khi ring r trong bn thn cc Chip v cc ng truyn s liu rt a dng, nn mt cch hp l ta khng th thc hin cc ng ni gia cc b phn , khi tng i mt vi nhau m ta ni chung tt c cc li vo/ li ra ca cc khi ring r vi nhau ln mt h thng cc ng dn chung; h thng ny c gi l bus.
Hnh 5.1. Cc bus trong mt h thng my tnh.
Cc b phn, khi c ni ln bus phi tho mn mt yu cu l c kh nng c ct ra hoc ni tr li theo lnh ca iu khin. Lc mt output c ct ra khi bus, n trng thi tr khng cao (High impedance, Hi-Z).
Quy tc nghim ngt ca truyn s liu l trong mi thi im, ti a ch c mt output c cp s liu ln bus.
Do trong mi thi im mt output thng cn phi ng thi cp s liu cho nhiu input, cho nn n cn phi c kh nng pht ra (source) mc logic cao hoc nut vo (sink) mc logic thp, mt dng in ln ti vi chc mA cp cho cc input , ng vai tr ti ca output.
Thng s c trng cho ng bus l tr khng vo ca n (gm c in tr thun v dung khng). Thng in tr thun khong vi K( l tho mn yu cu ca output, ch c dung khng ca bus gy kh khn cho cc thit b output, (v n cn tr tng tc bin thin ca cc mc in p trn bus), do dung khng c xem l thng s c trng ca bus.
V d xt trng hp mt bus c in dung vo 100 pF. Nu mun tc bin thin in p trn bus l du/dt =2V/10ns th thit b output phi nut c dng in in dung l
i = dq/dt = C(du/dt) = 20 mA.
Cn c theo cu hnh ca cc thit b ni vo bus, ngi ta phn chng thnh 3 nhm nh sau:
- Output cp s liu cho bus.
- Input nhn s liu t bus.
- In/ Out khi l input, khi l output.
II. BUS trong my vi tnh.
II.1. Bus trong vi x l v bus b x l
Trong cc b vi x l c mt h thng cc bus dng truyn s liu, lnh, cc tn hiu iu khin ,... , gia cc khi bn trong ca n. Ngoi ra c mt h thng cc bus a ra ngoi qua cc chn ca n. Cc ng bus trong c iu khin bi khi iu khin tu thuc hoc vo ni dung lnh uc gii m hoc theo cc iu khin ngt ca bn ngoi a vo vi x l. Cc ng bus ny hot ng theo nhp ca mt clock bn trong vi x l.
Xt vi v d cc ng bus trong kin trc ca vi x l 8088 nh gii thiu trong chng III.
Cc bus trong vi x l truyn s liu gia cc khi vi nhau, c hai loi ng truyn, mt chiu v hai chiu. H cc ng bus ni vi cc b phn, khi bn ngoi vi x l gm 20 ng a ch (AD0 - AD 19), 8 ng s liu ( ), v cc ng thuc bus iu khin.
Chnh khi iu khin pht cc tn hiu iu khin cc bus.
Bus b vi x l l ng truyn dn gia CPU v cc chip h tr trung gian. Nhng chip h tr ny c gi l b chip (chip set). Bus ny dng truyn d liu gia CPU v bus h thng chnh hoc gia CPU v cache ngoi.
V mc ch ca bus b x l gi hoc nhn thng tin t CPU vi tc nhanh nht c th, nn bus ny hot ng nhanh hn nhiu so vi bt k bus no khc trong h thng v m bo trnh hin tng tc nghn y. Bus b x l bao gm bus d liu, bus a ch v bus iu khin. Trong mt h thng thit k cho VXL Pentium, bus b x l c 64 ng d liu, 32 ng a ch. Pentium Pro v Pentium II c 36 ng a ch.
Bus b x l hot ng tc ng h c s ging nh CPU chy ngoi tr. V d Pentium II 333MHz chy tc ng h 333MHz ni tr nhng ch 66,6 MHz ngoi tr.
Tc truyn ca bus b x l c xc nh bng cch nhn rng d liu vi tc ng h c s ri chia cho 8.
Khi thit k cc b vi x l, c th tu la chn loi bus bn trong vi x l, cn vi cc bus lin h vi bn ngoi cn phi xc nh r cc quy tc lm vic cng nh cc c im k thut v in v c kh ngi thit k Main Board c th ghp ni vi x l vi cc thit b khc. ni cch khc, cc bus ny phi tun theo mt chun nht nh. Tp cc quy tc ca chun cn c gi l nghi thc bus (bus protocol).
Trong th gii my tnh c rt nhiu loi bus khc nhauc s dng, cc bus ny ni chung l khng tng thch vi nhau. Sau y l mt s loi bus c dng ph bin:
Tn bus
Lnh vc p dng
- Camac
Vt l ht nhn
- EISA
Mt s h thng dng b VXL 8036
- IBM PC, PC/AT
My tnh IBM PC, IBM/PC/AT
- Massbus
My PDP - 1 v VAX
- Microchannel
My PS/2
- Multibus I
Mt s h thng c VXL 8088, 8086
- Multibus II
Mt s h thng c VXL 80386
- Versabus
Mt s h thng dng VXL Motorola
- VME
Mt s h thng dng VXL 68x0 ca Motorola.
Ngi ta thng phn loi bus theo ba cch sau:
1. Theo t chc phn cng (nh cc loi bus nu trn)
2. Theo nghi thc truyn thng (bus ng b v khng ng b).
3. Theo loi tn hiu truyn trn bus (bus a ch, bus d liu ...)
S lm vic ca cc bus
Thng c nhiu thit b ni vi bus, mt s l thit b tch cc v c th i hi truyn thng tin trn bus, trong khi li c cc thit b th ng ch cc yu cu t cc thit b khc. Cc thit b tch cc c gi l ch bus (master), cn cc thit b th ng l t (slave).
Khi CPU ra lnh cho b iu khin a c/ ghi mt khi d liu th CPU l master c b iu khin a l slave. Tuy nhin khi b iu khin a ra lnh cho b nh nhn d liu m n c t a th n li gi vai tr ca master.
Bus Driver v Bus Receiver.
Tn hiu in m cc thit b trong my tnh pht ra thng khng mnh iu khin c bus, nht l khi bus kh di v c nhiu thit b ni vi n. Chnh v vy m hu ht cc bus master c ni vi bus thng qua mt chip c gi l bus driver, v cn bn l b khuych i tn hiu s. Tng t nh vy, hu ht cc slave bus c ni vi bus thng qua bus receiver. i vi cc thit b c th khi th ng vai tr master, khi th ng vai tr slave, ngi ta s dng mt chip kt hp, gi l transceiver. Cc chip ny ng vai tr ghp ni v thng l cc thit b 3 trng thi, cho php c th trng thi th ba: h mch (cn gi l th ni).
Ging nh MPU, bus c cc ng a ch, ng s liu v ng iu khin. Tuy nhin khng nht thit phi c nh x mt - mt gia cc tn hiu cc chn ra ca MPU v cc ng dy ca bus.
Nhng vn quan trng nht lin quan n thit k bus l: Nhp ng h bus (s phn chia thi gian, hay cn gi l bus cloking), c ch trng ti bus (bus arbitration), x l ngt v x l li.
Cc bus c th c chia theo nghi thc truyn thng tin thnh hai loi ring bit l bus ng b v bus khng ng b ph thuc vo vic s dng nhp ng h bus.
II.2. Bus ng b (Synchronous bus)
Bus ng b c mt ng dy iu khin bi mt b dao ng thch anh, tn hiu trn ng dy ny c dng sng vung, vi tn s thng nm trong khong 5MHz - 50 MHz. Mi hot ng bus xy ra trong mt s nguyn ln chu k ny v c gi l chu k bus.
Gin thi gian ca mt bus ng b vi tn s ng h l 4MHz, nh vy chu k bus l 250nS.
- T1 bt u bng sn ln ca tn hiu ng h (, trong mt phn thi gian ca T1, MPU t a ch ca byte cn c ln bus a ch. Sau khi tn hiu a ch c thit lp gi tr mi, MPU t cc tn hiu v tch cc. Tn hiu (memory request, truy cp b nh) ch khng phi thit b I/O; cn tn hiu (Read) chn Read.
- T2 l thi gian cn thit b nh gii m a ch v a d liu ln bus d liu.
- T3 ti sn xung xung ca T3, MPU nhn d liu trn bus d liu, cha vo thanh ghi bn trong MPU v cht d liu. Sau MPU o cc tn hiu v .
Nh vy kt thc mt thao tc c, ti chu k my tip theo MPU c th thc hin mt thao tc khc.
- TAD : theo gin thi gian, TAD 110ns, y l thng s do nh sn xut m bo, MPU s a ra tn hiu a ch khng chm hn 110ns tnh t thi im gia sn ln ca T1.
- TDS : Gi tr nh nht l 50ns, thng s ny cho php d liu c a ra n nh trn bus d liu t nht l 50ns trc thi im gia sn xung ca T3. Yu cu v thi gian ny m bo cho MPU c d liu liu tin cy.
Khong thi gian bt buc i vi TAD v TDS cng ni ln rng, trong trng hp xu nht, b nh ch c 250 + 250+ 125 - 110 - 50 = 465ns tnh t thi im c tn hiu a ch cho ti khi n a d liu ra bus a ch. Nu b nh khng p ng nhanh, n cn phi pht tn hiu xin ch trc sn xung ca T2. Thao tc ny a thm vo mt trng thi ch (wait state), khi b nh a ra d liu n nh, n s o tn hiu thnh WAIT.
- TML: m bo rng tn hiu a ch s c thit lp trc tn hiu t nht l 60ns. Khong thi gian ny l quan trng nu tn hiu iu khin s to ra tn hiu chn chip CS, bi v mt s chip nh i hi phi nhn c tn hiu a ch trc tn hiu chn chip. Nh vy khng th chn chip nh vi thi gian thit lp l 75ns.
- TM, TRL: Cc gi tr bt buc i vi 2 i lng ny c ngha l c hai tn hiu v s l tch cc trong khong thi gian 85ns tnh t thi im xung ca xung ng h T1. Trong trng hp xu nht, chip nh ch c 250 + 250 - 85- 50 = 365ns sau khi hai tn hiu trn l tch cc a d liu ra bus. S bt buc v thi gian ny b sung thm s bt buc thi gian vi tn hiu ng h.
- TMH, TRH: Hai i lng ny cho bit cn c bao nhiu thi gian cc tn hiu v s c o sau khi d liu c MPU c vo.
- TDH: Cho bit b nh cn phi lu d liu bao lu trn bus sau khi tn hiu o.
Block Transfer, truyn ti khi d liu.
Ngoi cc chu k c/ ghi, mt s bus ng b cn h tr truyn d liu theo khi. Khi mt thao tc c/ ghi bt u, bus master bo cho slave bit c bao nhiu byte cn truyn i, sau slave s lin tc a ra mi chu k mt byte, cho n khi s byte c thng bo. Nh vy, khi c d liu theo khi, n byte d liu cn n+2 chu k, thay cho 3n chu k nh trc.
Cch khc lm cho bus truyn d liu nhanh hn l lm cho cc chu k ngn li. Trong v d trn, mi byte c truyn i trong 750ns, vy bus c di thng l 1.33MBs. Nu xung ng h l 8MHz, thi gian mt chu k ch cn mt na, gii thng s l 2.67MBs.
Tuy vy vic gim chu k bus dn n cc kh khn v mt k thut, cc bit tn hiu truyn trn cc ng dy khc nhau trong bus khng phi lun c cng vn tc, dn n mt hiu ng, gi l bus skew.
Khi nghin cu v bus cn phi quan tm n vn tn hiu tch cc nn l mc thp hay mc cao. iu ny tu thuc vo ngi thit k bus xc nh mc no l thun li hn.
Bng 5.1. Gi tr ca mt s thng s thi gian
K hiuTham sMinMax
TADThi gian tr ca tn hiu a ch110
TMLThi gian a ch n nh trc tn hiu
60
TMThi gian tr ca so vi sn xung ca tn hiu ng h T185
TRLThi gian tr ca so vi sn xung ca tn hiu ng h T185
TDSThi gian thit lp d liu trc sn xung ca tn hiu ng h T350
TMHThi gian tr ca so vi sn xung ca tn hiu ng h T385
TRHThi gian tr ca so vi sn xung ca tn hiu ng h T385
TDHThi gian lu tr d liu t lc o tn hiu
0
II.3. Bus khng ng b (asynchronous bus).
Bus khng ng b khng s dng mt xung ng h nh nhp. Chu k ca n c th ko di tu v c th khc nhau i vi cc cp thit b trao i tin khc nhau.
Lm vic vi bus ng b d dng hn do n c nh thi mt cch gin on, tuy vy chnh c im ny cng dn n nhc im. Th nht l: mi cng vic c tin hnh trong nhng khong thi gian l bi s nhp ng h bus, nu mt thao tc no ca CPU hay b nh c th hon thnh trong 3,2 chu k th n s phi ko di thnh 4 chu k. iu hn ch ln na l chn chu k bus v xy dng b nh, I/O Card cho bus ny th kh c th tn dng c c nhng tin b ca cng ngh. Chng hn sau khi xy dng bus vi s nh thi nh trn, cng ngh mi a ra cc chip CPU v chip nh c thi gian chu k l 100ns (thay cho 250ns nh c), chng vn c phi chy vi tc thp nh cc CPU v chip nh loi c, bi v nghi thc bus i hi chip nh phi a ra d liu v n nh d liu ngay trc thi im ng vi sn xung ca T3. Nu c nhiu thit b khc nhau ni vi mt bus, trong c mt s thit b c th hot ng nhanh hn cc thit b khc th cn phi t bus hot ng ph hp vi thit b chm nht.
Bus khng ng b ra i nhm khc phc cc nhc im ca bus ng b. Hnh 5.3 minh ho s hot ng ca bus khng ng b, trong master yu cu c b nh.
Trc ht master cn pht ra a ch nh m n mun truy cp, sau pht tn hiu tch cc bo rng n mun truy cp b nh ch khng phi cng I/O. Tn hiu ny l cn thit v b nh v cc cng I/O u c th dng chung mt min a ch. Tip theo master phi pht tn hiu tch cc bn slave bit rng master s thc hin thao tc c ch khng phi l thao tc ghi.
Cc tn hiu v c a ra sau tn hiu nh a ch bao lu tu thuc vo tc ca master. Sau khi hai tn hiu ny n nh, master s pht tn hiu c bit, l (Master SYNchronization) mc tch cc bo cho slave bit rng cc tn hiu cn thit sn sng trn bus, slave c th nhn ly. Khi slave nhn cc tn hiu ny, n s thc hin cng vic vi tc nhanh nht c th c (nhanh chng a d liu ca nh yu cu ln bus d liu). Khi hon thnh, slave s pht tn hiu (Slave SYNchronization) tch cc.
Khi master nhn c tn hiu tch cc, n bit rng d liu ca slave sn sng v thc hin vic cht d liu, sau o cc ng a ch cng nh cc tn hiu v v .
Khi slave nhn c s o tn hiu thnh khng tch cc, n bit rng mt chu k kt thc v o tn hiu . By gi bus li tr li trng thi ban u, mi tn hiu u l khng tch cc, tt c sn sng ch bus master mi.
Trn gin thi gian ca bus khng ng b, ta s dng mi tn th hin nguyn nhn v kt qu. Vic a ln mc tch cc dn n vic truyn d liu ra bus d liu v ng thi cng dn n vic slave pht ra tn hiu tch cc. n lt mnh, tn hiu li gy ra s o mc ca cc ng a ch, v v . Cui cng s o mc ca li gy ra s o mc tn hiu v kt thc mt chu k c.
Full handshake.
Tp cc tn hiu phi hp vi nhau nh vy c gi l Full handshake, n ch yu gm c 4 s kin sau:
1. c t ln mc tch cc.
2. c t tch cc p li tn hiu
3. c o p li tn hiu
4. c o p li tn hiu thnh khng tch cc.
Ta c th nhn thy Full handshake l quan h nhn qu, c lp vi thi gian. Nu mt cp master-slave no hot ng chm hoc thi gian b ko di th cp master-slave k tip khng h b nh hng.
Tuy u im ca bus khng ng b rt r rng, nhng trong thc t phn ln cc bus ang c s dng l loi bus ng b. L do cn bn l cc h thng s dng bus ng b l d thit k hn. CPU ch cn chuyn cc mc tn hiu cn thit sang trng thi tch cc l cc chip nh p ng ngay, khng cn tn hiu phn hi. Ch cn cc chip c chn ph hp th mi hot ng u tri chy.
III. Trng ti bus (bus arbitration).
Trong h thng my tnh khng phi ch c CPU lm bus master, thc t cc chip I/O cng c lc phi lm ch bus c th c hoc ghi vo b nh v gi ngt; cc b ng x l cng c th lm ch bus. Nh vy cn phi gii quyt vn tranh chp khi c t hai thit b tr ln ng thi mun lm ch bus. gii quyt vn ny cn c mt c ch trng ti trnh s xung t. C ch trng ti c th l tp trung hoc khng tp trung.
III.1 Trng ti bus tp trung
Hnh 5.4 l mt v d n gin v trng ti bus tp trung. y, mt trng ti bus duy nht s quyt nh thit b no c l ch bus tip theo. Nhiu b VXL c n v trng ti bus c thit k ngay trong chip VXL, trong mt s my tnh mini, n v trng ti bus nm ngoi CPU.
Theo c ch ny, trng ti ch c th bit l c yu cu chim dng bus hay khng, ch khng bit c bao nhiu n v mun chim bus. Khi trng ti bus nhn c mt yu cu, n s pht ra mt tn hiu cho php trn ng dy bus grant (cho dng bus). ng dy ny ni qua tt c cc thit b vo/ ra theo kiu ni tip.
Khi thit b nm gn trng ti nht nhn c tn hiu cho php, n s kim tra xem c phi chnh n pht yu cu chim bus khng? Nu ng th n s chim ly bus v khng truyn tip tn hiuh cho php trn ng dy. Nu n kim tra thy khng phi l yu cu ca mnh th tip tc truyn tn hiu cho php ti thit b k tip trn ng dy.
Hnh 5.4. Trng ti bus tp trung c mt mc, mc ni tip.
Mt s loi bus c nhiu mc u tin, vi mi mc u tin c mt ng dy yu cu bus v mt ng dy cho chim bus. Hnh 5.5 l mt v d v bus c hai mc (cc bus trong thc t thng c 4, 8 hay 16 mc). Mi thit b trong h thng my tnh ni vi mt trong cc mc yu cu bus, cc thit b thng c s dng hn c gn vi ng dy c mc u tin cao hn.
Hnh 5.5. Trng ti bus tp trung c hai mc, mc ni tip.
Nu c mt s thit b cc mc u tin khc nhau cng yu cu, trng ti bus s ch pht tn hiu cho php i vi yu cu c mc u tin cao nht. Trong s cc thit b c cng mc u tin, thit b gn trng ti bus hn s c quyn u tin cao hn.
Mt s trng ti bus c ng dy th ba ni ti cc thit b cc thit b xc nhn vic nhn c tn hiu cho php v chim dng bus, gi l ng dy bin nhn acknowledgement (ACK). Ngay sau khi mt thit b pht tn hiu tch cc trn ng dy ACK, trng bus c th o tn hiu trn cc ng dy trn cc ng dy yu cu bus v cho php dng bus thnh mc khng tch cc. Kt qu l cc thit b khc c th i hi chim dng bus trong khi thit b u tin ang dng bus. Khi kt thc phin lm vic hin thi, bus master k tip s c la chn. Cch lm vic nh vy lm tng hiu qu s dng bus, nhng cn thm mt ng truyn tn hiu ACK v cu trc ca cc thit b cng phc tp hn. Cc chip ca Motorola s dng cc bus loi ny.
III.2 Trng ti bus khng tp trung
Trong c ch trng ti bus khng tp trung, khng cn s dng mt n v ring lm trng ti bus, nh vy gim c gi thnh phn cng. Trong mt s loi my tnh khc nhau, ngi ta s dng mt vi kiu trng ti bus theo c ch ny.
Trng ti bus khng tp trong trong multibus
Trong Multibus, ngi ta cho php c th la chn c ch trng ti bus khng tp trung hoc khng tp trung, c ch trng ti bus khng tp trung c thc hin theo s trn hnh 5.6
Hnh 5.6. Trng ti bus khng tp trung trong Multibus.
Ngi ta ch s dng 3 ng dy, khng ph thuc vo s lng thit b ni vi bus. Bao gm:
+ Yu cu chim dng bus (bus request)
+ Trng thi bus (bus busy), c bus master t mc tch cc
+ Trng ti bus, c mc ni tip qua cc thit b
Khi khng c thit b no yu cu chim bus, ng dy trng ti bus truyn mc tch cc ti tt c cc thit b. Khi mt n v no mun chim dng bus, u tin n kim tra bus c ri khng v kim tra u vo ca ng trng ti bus, nu thy c in p IN = 5V th n c th xin bus bng cch a tn hiu yu cu bus (Request) v xo tn hiu OUT, tc l t OUT = 0V. Do cc thit b u tin thp hn s khng xin c bus. Lc ny n tr thnh bus master.
IV. X l ngt
Mt chc nng quan trng ca bus l x l ngt. Khi CPU ra lnh cho mt thit b trong my tnh thc hin vic c, ghi hay x l tin, n thng ch i tn hiu ngt do thit b I/O pht ra khi hon thnh cng vic c CPU yu cu. Khi nhn c tn hiu ngt, CPU p ng ngay, c th l vic nhn d liu do thit b I/O chuyn v, cng c th l vic tip tc gi d liu ti thit b I/O hoc CPU s dng bus cho mt thao tc khc ... . Nh vy chnh ngt pht ra tn hiu yu cu bus.
V c th c nhiu thit b ngoi vi cng pht tn hiu ngt, cho nn cng cn
c mt c ch trng ti ging nh i vi cc bus thng thng. Gii php thng dng l gn cc mc u tin cho cc thit b v s dng mt trng ti tp trung trao quyn u tin cho cc thit b v s dng mt trongh ti tp trung trao quyn u tin cho cc thit b quan trng thng xuyn c s dng.
V. Mt s bus thng dng
V.1 Bus IBM PC
y l v d in hnh v mt loi bus c s dng trong cc h thng thng mi, n c s dng rng ri trong cc h thng vi x l da trn chip 8088. Hu ht h PC, k c cc my tng thch u s dng bus ny. Chnh bus IBM PC to nn c s cho bus IBM PC/AT v nhiu loi bus khc. Bus ny c 62 ng dy, trong c 20 ng a ch, 8 ng s liu v cc ng tn hiu khc. .... c lit k trong bng 5.1
V mt vt l, bus IBM PC c thit k ngay trn bo mch chnh v c khong gn chc u ni dng khe cm (slot) cm cc card m rng, trn mi khe cm c 62 chn c chia thnh hai hng.
Tn hiuS dyInOutgii thch
OSC1xChn dao ng (14,31818 MHz)
CLK1xXung ng h (4,77 MHHz)
RESET1xTn hiu reset CPU v cc thit b I/O
A0 - A920xCc ng dy a ch
D0 - D78xCc ng truyn d liu
ALE1xCht a ch
(MEMR)1xc b nh
(MEMW)1xGhi vo b nh
(IOR)1xc cng I/O
(IOW)1xGhi ra cng I/O
AEN1xAdress ENable, yu cu bus a ch
(IOCHCHK)1xI/O Chanel Check
IOCHRDY1xI/O Chanel Ready
IRQ2 - IRQ76xCc ng yu cu ngt
DRQ1 - DRQ33xDMA Request
DACK0 - DACK34xDMA Acknowleage
T/C1xTerminal/Count
Power5
GND3
Reserved1
Tn hiu ng h OSC v CLK
Cc my IBM PC u tin s dng cc phn t dao ng thch anh, tn s 14,31818 MHz, tn s ny c chn phi tho mn vic to ra tn hiu ng b mu h NTSC. Tn s ny cao hn so vi chun 8088 (tn s cc i l 5 MHz), do n c chia ba thnh 4,77MHz. Tn s 4,77 MHz c dng lm ng h chnh xc nh chu k bus. Tn hiu tn s 4,77 MHz cng c trn bus IBM PC v k hiu l CLK. Tn hiu ny khng cn xng nh tn hiu ng h 14,31818 MHz m trong mt chu k bao gm 2/3 thi gian mc thp v 1/3 thi gian mc cao.
Tn hiu RESET
Tn hiu RESET trn bus do chip 8284A to ra. RESET CPU, cc mch in bn ngoi gi tn hiu ti 8284A, n s t tn hiu reset ln mc tchs cc, buc CPU v cc thit b I/O kh to li.
Cc ng a ch v d liu
CPU khng ni trc tip vi cc ng a ch v ng s liu ca bus, m thng qua cc chip khc. Cc ng a ch c cht bng cch dng 3 chip 74LS373, mi chip l mt b 8 thanh ghi cht, tuy nhin ch s dng 20 trong s 24 ng c th.
Cc ng d liu s c ly mu (c nhanh gi tr) hoc cung cp gi tr trong nhng thi gian xc nh, nh trong sn dng ca mt tn hiu ng h no , v vy khng cn cht. Cc ng d liu ca bus c iu khin bi bus transceiver (chip 74LS245). Chn DIR xc nh hng ca tn hiu l i n hay i ra t CPU.
L do chnh ca vic ni cc chn ca MPU vi bn ngoi thng qua cc b m chnh l v n c ch to theo cng ngh MOS, CPU khng c kh nng cung cp dng iu khin tt c cc phn t ni vi bus. Cc chip lm b m dng cng ngh TTL c kh nng cung cp dng cho c cc thit b ni vi bus.
Ngoi ra cn l do khc l, khi c mt thit b no khc CPU mun tr thnh bus master (nh DMAC), CPU cn phi th ni cc bus. Phng php n gin nht c p dng l thit b phi pht tn hiu AEN (Address ENable) o tn hiu cho php a ra trn cc thanh ghi cht v transceiver, lm cho cc bus c th ni.
Tn hiu ALE (Address Latch Enable)
Tn hiu ALE c t mc tch cc khi CPU ang iu khin cc ng tn hiu a ch, cho php cc chip 74LS373 bit khi no cn cht a ch li. Tn hiu ny c bus cng cho b nh v cc chip I/O bit khi no cc tn hiu trn bus a ch l hp l.
Cc ng tn hiu , , ,
iu khin vic c/ ghi vo b nh hoc cc thit b vo/ra. Nh cc tn hiu ny, bus cung cp hai thng gian a ch ring bit, mt cho MEM v mt cho I/O. B nh s khng phn ng khi thy tn hiu , mc tch cc.
CPU s dng cc tn hiu - a vo chip iu khin bus 8288 to ra cc tn hiu , , , cng vi tn hiu ALE. Chip iu khin bus cng nhn tn hiu iu khin ANE t bus, tn hiu ny do mt thit b mun tr thnh bus master a ra, khi nhn c tn hiu ANE, chip iu khin bus s pht tn hiu iu khin cc chip cht a ch n chip bus transceiver th ni bus.
Tn hiu (I/O CHanel CHeck)
Tn hiu ny s tch cc khi c li chn /l b pht hin trn bus. Tn hiu ny s tc ng mmt ngt NMI.
Tn hiu IOCHRDY (I/O CHanel ReaDY)
Tn hiu ny do b nh a ra khi tc hot ng ca n thp, yu cu CPU cho thm mt s chu k i, bng cch chn wait states vo cc chu k c/ghi b nh.
Cc tn hiu IRQ2-IRQ7.
L cc tn hiu do cc thit b ngoi vi a ra, a n chip iu khin ngt 8259A. Khi c tn hiu gi n chip iu khin ngt, n s kim sot cc tn hiu ny v a ra mt tn hiu yu cu ngt ti CPU v t s hiu vect ngt ln ng d liu khi CPU cn n. IRQ0 thng c mch ng h v IRQ1 c bn phm s dng.
Cc tn hiu lin quan n DMA
Cc tn hiu cn li ni chung lin quan n hot ng DMA, chng hn khi CPU yu cu a c mt khi d liu, mch iu khin a s ch nhn c byte u tin t a a ra, sau pht ra mt yu cu tr thnh bus master ghi byte vo b nh.
Chip 8237A c INTEL thit k nhm qun l cc nghi thc bus v thc hin DMA trong c vic tang a ch b nh v gim con m sau khi truyn mi byte. Vic ny n thc hin thay cho cc thit b I/O, gip gim gi thnh ca chng.
V cn bn, chip 8237A l mt CPU nh, c cc chng trnh c ghi sn bn trong. Khi 8088 mun bt u hot ng DMA i vi mt thit b ngoi vi no , n np s hiu vo thit b, a ch nh, s byte, hng truyn v cc thng tin khc vo cc thanh ghi bn trong 8237A. Khi chip iu khin sn sng c hoc ghi byte u tin, n t mc tch cc ln mt trong cc ng DRQ ca bus a vo chip 8237A. Khi nhn c tn hiu, 8237A i chim bus v sn sng truyn mt byte. Chip 8237A pht tn hiu ti chip iu khin bo cho n bit hy ghi hoc c byte ca mnh (trong thao tc c hoc ghi tng ng). Trong khong mt chu k ny, chip 8237A iu khin hot ng ca bus nh mt bus master.
Chip 8237A c 4 knh c lp v c th qun l ng thi 4 ng truyn.
Tn hiu T/C (Terminal/Count)
ng T/C c chip 8237A t mc tch cc khi con m byte (byte count) bng 0, bo cho b iu khin I/O bit rng cng vic yu cu hon tt, n lc bo hiu cho 8258A gi ngt ti CPU.
V.2. Bus IBM PC/AT
Bus IBM PC/AT l bc pht trin tip theo ca th h bus IBM PC nhm pht huy c nhng kh nng hn hn ca b VXL 80286 so vi 8088 trc n. Vi bus a ch 24 dy, c kh nng nh a ch cho 224 = 16MB b nh v c bus d liu 16 bit.
Vi gii php m rng PC bus, b sung thm vo cc khe cm c mt on khe cm ngn, trn c 36 dy tn hiu, tng thm cho bus a ch 4 dy, bus d liu 8 dy, cc ng yu cu ngt, knh DMA, ... . Nh vy cc card m rng trc y vn dng cho IBM PC c th dng cho IBM PC/AT.
Ngoi vic m rng bus, tn s tn hiu ng h bus cng c tng t 4,77 MHz PC bus thnh 8MHz, nh tc truyn thng trn bus cng tng ln nhiu.
Nm 1991 t chc IEEE (Institute of Electrical and Electronic Engineers) a ra tiu chun quc t cho bus ca my AT, gi l bus ISA (Industrial Standard Architecture)
Cc nh sn xut PC khc a ra mt chun khc, l bus EISA (Extended ISA), v cn bn bus ny l s m rng bus PC/AT thnh 32 bit, gi nguyn tnh tng thch vi cc my tnh v cc card m rng c.
th h PS/2, th h sau ca IBM PC/AT mt bus hon ton mi c p dng, bus Micro chanel.
V.3. Bus PCI
Vo u nm 1992, Intel thnh lp nhm cng ngh mi. Nhm nghin cu ci thin cc c tnh k thut v nhng hn ch ca cc bus hin c nh: bus ISA, bus EISA.
PCI (Peripheral Component Interconnect, lin kt cc thnh phn ngoi vi). nh chun bus PCI c a ra vo thng 6 nm 1992 v c cp nht vo thng 4 nm 1993, thit k li bus PC truyn thng bng cch b sung thm mt bus khc vo gia CPU v bus I/O.
Bus PCI thng c gi l bus mezzanine v n b sung thm mt tng khc vo cu hnh bus truyn thng. PCI b qua bus I/O tiu chun, n s dng bus h thng tng tc ng h bus ln v khai thc ht li th ca ng dn d liu ca CPU.
Thng tin c truyn qua bus PCI 33MHz v rng d liu y ca CPU. Khi bus y c s dng ni vi CPU 32 bit, di thng l 132 MBit/s, c tnh theo cng thc: 33MHz*32bit/8 = 132MBit/s. Khi bus y c s dng vi nhng h thng b sung 64 bit, di thng tng gp i, ngha l tc truyn d liu t ti 264MBs. L do chng m bus PCI tng tc nhanh hn cc bus khc l n c th hot ng ng thi vi bus vi x l. CPU c th c x l d liu trong cc cache ngoi tr, trong khi bus PCI phi truyn thng tin lin tc gia cc thnh phn khc ca h thng, y l u im thit k chnh ca bus PCI.
nh chun PCI c ba cu hnh, mi cu hnh c thit k cho mt kiu h thng ring bit vi nhng quy nh ngun ring. nh chun 5V cho nhng h thng my tnh vn phng, nh chun 3,3V cho cc h thng my tnh xch tay v nhng nh chun chung cho nhng bo m v cc cc hot ng trong hai kiu y.
V.4. Bus ni tip chung USB
Bus USB (Universal Serial Bus) l mt cng ngh bus mi y trin vng, nhanh chng ph bin trong nhng th my tnh ngy nay. Ch yu USB l cp cho php ni ln ti 127 thit b bng cch s dng chui xch. Tuy nhin n truyn d liu khng nhanh bng FireWire, tc 12MBs n c kh nng p ng cho hu ht cc thit b ngoi vi. nh chun USB c a ra vo nm 1996 do mt hi ng gm nhng i din ca cc nh sn xut my tnh ln nh Compaq, Digital, IBM, NEC v Northen Telecom.
Mt u im ni bt ca USB l nhng thit b ngoi vi t nhn dng, mt c trng ht sc thun li cho vic ci t, xc lp cc thit b ngoi vi. c trng ny hon ton tng thch vi nhng cng ngh PnP v cung cp tiu chun cng ngh cho kt ni tng lai. Hn na, nhng thit b USB c kh nng cm nng.
CHNG VI. KIN TRC B NH MY VI TNH
I. Cc khi nim chung
Mt trong cc hot ng c bn ca my tnh l lu tr d liu dng nh phn. Cc d liu ny l cc chng trnh hoc s liu m Vi x l a ra hoc c vo tu theo yu cu. B nh l cc thit b thc hin nhim v lu tr d liu ca my vi tnh.
Mi nh c xc nh bi mt a ch. Thng thng mi nh c dung lng l 1 byte. Cc byte c ghp thnh t. Nhng my 16 bit s liu th t chc 2 byte/t, cn cc my 32 bit s liu th di t gp i (4 byte/t).
I.1. Trt t cc byte trong t.
C th l t phi sang tri (vi x l h Intel) hoc ngc li t tri sang phi (vi x l h Motorola). Trng hp d liu lu gi l s nguyn th hai cch sp xp trn khng c tr ngi g. Nhng khi d liu bao gm c s nguyn v c xu k t ... th c vn .
V d, xt mt bn ghi (h 7.1) gm c xu l tn nhn vin BILL GATE v trng l s nguyn: tui 42. Xu kt thc bng cc byte 0 cui in kn ch trng ca t, cn s nguyn th c thm vo cc byte phn c trng s cao hn. Do vy nu dch cch sp xp n sang cch kia ca xu ging nh ca s nguyn th s b nhm.
I.2. M pht hin li v sa sai.
S cc v tr bit khc nhau trong hai t gi l khong cch Hamming. V d, trong hai t:
10001001 v 10110001 c khong cch Hammming bng 3.
sa sai, bn cnh m s bit s liu ca t, ngi ta thm vo r bit d (redundant bits) v chiu di tng ca t l n : n = m + r
pht hin d bit li n, cn dng m c khong cch d+1. Tng t, sa li d bit n, cn dng m c khong cch 2d+1. V d, dng m bit parity thm vo byte s liu, m ny c khong cch bng 2, dng pht hin 1 bit sai, nhng khng sa c li.
Trong truyn 1 khi k t, mi k t c mt bit parity kim tra. cui mi khi, ta truyn thm mt k t l parity ca ton th bn tin, gi l longitudinal check (LRC). Pha thu s tnh LRC v so vi LRC nhn c kim tra li. Mt phng php na kim tra li khi truyn s liu l dng CRC (Cyclic redundance check), l mt a thc nh phn d thu c khi chia a thc cc bit ca bn tin cho mt a thc quy nh.
V d m sa sai l m c 4 t di 10 bit nh sau:
0000000000,0000011111,1111100000,1111111111. M ny c khong cch l 5, tc l n c th sa c cc li kp. V d nu ta nhn c t 0000000111, my thu s bit rng t phi l 0000011111 (nu coi nh khng c nhiu hn mt li kp). Nhng nu mt li ba xy ra, bin 0000000000 thnh 0000000111 th ta khng sa li c.
sa li, ngi ta dng thut ton ca Hamming.
I.3. Kin trc tng th ca b nh. (h 7.2)
Xt mt cch tng th, b nh ca my tnh c kin trc theo cung bc (hierarchy) tri di t b nh ngoi n b nh trong v cui cng l n b nh m (cache) trong v ngoi CPU.
Hnh 7.2. Hieratchy ca b nh trong my vi tnh.
I.4. Qun l b nh (MMU, Memory Management Unit)
Cng vic qun l b nh ca my vi tnh ch yu l do b vi x l m nhim. Dn cnh cn c DMAC (Direct Memory Acess Controller) cng tham gia qun l b nh trong vic truyn s liu gia controller a vi b nh v lm ti b nh. nhng my c Cache Memory th Cache Memory Controller thc hin cc cng vic truyn s liu gia Cache Memory v RAM.
khu vc trung tm ca my vi tnh (b vi x l, ROM, RAM, cc bus...), thc cht ca vic qun l b nh l cc thanh ghi ca vi x l a ra cc a ch ca nh hoc ca cng I/O qua bus a ch, cng cc lnh iu khin/ trng thi khc v c vo/ vit ra cc s liu ca cc nh y. Cc b phn bn ngoi VXL s gii m cc a ch v cc tn hiu iu khin/ trng thi tr vo cc byte/ t/ t kp... ca b nh thc hin cc thao tc tng ng.
Cn t cc a tr i, vic qun l b nh l thc hin cc lnh co hn iu hnh ln cc file (c a ch 3 chiu l C-H-S), c th l truyn s liu nh DMAC gia vng m (buffer) ca b iu khin a vi b nh RAM.
Cc b vi x l Intel t th h 286 tr i phn bit hai mode a ch: mode a ch thc (ch qun l 20 bit a ch vt l ca b nh) v mode a ch bo v (qun l ti 32 bit a ch o nh cc thanh ghi n trong b vi x l).
cp di, tc cp ngoi vi, nh b iu khin a, b iu khin mn hnh, my in... cng c t chc b nh ring ca chng tin cho vic ct gi v x l vi cc c th ring.
Cc b nh RAM-ROM v cc vng nh ca b nh ngoi (trn cc a), khc nhau v cch m ho cc bit, cch t chc, do c cch truy nhp cng khc nhau.
II. T chc b nh ca vi x l.
B nh ca vi x l c th xem nh bao gm c b nh ROM v b nh RAM. B nh RAM ca vi x l chnh l cc thanh ghi (thanh ghi chung, thanh ghi ch s, thanh ghi on, thanh ghi ngn xp, thanh ghi trng thi, thanh ghi c, cc b m s liu/ a ch/ iu khin...). Cn b nh RAM l b phn gii m lnh pht ra cc vi lnh.
Nhm mc ch qun l c s lng a ch nh (o) nhiu hn s ng a ch ca b vi x l v bo v cc vng nh ca cc nhim v khc nhau (task) v ca ht nhn (kernal) chng truy nhp khng hp php, cc vi x l c cc cch t chc c bit cc thanh ghi a ch (b phn phn trang, iu khin on ca cc nhim v).
Cc b vi x l t th h 486 tr i cn c mt b nh Cache Memory vi kch thc nhiu Kbyte cha mng cc lnh v s liu ang thng dng ly t b nh RAM, nhm tng tc truy nhp.
tng tc tnh ton cc php ton du chm ng, trong cc b vi x l t 486 tr i cn c b phn du chm ng (FPU, Floating Point Unit), b phn ny cng c cc thanh ghi FPU phc v ring cho n.
III. T chc b nh trong ca my vi tnh
B nh trong ca my tnh dng cha chng trnh v s liu ca phn chng trnh ht nhn v cc nhim v. Mi byte c gn cho mt a ch v l v DMAC c th truy nhp ti.
B nh RAM nhng my t 386 tr i c th c tch ring ra b nh m (cache memory), l RAM tnh vi thi gian truy nhp nhanh, c kch thc di 1Mb c ni ngay vo bus ni b ca my tnh st ngay vi x l v c iu khin bi Cache controller. Phn cn li l DRAM, chm hn nhng r hn v c dung lng ln hn. Hnh 7.3 th hin s khi bn trong mt my 386.
Local CPU Bus ; System control/ status bus
System address bus; System data bus; Peripheral bus.
Hnh 7.3. Phn trung tm my tnh AT 386
Trong s : Vi x l l 80386, ng x l ton l 80387, cache controller 82385 c ni trc tip vi nhau thnh mt bus local. Cc ng a ch A2-A31 ca 386 ni trc tip ti cc ng cng tn ca 82385DX, cc ng s liu D0-D31 ca 386 c ni trc tip ti cc ng s liu cng tn ca 387DX. Hn na, cc chn quy nh chu k bus D/C#, W/R# v M/IO# c ni trc tip ti cc chn tng ng ca 82385DX.
T bus local ca VXL, cc ng a ch c m ra bng cc cht a ch 8 bit 74373 (khng v trong hnh). Cc ng s liu ca bus local c m hai chiu bng Data Buffer 82345.
System Controller 82346 l tri tim ca cc chipset 340. N ni ti bus local ca 386, bus m rng ISA, Data buffer 345, ISA Controller 344. N thc hin mt s chc nng sau:
- Nhn xung ng h t bn ngoi pht nhp clock TURBO v clock chm hn.
- Lm trng ti bus (cc vic v DMA v lm ti b nh)
- Pht cc tn hiu a ch hng RAS v a ch ct CAS n cc dy nh ca ton b b nh DRAM trn MainBoard, pht tn hiu ghi vo RAM
- Pht tn hiu ready, tn hiu Reset CPU
- Giao tip gia ng x l vi CPU.
Controller ISA 82344 ni gia bus local ca CPU vi bus h thng lm cc chc nng giao tip vi CPU, system controller 346, data buffer 345, ROM, bus, cc thit b ngoi vi nh sau:
- Nhn cc tn hiu BE0# - BE3# ca CPU, ROM8# v IOCHRDY t bus ISA sinh ra cc tn hiu chn byte chn v byte l SA0# v SBHE#
- To cc tn hiu giao tip gia 344, 345 v 346.
- Cha khi iu khin ngoi vi Peripheral Control gm cc vi mch c tch hp cc cao (VLSI) quen thuc: hai 82C59 (ngt), hai chip 82C37A (DMAC), vi mch nh thi 82C54, thanh ghi a ch trang 74LS612, b driver cho loa, port B parallel I/O, ng h thi gian thc v b m lm ti b nh.
- Gii m a ch to ra cc tn hiu chn chip CS8042# cho controller bn phm 8042 v ROMCS# cho php chn ROM BIOS.
Vi mch Peripheral Combo 82341 c ghp vo bus m rng ca bus ISA, n cha cc VLSI thc hin mt s chc nng ca cc thit b ngoi vi sau y:
- Hai cng ni tip khng ng b 16C450
- Mt cng song song cho my in
- ng h thi gian thc
- RAM s tay, cc controller cho bn phm v chut.
- Interface cho a cng (tiu chun IDE).
Controller a mm 82077 c th iu khin ti 4 a mm cc loi 51/2 v 31/2.
III.2. T chc b nh RAM ca my tnh.
Xt trng hp my 386, n c 32 bit a ch, t 00000000H n FFFFFFFFH, ng vi 4 GByte khng gian nh vt l. V quan im phn cng, ta chia khng gian thnh 4 dy nh c lp nhau, l bank0 - bank3, mi bank kch thc 1 GByte. Chng cn cc tn hiu Bank Enable BE0# ti BE3#. Trong hnh 7.4 sau, ta thy cc a ch A2 - A31 c t song song vo tt c 4 bank nh. Cn mi bank nh ch cung cp 1 byte s liu cho 32 ng s liu.
ch thc, 386 ch dng cc ng a ch A2 - A19 v 4 tn hiu BE# dng chn bank nh. Mi bank ch c 256 KByte.
T hnh 7.4 ta thy khng gian nh vt l c t chc thnh dy cc t kp (32bit). Do mmi t kp xp ng hng (aligned) bt u a ch bi s ca 4.
Dng t hp cc tn hiu BE# c th truy nhp c vo cc fmat khc nhau (byte, t, t kp) nh hnh 7.5. Vic truy nhp vo a ch u ca t kp c th cn 1 chu k bus (khi t kp xp ng hng) hoc 2 chu k bus (khi t kp xp lch hng, misaligned).
II.3. Interface gia VXL v b nh (h 7.7).
S giao tip gia vi x l 386 vi b nh ch bo v c v trn hnh 7.6. Ta thy rng giao tip bao gm cc vic:
- Gii m cc trng thi ca vi x l (ADS#, M/IO#, D/C#, W/R#) cp ra cc tn hiu iu khin bus (ALE#, MWTC#, MRDC#, OE# cho b nh, DT/R# v DEN#).
- Gii m 3 a ch cao nht (A29-A31) c c 8 tn hiu chn chip CE0# - CE7#, cho trng hp mi chip 1 bit, ri cht cc a ch A2-A28 v CE0# - CE7# a sang b nh.
- m truyn s liu hai chiu gia VXL v b nh c iu khin bi cc tn hiu cho php a ra s liu EN# v nh hng truyn DIR.
- T cc tn hiu BE0# - BE3# v MWTC# cp iu khin vit ln cc bank nh WEB0# - WEB3#.
- B nh cp cc tn hiu NA#, BS# v READY# cho VXL.
III.4. Gii m a ch v Latch a ch, m hai chiu s liu.
B gii m a ch c th t trc hoc sau b cht (h 7.7a,b). Sau b cht a ch c khi cn m ring cho a ch I/O. V d dng 4F244 c th sink c 64 mA (h 7.7c).
gii m a ch ngi ta dng mch 74F138 vi 8 ng ra (hoc 74F139 hai mch gii m, mi mch c 4 ng ra). Trn hnh 7.8 ta thy 2 a ch cao nht dng gii m ra 4 tn hiu chn chip CE0# - CE3#. Latch ta dng cc vi mch 74F373 (c th sink c 24 mA max). Chn ra 3 trng thi OC# ni t, cn chn CLK ca 373 c cp ALE# lc cn Latch a ch ra. Chn ra 3 trng thi OC# ni t, cn chn CLK ca 373 c cp ALE# lc cn latch a ch ra.
m v truyn s liu hai chiu (hnh 7.9) cho bus s liu ca VXL (dng max 4mA) ta dng cc m 8 bit hai chiu 74F245 vi dng sink max l 64mA. Ta cng dng vi mch 74F646 l cc m 2 chiu vi thanh ghi, n c th dng nh mt b m n gin hoc dng vi chc nng m - thanh ghi trong s liu truyn t bus ny vo mt thanh ghi bn trong vi mt dy tn hiu iu khin, v t thanh ghi trong ra bus kia vi tn hiu iu khin khc.
II.5. Gii m trng thi bus VXL
VXL 386 cp trc tip ra ba tn hiu quy nh kiuy ca chu k nh hin hnh ca bus l: Mem/IO#, Data/Control# v Write/Read#.
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