CBP 2002 Repository 1
Overview PC Structure 1
CBP 2002 Repository 2
CBP 2002 Repository 3
CPU
CachesSystem Bus
Memory
I/O controllers
bridges
Disk, MouseDisplaysKeyboards
Ethernet
I/O Buses
CBP 2002 Repository 4
caclulator
CBP 2002 Repository 5
Stonehenge
CBP 2002 Repository 6
CBP 2002 Repository 7
Sam 4 Series Master
Data Memory
Code Memory
ALU
r1
r2
r0X
Y
W
X Y
W
0
1
7mar
mdr
CBP 2002 Repository 8
Sam 4 Series Master
Data Memory
Code Memory
ALU
r1
r2
r0X
Y
W
X Y
W
0
1
7mar
mdr
CBP 2002 Repository 9
Sam 4 Bits
Data Memory
Code Memory
ALU
r1
r2
r0X
Y
W
X Y
W
0
1
7mar
mdr
CBP 2002 Repository 10
Computer Clipart
CBP 2002 Repository 11
Sam 4 outline
CBP 2002 Repository 12
• Memory• CPU Arithmetic Logic Unit (ALU)• CPU Control Unit• Input• Output
CBP 2002 Repository 13
Data Memory
0
1
7
mar
mdr
X
Y
W
Y
W
r1
r2
r0
X
PC
Code Memory
Sam4 Bits X
Y
W
Y
W
r1
r2
r0
X
0
1
7
mar
mdr
CBP 2002 Repository 14
Data Memory
0
1
7
mar
mdr
X
Y
W
Y
W
r1
r2
r0
X
PC
Code Memory
Sam4 Bits X
Y
W
Y
W
r1
r2
r0
X
0
1
7
mar
mdr
CBP 2002 Repository 15
Memory Cells
CBP 2002 Repository 16
Mem reg and inst for Sam
7
696
2315
1154
1453
2
1
0
231r3
unusedrtrsrdldr
opcodedestination
Source regs
CBP 2002 Repository 17
Spreadsheet Bits
CBP 2002 Repository 18
Timing diag bits 1
T1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU Op Mem Access Reg Write
CBP 2002 Repository 19
Timing Diag WorksheetT1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU Op Mem Access Reg Write
CBP 2002 Repository 20
Timing diag bits 1
T1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU OpMem Access
Reg Write
T1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU OpMem Access
Reg Write
T1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU OpMem Access
Reg Write
T1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU OpMem Access
Reg Write
CBP 2002 Repository 21
Reg and ALU Bits (nonsam)
Memory
Register
ALU
r0
r1
r2
r3
r11
r0
r0
r0
r0
r0
r0
r0
ALU
CBP 2002 Repository 22
More Reg ALU Bits (nonsam)
..
..
0
8
16
24
32
..
..
CBP 2002 Repository 23
MEM
CPU
DISK
IO
IO
MEM
CPU DISKIO
IO
CBP 2002 Repository 24
Turing Machine Bits
S0
R
… …
CBP 2002 Repository 25
Logic gates
CBP 2002 Repository 26
Buses
Correctly Sized Components !
CBP 2002 Repository 27
Buses
Correctly Sized Components !
CBP 2002 Repository 28
This Time
AL
UMem Reg Mem Reg
AL
UMem Reg Mem Reg
CBP 2002 Repository 29
This Time
AL
UMem Reg Mem Reg
CBP 2002 Repository 30
coffee
CBP 2002 Repository 31
CBP 2002 Repository 32
Pipeline template
CBP 2002 Repository 33
Pipeline template
CBP 2002 Repository 34
Pipeline template
CBP 2002 Repository 35
CBP 2002 Repository 36
CBP 2002 Repository 37
Pipeline template
CBP 2002 Repository 38
Performance incl. Stalls5 cycles gives 5 loads so we have 1 cycle per load (CPL = 1)
Speedup = 5. This is of course just the pipeline depth. (Assuming there are no stalls).
CBP 2002 Repository 39
Increasing Shirt Throughput
idle
idle running
running idlerunning
running running
A. Wash then Dry B. Wash then Dry and Reload Wash
time
time
CBP 2002 Repository 40
blank
CBP 2002 Repository 41
T1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU Op Mem Access Reg Write
CBP 2002 Repository 42
T1 T2 T3 T4 T5
Fetch Decode, Reg Op ALU Op Mem Access Reg Write
CBP 2002 Repository 43
T1 T2 T3 T4 T5
Fetch Decode, Reg Op
ALU OpMem Access
Reg Write