direct conversion receivers

AgendaWireless communication architecturesDual IF Superheterodyne, Low IF SamplingSingle IF Superheterodyne, High IF SamplingDirect (Zero-IF) ConversionHomodyne receiver challengesDC offsetQuadrature errorsEven order distortionsOrigins of DC offsetLO feed throughCommon mode mismatch Theory behind quadrature errorsAmplitude and phase mismatch Consequences of DC and Quadrature errorEVMOccupy available bandwidthImplementation of DC and quadrature correctionResultsSummary

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Receive Architectures Dual IF Superheterodyne, Low IF Sampling

*Cos(LO-IF)Cos(LO)=Cos(2LO-IF)+Cos(IF)

Cos(LO+IF)Cos(LO)=Cos(2LO+IF)+Cos(IF)

IF

DesiredChannel

Image

LO

ImageRejectFilter

IF

IF

LO

IF

DesiredChannel

Image

IF

Out-of-band Interferers

Receive Band

DesiredChannel

In-band Interferers

Band SelectFilter

Receive Band

IF

0

0

TuningControl

RF front-end harmonics

Anti-aliasfilter

fADC/2

0

ADC Input

ADC Output

Wideband Fundamental

HD2

HD3 +aliased HD3

fADC/2

0

0

ChannelSelectFilter

IF

ChannelSelectFilter

Receive Architectures Dual IF Superheterodyne, Low IF Sampling

Large RF/IF contentRF front endFixed final LO frequency and mixer, reconfigurable first LO frequency and maybe mixerFinal IF amplifier HD2/HD3 may require sharper anti-alias filterDistributed RF gain eases per block noise/gain/IP trade-offTypically used for multi-band single carrier designsIF ranges to 15MHz*

*Receive Architectures Single IF Superheterodyne, High IF SamplingCos(LO-IF)Cos(LO)=Cos(2LO-IF)+Cos(IF)

Cos(LO+IF)Cos(LO)=Cos(2LO+IF)+Cos(IF)

IF

DesiredChannel

Image

LO

ImageRejectFilter

IF

IF

LO

IF

DesiredChannel

Image

IF

Out-of-band Interferers

Receive Band

DesiredChannel

In-band Interferers

Band SelectFilter

Receive Band

IF

TuningControl

IF

ChannelSelectFilter

IF

Anti-aliasfilter

fADC

fADC/2

0

ADC Input

3*fADC/2

2*fADC

5*fADC/2

RF front-end HD2

Relaxed transitionband

fADC

fADC/2

0

ADC Output

3*fADC/2

2*fADC

5*fADC/2

Undersample in-phasefrom 3rd nyquist zone

Receive Architectures Single IF Superheterodyne, High IF Sampling

Cuts out one mixer stagePuts the final mixer requirements on the ADCLast IF mix done in digital domain (digital complex down mix)RF front endBand reconfigurable first LO frequency and maybe mixerFinal IF amplifier HD2 usually of no concernReduced RF gain distribution requires higher performing RF/IFADC needs good IF performance (nyquist or under-sample)IF ranges from 100-300MHz*

*Receive Architectures Direct (Zero-IF) ConversionCos(RF) Cos(RF)=1+Sin2(RF)Cos(SIG) Cos(SIG)=1+Sin2(SIG)LNA(t)=1x(t)+2x2(t)input(t)=A1Cos(1t)+A2Cos(2t)feedthrough(t)=2A1A2Cos(2-1)tPhase andGain ErrorPhase andGain Error

TuningControl

RF

*Conceptually

0

TuningControl

RF

Receive Band

Band SelectFilter

RF

2

1

0

2

1

2-1

Feedthrough

2-1

0

0

+RF

-RF

0

Anti-aliasfilter

Complex

fADC/2

0

-fADC/2

LO feedthrough

Unsupressed Quadrature Image

ADC Output

Homodyne Receiver Advantages and ChallengesAdvantages:Low component count leads to lower system costNo image reject filter neededFiltering requirements more relaxed at basebandGain stages at baseband provide power savings

Challenges:DC offset appearing at basebandSelf mixingOffset voltages Images appearing symmetrically about zero frequencyI/Q mismatches in phase and amplitudeEven order nonlinearitiesTwo high frequency interferers close to the channel of interest can result in even order non-linearities that fall within the band of interest.

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*The Imperfect I/Q Demodulator

Imperfections in the I/Q Signal Path*Offsets within the dual channel ADCPCB and Layout mismatchesComponent mismatches

Back to Basics : Eulers FormulasSin 0t is 90 out of phase with respect to cos 0t With perfect amplitude and phase matching the signal content at - 0 cancels*

Amplitude and Phase MismatchAmplitude Mismatch

Phase Mismatch

*Desired SignalImage

*Critical IQ Demodulator Specs LO to RF LeakageIf some of the LO leaks to the RF input, it mixes (multiplies) with itself in the mixer generating unwanted dc offsets on top of the recovered baseband data streamADCLNADesired-70dBm0dBmLeakage-60dBm-40dBm-30dBm(~20mVp-p)ABCAssume, Gain from A to C =30dBLO to RF leakage ~ 60dBFLOFLOX

Effects of Gain, Offset, and Phase Errors *

*What is causing the poor quality of this demodulated Constellation?Very poor LO Quadrature Phase Split (in DMOD)DC Offset of the complete constellation (probably LO to RF Leakage) Noise has enlarged the footprint of the constellation points (poor Receiver Noise Figure)SymbolDecisionThresholdIf the symbol landson the edge or outsideof the box, bit errors will occur

Effects of I/Q Mismatch*Gain Error** EVM Degradation **** Images Occupy BW **** Interfere with Desired Signal **

DC Offset and Quadrature Error CorrectionDC offset and quadrature error correction implemented digitally at the end of the receive chainMost efficient approach in order to compensate for all potential mismatches or errors in the signal pathDC CorrectionIf DC free coding is used, a notch filter can be applied Quadrature Error CorrectionGain CorrectionCalculate I^2 Q^2 to determine the power difference between I and Q.The power difference should be driven to zero.Phase CorrectionPerform a cross-multiply between I and Q.Can be viewed as a Mixer. The DC term is proportional to the phase difference between I and Q.By definition this should be zero if they are perfectly orthogonal.*

*AD9262: Direct Conversion RX Signal ChainDiscrete signal chain targeting Multi-Carrier base stations.WCDMA, CDMA2000, TDSCDMA, WiMax, LTEADL5523: 400 MHz to 4 GHz Low Noise AmplifierADL5382: 700 MHz to 4 GHz Quadrature DemodulatorAD9262: 16-bit Dual Continuous Time Sigma-delta ADCIntegrated DC and Quadrature Error Correction

*AD9269: Direct Conversion RX Signal ChainDiscrete signal chain targeting Multi-Carrier base stations.WCDMA, CDMA2000, TDSCDMA, WiMax, LTEADL5523: 400 MHz to 4 GHz Low Noise AmplifierADL5382: 700 MHz to 4 GHz Quadrature DemodulatorAD9269: 16-bit Dual Pipeline ADCIntegrated DC and Quadrature Error Correction

CW Single ToneQEC DisabledDC Power: -46.4 dBImage Rejection: 58.5 dBQEC EnabledDC Power: -100 dBImage Rejection: 112 dB

WCDMA Carrier with GSM BlockerQEC DisabledDC Power: -46.8 dBImage Rejection: 60.8 dBQEC EnabledDC Power: Image Rejection: 99.2 dBGSM blocker 10 MHz away from WCDMA carrierAt the antenna, blocker power: -25 dBm and WCDMA carrier: -50 dBm

WCDMA Carrier with Modulated BlockerQEC DisabledDC Power: -46.9 dBImage Rejection: 56.7 dBQEC EnabledDC Power: -105 dB Image Rejection: 63.2 dBBlocker 10 MHz away from WCDMA carrierAt the antenna, blocker power: -40 dBm and WCDMA carrier: -60 dBm

SummaryDirect conversion or homodyne receivers have there own merits and challenges.Gain, phase, and offset errors are a few of the challenges that can be addressed with quadrature error correction algorithmsGain, phase, and offset errors cause degradations in receiver EVM and sensitivityQuadrature error correction will improve EVM and sensitivityDirect conversion offers advantages in power, cost and performance over IF sampling architecturesQuadrature error correction enables realizable direct conversion solutions for macro level basestationsAnalog Devices first generation of QEC is available integrated into the following productsAD9262 dual 16b continuous time sigma delta ADCAD9269 dual 16b pipeline ADC

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AD9262 16-Bit, 2.5/5/10MHz, 30-160MSPSDual Continuous Time Sigma Delta ADCKEY FEATURESSNR: 84.5 dBFS to 10 MHz inputSFDR: 87 dBc to 10 MHz inputNoise Figure: 15dBPower: 675 mWSample rate converter: 30-160 MSPSSelectable bandwidth:5/10/20MHz complexPassive input networkNo ADC driver amplifier Alias immuneNo Anti-Alias Filter Integrated Funtions:Decimation filter and Sample Rate Conv.Quadrature Error and DC offset correctionPLL clock multiplierLow drift voltage reference Serial Control Interface 1.8 V Analog supply

Temp Package-40C +85C 9 x 9 mm LFCSP Pb-Free

SamplingFinal ReleaseNowJanuary 2010

*AD9269 : 16-Bit, 20/40/65/80 MSPS 1.8V DUAL ADC

KEY BENEFITSTotal Power Dissipation = 125 mW / ch @80Msps Outstanding PerformanceSNR = 77 dBFs @ fIN = 40 MHz @ 80 MSPSENOB of 12.4 @ fIN = 40 MHz @ 80 MSPS SFDR = 88 dBFs @ fIN = 40 MHz @ 80 MSPSExcellent LinearityDNL = 0.7 LSB (Typical)INL = 5.5 LSB (Typical) 1.8V or 3.3V CMOS outputs 650 MHz Full Power Analog Bandwidth 1Vp-p to 2Vp-p Input Voltage Range Data Clock Output Provided User Controls via Serial port interfaceOutput Data Format and Muxd OptionsClock Duty Cycle StabilizerOutput Test patternsAnalog input range adjustmentPower down modesQuadrature Error Correction16-bit and 14-bit Pin Compatible familyAD9268-125 (16-bit), AD9258-125 (14-bit)AD9251 (14-bit), AD9231 (12-Bit), AD9204 (10-bit)

Key BenefitLower Power per channelSmall FootprintOutstanding dynamic performance

Temp Package-40C +85C64-pin LFCSP (9x9mm)Pb-Free

SamplingProduction QtysNowOct09

**Receiver architectures fall into two broad categories: heterodyne and homodyne receivers.