Digital SignalProcessing for

MultimediaSystems

edited by

Keshab K. ParhiUniversity of MinnesotaMinneapolis, Minnesota

Takao NishitaniNEC Corporation

Sagamihara, Japan

M A R C E L

MARCEL DEKKER, INC. N E W YORK • BASEL

Contents

Series Introduction by K. J. Ray Liu iii

Preface v

Part I System Applications

1. Multimedia Signal Processing Systems 1Takao Nishitani

1.1 Introduction 11.2 Digitization of Audio and Video 41.3 Multimedia Services 101.4 Hardware Implementation 12

References 16

2. Video Compression 17Keshab K. Parhi

2.1 Introduction 172.2 Entropy Coding Techniques 182.3 Transform Coding Techniques 222.4 Motion Estimation/Compensation 312.5 MPEG-2 Digital Video Coding Standard 332.6 Computation Demands in Video Processing 382.7 Conclusions 40

References 40

3. Audio Compression 43Akihiko Sugiyama and Masahiro Iwadare

3.1 Standardization Activities of HiFi Audio Coding 433.2 MPEG Audio Algorithm Structure 443.3 MPEG-1 Audio Algorithm Structure 513.4 MPEG-2 Audio Algorithm Structure 603.5 Future Work 64

4. System Synchronization 67Hidenobu Harasaki

4.1 Introduction 674.2 System Clock Synchronization Overview 684.3 Clock Transmission Methods 714.4 Multiplexing and Demultiplexing 724.5 MPEG-2 System 754.6 Network Adaption 77

ix

x CONTENTS

4.7 ATM Adaption for Low Bitrate Speech 794.8 Multipoint Communication 794.9 Resilience for Bit Error and Cell/Packet Losses 80

4.10 Future Work 81References 81

5. Digital Versatile Disk 83Shin-ichi Tanaka, Kazuhiro Tsuga, and Masayuki Kozuka

5.1 Introduction 835.2 Physical Format 845.3 File System Layer 935.4 Application Layer 94

References 108

6. High-Speed Data Transmission over Twisted Pair Channels 109Naresh R. Shanbhag

6.1 Introduction 1096.2 Preliminaries 1106.3 The Channel 1136.4 The Carrierless Amplitude/Phase (CAP) Modulation Scheme 1166.5 The Hilbert Transform Based FSLE Architecture 1226.6 Strength Reduced Adaptive Filter 1276.7 Design Examples 1316.8 Conclusions 135

7. Cable Modems 139Alan Gatherer

7.1 Introduction 1397.2 Cable System Topologies for Analog Video Distribution 1407.3 An Overview of a Cable Modem System 1457.4 Channel Model 1527.5 Downstream PHY 1597.6 Upstream PHY 1687.7 Acknowledgements 171

References 171

177

177178180190194198214217220221222

8.

8.18.28.38.48.58.68.78.88.9

8.10

Wireless Communication SystemsElvino S. SousaIntroductionAmpsDigital Wireless SystemsIS-54/136GSMCDMAPower ControlHand-off ProcessesMultimedia ServicesConclusionsReferences

CONTENTS ' xi

Part II Programmable and Custom Architectures and Algorithms

9. Programmable DSPs 225Wanda K. Gass and David H. Bartley

9.1 Introduction 2259.2 History of Programmable DSPs 2259.3 Architecture Overview 2269.4 Hard Real-Time Processing 2289.5 Low Cost 2299.6 Minimum Code Size 2389.7 Low Power Dissipation 2409.8 Specialization 2419.9 Summary 241

References 242

10. RISC, Video and Media DSPs 245Ichiro Kuroda

10.1 Introduction 24510.2 Media MPU 24710.3 Video DSP and Media Processors 26010.4 Comparison of Architectures 26610.5 Conclusions 269

11. Wireless Digital Signal Processors 273Ingrid Verbauwhede and Mihran Touriguian

11.1 Introduction 27311.2 Digital Wireless Communications 27311.3 Wireless Digital Signal Processors 28411.4 A Domain Specific DSP Core: Lode 28811.5 Conclusions 296

References 297

12. Motion Estimation System Design 299Yasushi Ooi

12.1 Introduction 29912.2 Block-Matching Motion Estimation 30112.3 Motion Vector Search Algorithms 30412.4 Circuit Architectures for Motion Vector Search 30912.5 Video Encoder LSI Implementations 31712.6 Motion Estimation—Other Techniques 32312.7 Concluding Remarks 325

References 325

13. Wavelet VLSI Architectures 329Tracy C. Denk and Keshab K. Parhi

13.1 Introduction 32913.2 Introduction to Wavelet Transforms 32913.3 The One-Dimensional DWT 33313.4 Architectures for 2-D DWT 348

xii CONTENTS

13.5 Summary 349References 351

14. DCT Architectures 355Ching Yu-Hung

14.1 Introduction 35514.2 DCT Algorithms 35614.3 DCT Architectures 36514.4 Conclusion and Future Trends 376

References 378

15. Lossless Coders 385Ming-Ting Sun, Sachin G. Deshpande, and Jenq-Neng Hwang

15.1 Introduction 38515.2 Huffman-Based Lossless Coding 38615.3 Implementation of Huffman-Based Encoders and Decoders 38915.4 Arithmetic Coding 39415.5 Implementation of Arithmetic Coders 39815.6 Systems Issues 41215.7 Summary 413

References 413

16. Viterbi Decoders: High Performance Algorithmsand Architectures 417Herbert Dawid, Olaf Joeressen and Heinrich Meyr

16.1 Introduction 41716.2 The Viterbi Algorithm 41916.3 The Transition Metric Unit 42816.4 The Add-Compare-Select Unit 43216.5 Synchronization of Coded Streams 44916.6 Recent Developments 452

References 453

17. A Review of Watermarking Principles and Practices 461Ingemar J. Cox, Matt L. Miller, Jean-Paul M. G. Linnartz,and Ton Kalker

17.1 Introduction 46117.2 Framework 46317.3 Properties of Watermarks 46517.4 Example of a Watermarking Method 47117.5 Robustness to Signal Transformations 47217.6 Tamper Resistance 48217.7 Summary 482

References 482

18. Systolic RLS Adaptive Filtering 487K. J. Ray Liu and An- Yeu Wu

18.1 Introduction 48718.2 Square Root and Division Free Givens Rotation Algorithm 489

CONTENTS xiii

18.3 Square Root and Division Free RLS Algorithms andArchitectures 491

18.4 Square Root and Division Free CRLS Algorithmsand Architectures 497

18.5 Split RLS Algorithm and Architecture 50318.6 Performance Analysis and Simulations of Split RLS 50718.7 Split RLS with Orthogonal Preprocessing 51218.8 Conclusions 514

References 517

Part III Advanced Arithmetic Architectures and DesignMethodologies

19. Pipelined RLS FOR VLSI: STAR-RLS Filters 519K. J. Raghunath and Keshab K. Parhi

19.1 Introduction 51919.2 The QRD-RLS Algorithm 52019.3 Pipelining Problem in QRD-RLS 52219.4 Pipelining for Low-Power Designs 52419.5 Star-RLS Systolic Array Algorithm 52519.6 Pipelined Star-RLS (PSTAR-RLS) Architecture 52919.7 Numerical Stability Analysis 53519.8 Finite-Precision Analysis 53619.9 A 100 Mhz Pipelined RLS Adaptive Filter 541

19.10 Conclusions 544References 544

20. Division and Square Root 551Hosahalli R. Srinivas and Keshab K. Parhi

20.1 Introduction 55120.2 Division 55220.3 Square Root 57120.4 Unified Division Square Root Algorithm 57820.5 Comparison 581

References 585

21. Finite Field Arithmetic Architecture 589Leilei Song and Keshab K. Parhi

21.1 Introduction 58921.2 Mathematical Background 59121.3 Finite Field Arithmetic Architectures Using Standard Basis 59721.4 Finite Field Division Algorithms 61321.5 Finite Field Arithmetic Using Dual Basis Representation 61421.6 Conclusions 617

References 619

22. CORDIC Algorithms and Architectures 623Herbert Dawid and Heinrich Meyr

22.1 Introduction 623

xiv CONTENTS

22.2 The Cordic Algorithm 62422.3 Computational Accuracy 63322.4 Scale Factor Correction 63722.5 Cordic Architectures 64022.6 Cordic Architectures Using Redundant Number Systems 645

References 652

23. Advanced Systolic Design 657Dominique Lavenier, Patrice Quinton and Sanjay Rajopadhye

23.1 Introduction 65723.2 Systolic Design by Recurrence Transformations 65923.3 Advanced Systolic Architectures 67823.4 Conclusion 686

References 687

24. Low Power CMOS VLSI Design 693Tadahiro Kuroda and Takayasu Sakurai

24.1 Introduction 69324.2 Analysis Power Dissipation 69624.3 Low Voltage Circuits 69724.4 Capacitance Reductance 72724.5 Summary 735

References 736

25. Power Estimation Approaches 741Janardhan H. Satyanarayana and Keshab K. Parhi

25.1 Introduction 74125.2 Previous Work 74625.3 Theoretical Background 75025.4 Hierarchical Approach to Power Estimation of Combinatorial

Circuits 75225.5 Power Estimation of Combinatorial Circuits 76125.6 Experimental Results 76225.7 Conclusions 769

References 769

26. System Exploration for Custom Low Power Data Storage andTransfer 773Francky Catthoor, Sven Wuytack, Eddy De Greef, Florin Balasaand Peter Slock

26.1 Introduction 77326.2 Target Application Domain and Architecture Style 77426.3 Related Work 77526.4 Custom Data Transfer and Storage Exploration Methodology 77726.5 Demonstrator Application for Illustrating the Methodology 79026.6 Industrial Application Demonstrators for Custom Realizations 80226.7 Conclusions 805

References 806

CONTENTS XV

27. Hardware Description and Synthesis of DSP Systems 815Lori E. Lucke and Junsoo Lee

27.1 Introduction 81527.2 High Level Synthesis 81627.3 Top Down Design 81827.4 Design Entry 81827.5 Functional Simulation 82627.6 Logic Synthesis 82627.7 Structural Simulation 82827.8 Design Analysis 83027.9 Power Estimation and Low Power Design 831

27.10 Layout 83627.11 Structural Simulation 83727.12 Conclusion 83727.13 Appendix: VHDL Code for 4 Tap FIR Filter 839

References 843

Index 847