2-bit ripple binary counter using JK flip flops (asynchronous counters)

K Q(t+1)0011

0101

Q(t)01

Q’(t)

J

K

J

K

Q1

Q1’

Q0

Q0’

1

CP

CP

J

Q0’

Q0

Q1

0

0

1

0

0

1

1

1

0

0

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3-bit ripple binary counter using JK flip flops (asynchronous counters)

J

K

J

K

Q1

Q1’

Q0

Q0’

1

CP

J

K

Q2

Q2’

Q0’

Q0

CP

Q1

Q2

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Simple Registers

No external gates. Example: A 4-bit register. A new 4-bit data is loaded

on every clock cycle.

A4 A3 A2 A1

I4 I3 I2 I1

CP

Q

D

Q

D

Q

D

Q

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4-bit register with parallel loadLoad

Clear

CP

S Q

S Q

S Q

S Q

R

R

R

R

I1

I2

I3

I4

A1

A2

A3

A4

(Control Signal)

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Register with Parallel Load Using D Flip Flops

D Q

D Q

D Q

D Q

Load

ClearCP

I1

I2

I3

I4

A1

A2

A3

A4

Load A1 + Load I1

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Using Registers to implement Sequential Circuits• A sequential circuit may consist of a register (memory) and a

combinational circuit.Next-state value

• The external inputs and present states of the register determine the next states of the register and the external outputs, through the combinational circuit.

• The combinational circuit may be implemented by any of the methods covered in MSI components and Programmable Logic Devices.

Combinational Circuit

Register

Inputs Outputs

Clock Pulse

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Using Registers to implement Sequential Circuits

• Example 1: Design a Sequential Circuit whose state table is given below using two flip-flops.A1

+ = ∑ m(4,6) = A1. x'

A2+ = ∑ m(1,2,5,6) = A2.x' + A'

2 .x = A2 xy = ∑ m(3,7) = A2.x

Present State

A1 A2

InputNext State

A1+ A2

+xOutput

y

State Table

100111

011011

010101

001001

100110

010010

010100

000000

A1 . x’

A2 x

xy

Logic Diagram

Sequential Circuit Implementation

A1

A2FaaDoOEngineers.com

Using Registers to implement Sequential Circuits• Example 2: Repeat example 1, but use a ROM &Register.

Address Outputs1 2 3 1 2 3A1 A2 x A1 A2 y0 0 0 0 0 0 0 0 1 0 1 0

0 1 0 0 1 0

0 1 1 0 0 1

1 0 0 1 0 0

1 0 1 0 1 0

1 1 0 1 1 0

1 1 1 0 0 1ROM truth table

1 1

2 2

3 3

A1

A2

8 X 3

ROMx y

Sequential circuit using a register and a ROM

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Serial IN/Serial Out Shift Registers

• Accepts data serially – one bit at a time and also produces output serially.

D Q D Q D Q D Q

CLK

Serial Input (SI)

Q0 Q1 Q2 Q3 Serial Output (SO)

Shift Register

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Serial In/Serial Out Shift Registers

• Application: Serial transfer of data from one register to another.

Shift register A Shift register BSOSO SISI

CPClock

Shift Control

Clock

Wordtime

1011 0010

T1 T2 T3 T4

CP

Shift ControlFaaDoOEngineers.com

Serial In/Serial Out Shift Registers

Serial-transfer example.

Timing Pulse

Initial value

After T1

After T2

After T3

After T4

Shift Register A

1

1

1

0

1

0

1

1

1

0

1

0

1

1

1

1

1

0

1

1

Shift Register B

0

1

1

0

1

0

0

1

1

0

1

0

0

1

1

0

1

0

0

1

Serial output of B

0

1

0

0

1

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Q

D

Q

D

Q

D

Q

D

4x1MUX

0123

4x1MUX

0123

4x1MUX

0123

4x1MUX

0123

A3 A2A4 A1

I3 I2I4 I1

Serial input for shift-left

Serial input for

shift-right

Parallel inputs

Parallel outputs

Clear

CLK

S1

S0

Bidirectional Shift Registers 4-bit bidirectional shift register with parallel load

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Bidirectional Shift Registers

• 4-bit bidirectional shift register with parallel load.

Mode Controls1 s0 Register Operation

0 0 No change

0 1 Shift right1 0 Shift left1 1 Parallel load

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An Application-Serial Addition

• Most operations in digital computers are done in parallel. Serial operations are slower but require less equipment.

• A serial adder is shown below. A A+B.

Shift register A

Shift register B

SI

SI

FAxyz

S

C

Q D

Clear

1010

0111

SO

SOExternal input

Shift-rightCP

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S = x + y + Q

JQ = xy

KQ = x’y’ =(x+y)’

Excitation table for a serial adder

Example: Design a serial adder using a sequential logic procedure

with JK flip-flops.Next

StateInputs Output

Present

State

Flip-flop

inputs

Q x y S JQ KQQ

0

0

0

0

1

1

1

1

0

0

1

1

0

0

1

1

0

1

0

1

0

1

0

1

0

0

0

1

0

1

1

1

0

1

1

0

1

0

0

1

0

0

0

1

X

X

X

X

X

X

X

X

1

0

0

0

Q(t) Q(t+1) J

0

0

1

1

0

1

0

1

0

1

X

X

X

X

1

0

K

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Shift register A

Shift register B

SSO=x

SO=y

External input

Shift-rightCP

J

K

Q

Clear

Second form of a serial adder

S = x + y + QJQ = xyKQ = x’y’ =(x+y)’

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4-bit binary ripple counter

J K Q(t+1)

0

0

1

1

0

1

0

1

Q(t)

0

1

Q’(t)

To next stage

Q J Q J Q J Q J1 1 1 1

Countpulses

1 1 1 1K K K K

A3 A2A4 A1

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Count sequence for a binary ripple counter

A4

0

0

0

0

0

0

0

0

1

A3

0

0

0

0

1

1

1

1

0

A2

0

0

1

1

0

0

1

1

0

A1

0

1

0

1

0

1

0

1

0

Complement A1

Complement A1

Complement A1

Complement A1

Complement A1

Complement A1

Complement A1

Complement A1

And so on……

A1 will go from 1 to 0 and complement A2

A1 will go from 1 to 0 and complement A2

A2 will go from 1 to 0 and complement A3

A1 will go from 1 to 0 and complement A2

A1 will go from 1 to 0 and complement A2;

A2 will go from 1 to 0 and complement A3;

A3 will go from 1 to 0 and complement A4

Count sequence Condition for complementing flip-flops

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State diagram of a decimal BCD counter

0000 0001 0010 0011 0100

1001 1000 0111 0110 0101FaaDoOEngineers.com

Logic diagram of a BCD ripple counter

J K Q(t+1)0011

0101

Q(t)01

Q’(t)

Q J Q J Q J Q J1 1

Countpulses

1 1 1 1K K K

Q4Q8

00

Q2

0

Q1

0

01 0 1

Q’ K

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1 1 1 10 0 0 0 1 00

0

0

0

0

0

1

0

0

1

1

1

0

1

1

0

0

1

0

0

1

0

1

0

0

1

0

0

0

0

0

0

0

0

Timing diagram for the decimal counter

Q1

Q2

Q3

Q4

Q5

Count pulses

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BCDCounter

BCDCounter

BCDCounter

Count pulses

102 digit 101 digit 100 digit

0-999 0-99 0-9

Block diagram of a 3-decade decimal BCD counter

Q1Q2Q4Q8Q1Q2Q4Q8Q1Q2Q4Q8

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A4 A3 A2 A1

Q

J

Q

J

Q

J

Q

JKKKK

Count enable

CP

To next stage

J K Q(t+1)0011

0101

Q(t)01

Q’(t)

4-bit synchronous binary counter

Q/Q/Q/Q/

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A4 A3 A2 A1

CP

Q Q Q QQ/ Q/ Q/ Q/

TTTT

UP

Down

4-bit up-down binary counter

To Next stage

T Q(t+1)01

Q(t)Q’(t)

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110011001

010000001

011111110

010000110

011001010

010000010

011101100

010000100

011001000

010000000

yTQ1TQ2TQ4TQ8Q1Q2Q4Q8

Output CarryFlip-flop inputsCount Sequence

Using K-maps, we getTQ1 =1TQ2 = Q/

8Q1

TQ4 = Q2Q1

TQ8 = Q8Q1 + Q4Q2Q1

y = Q8Q1

Q(t) Q(t+1) T

0

0

1

1

0

1

0

1

0

1

1

0

Design a BCD counter using T flip-flops

Excitation table for a BCD counter

Now logic diagram can be drawn for BCD synchronous counter

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y

CP

Q1Q2Q4Q8

Q1Q2Q4Q8

T T T T

1

TQ1 =1TQ2 = Q/

8Q1

TQ4 = Q2Q1

TQ8 = Q8Q1 + Q4Q2Q1

y = Q8Q1

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J Q

J Q

J Q

J Q

K

K

K

K

Count

Load

A4

A3

A2

A1

I4

I3

I2

I1

Clear

CP Carry out

Counters with Parallel Load

4-bit counter with parallel load.

Next State (counting)

101

Load inputsX11

No Change00X1

Clear to 0XXX0

FunctionCountLoadCPClear

J K Q(t+1)0011

0101

Q(t)01

Q’(t)

4-bit binary counter with parallel load

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A4 A3 A2 A1

Count = 1Clear = 1CP

Inputs = 0

Load

(a) Binary states 0,1,2,3,4,5

A4 A3 A2 A1

Count = 1Clear = 1CP

Load

(c) Binary states 10,11,12,13,14,15

A4 A3 A2 A1

Count = 1Load = 0CP

Clear

(b) Binary states 0,1,2,3,4,5

A4 A3 A2 A1

Count = 1Clear = 1CP

Load

(d) Binary states 3,4,5,6,7,8

1 0 1 0 0 0 1 1

Carry-out

Counters with Parallel Load

Different ways of getting a MOD-6 counter

I4 I3 I2 I1 I4 I3 I2 I1

I4 I3 I2 I1I4 I3 I2 I1

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S Q

R

3-bit counterCount enable

CP

CP

Start

Stop

Word-time control

Word-time = 8 pulses

Timing Sequences

(a) Circuit Diagram

(b) Generation of a word-time control for serial operations

CP

Start

Stop

Q

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T3T2T1T0

2 X 4 decoder

2-bit counter

T0 T1 T2 T3

Count enable

Shift right

CP

T0

T1

T2

T3

(a) ring-counter (initial value = 1000)

(b) Counter and Decoder

(c) Sequence of four timing signals

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D Q

Q/

D Q

Q/

D Q

Q/

D Q

Q/

CP

A B C E

(a) 4-stage switch tail ring counter

A/ B/ C/ E/

C/ E10008

B/ C11007

A/ B11106

A E11115

C E/01114

B C/00113

A B/00012

A/ E/00001

And gate required for outputs

Flip-flop outputs

A B C E

Sequence number

(b) Count sequence and

required decoding

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