digital design: sequential circuits for registers and counters

Chapter 16

Sequential Circuits for Registers and Counters

Ch07L13- "Digital Principles and Design", Raj Kamal, Pearson Education, 2006

Lesson 1

REGISTERS


Outline• Register• Parallel-In Parallel-Out Register• Bistable latches as register• Buffer Register


D-FF as 1-bit Register

• A D flip-flop registers at the Q output the bit at D-input. Qn+1 ←D

• This fact can be used to design a multi-bit register


4- bit Register using D-FFs

DQD

D-FFDQC

D-FFDQB

D-FFDQA

D-FF

CLK (Load)

XA XBXC XD

4-bit Output


Timing Diagram when -ve edge Clk D-FFs used CLK(Load)

XA...XD

t

QA...QD


Timing Diagram when +ve edge Clk D-FFs used CLK(Load)

XA...XD

t

QA...QD


Register Inputs and Outputs

• Since the Ds must be set up before a time equal to the setup time, therefore the Ds need to be set-up at the inputs before ts (= set up time) from the clock edge. Next-state Qs are valid when the Ds hold up to th (= hold time) after the edge


Setup Time for Register inputsXA.. XD

• Setup time, ts is an average of the minimum required time for XA.. XD at D inputs before -ve edge of CLK is applied so that the outputs QA.. QD are as per D-FF circuit design and its state table.


Hold Time for Register inputsXA.. XD

• Hold time, th is an average of the minimum required time for input to hold its logic state unchanged after a -ve edge of CLK is applied so that the output QA.. QD is as per the circuit design and its state table.


Register• A register transfers the input D bits to

next Qs such that Q’i (n+1) = Di after an interval from nth clock edge instance plus propagation delay


Clock Edges • A register “looks upon” the data bits at

DD DC DB DA only at the instant of a falling edge (-ve edge) in case of -ve edge D-FFs are used and at rising edge in case +ve edge D-FFs are used. A Register does not care (accept or clock) the data just before rising edge and after th and will care only again at the next rising edge.


Average Propagation Delay in Registering at outputs

• Average propagation delay, tp of a Register is average interval tp from the -ve edge of CLK after which XA.. XDare available at QA.. QD


A parallel in parallel out (PIPO)

• Applied all n-inputs Xs on n-parallel input lines

• All n-outputs Qs are on parallel lines.



• Transfers the input bits X to next Qs such that Q’i (n+1) = X i after nth clock input.

• Loads the external inputs as the excitation inputs and undergoes transition to the next state on a clock transition.



• Gives parallel outputs, which are the same as the next state. [Parallel inputs mean Di = Xi at same time and Parallel outputs mean Yi = Qi at same time where i = 0, 1, 2 or 3 for a 4-bit PIPO. Note: i = 0, 1, 2... n-1 in an n-bit PIPO register]


4- bit Register using D-Latches

DQD

D-Latch

DQC

D-Latch

DQB

D-Latch

DQA

D-Latch

CLK (Load)

XA XBXC XD

4-bit Output


Timing Diagram when + Level 1 CLK at D-Latches

CLK(Load)

XA...XD

t

QA...QD

Latch Transparent region


Bi-stable Latches

• The bi-stable latches, for example, D Latches, arranged in place of the flip-flops in circuit can also store the data.


Transparent Latch as Register • A latch differs from the register in

the sense that after the activation of the clock (enable or strobe or write) input (CLK), the bi-stable latches are transparent, and allow the data bits at DD DC DB DA to pass from the D inputs to the QDQC QB QA outputs during that period.


Outputs from Latches

• The QD QC QB QA stabilizes to the D-values after the CLK input inactivates. If we send a pulse at an CLK input, then the DD DC DB DA should be stable during the entire clock period of activation plus the period for set-up for the inputs plus the period needed for as hold up time of inputs.


Register Outputs for Latches• The last Qs before the CLK

inactivates become the registered values. These outputs appear after a time equal to ∆T (propagation delay) from the inactivation at the CLK.


Buffer Register

• Register, which is used to hold the inputs till they are used by the next stage circuit

• Parallel out register can be used as buffer.


Summary


• Registers register the inputs on clock edge

• Transparent latch is transparent to the inputs during the clock active interval and register the inputs just before the clock inactivation.

• n D-FFs give n-bit register • n D-latches give n-bit transparent latch

register


End of Lesson 1 on

REGISTERS


Thank You

digital design: sequential circuits for registers and counters

Education

raj kamal

pearson education

ch07l13 digital principles

register buffer register

ve edge clk d

d inputs

case ve edge d

ve edge of clk