dheeraj thesis

Design of CMOS based current conveyor and their applications

Chapter 1Introduction

Department of Electronics and Instrumentation Engineering, SGSITS, Indore-452003 1


1.1 Overview

At the time of the introduction of the current conveyor (1968) it was not

clear what advantages the current conveyor offered over the conventional op-

amp. Moreover, the electronics industry was just beginning to focus its efforts on

the creation and application of the first generation of monolithic op-amps.

Without clearly stated advantages, the electronics industry lacked the motivation

to develop a monolithic current-conveyor realization. After all, the op-amp

concept was entrenched in the minds of many analog circuit designers since the

late 1940’s and as far as IC manufacturers were concerned an op-amp market was

already there to be tapped and expanded.

It is only now that analog designers are discovering that the current

conveyor offers several advantages over the conventional op-amp, specifically a

current conveyor circuit can provide a higher voltage gain over a larger signal

bandwidth under small or large signal conditions than a corresponding op-amp

circuit in effect a higher gain –bandwidth-product.

In addition, current conveyors have been extremely successful in the

development of an instrumentation amplifier which does not depends critically

on the matching of external components, instead depends only on the absolute

value of a single component.

In this project we shall introduce the current conveyor concept in its

various forms, demonstrate its various applications, and describe the design and

experimental details of a monolithic current conveyor implemented in 1.5µm

CMOS.



The second-generation current conveyor (CCII) [1] is a versatile analog

building block that presents an alternative method of implementing analog

systems which traditionally have been based on voltage op amps. Conveyor-

based implementations offer improved performance to the voltage op amp based

implementations in terms of accuracy, bandwidth, and convenience due to the

inherent local feedback of the follower based structure of the device and its very

attractive combined voltage–current capabilities.

A new CMOS realization of differential difference current conveyor

(DDCC) is presented. The negative feedback action is introduced by using a

current mirror to reduce channel length modulation effect of MOS transistors.

Furthermore, the circuit is insensitive to the threshold voltage variation caused by

the body effect of MOS transistors. Comparing with conventional design, the

proposed DDCC circuit has less harmonic distortion and larger linear range. A

voltage-mode filter, which simultaneously provides band pass, high pass, and low

pass functions, is also described.

The proposed DDCC circuit is quite useful as a powerful building block

of current-mode circuits because of its high performances, and its application

employs less number of passive elements. SPICE simulations confirm the

excellent properties of the proposed circuits.

1.1 Advantages of current conveyor

Higher voltage gain –The current conveyor circuit can provide a higher

voltage gain over a larger signal bandwidth under small or large signal

conditions.



Successful in the development of an instrumentation amplifier-The

current conveyor current conveyors have been extremely successful in the

development of an instrumentation amplifier which does not depends

critically on the matching of external components, instead depends only

on the absolute value of a single component.

More accuracy – Current Conveyor-based implementations offer

improved performance to the voltage op amp based implementations in

terms of accuracy, and bandwidth.

Larger bandwidths wider dynamic ranges-The current conveyor

attributed to the bandwidths and wider dynamic ranges obtainable

compared to the classical operational amplifier based circuits.

Larger linearity-The current conveyor –based implementations have

larger linearity as compare to voltage mode circuit.

Higher slew rate – Slew rate of current conveyor is more as compare to

voltage mode circuit .this advantage is very useful in filters, and oscillator,

design.

1.2 Applications of current conveyor:

The current conveyor is useful in realization of controlled sources,

impedance converters, impedance inverters, gyrators, and various analog

computation elements as shown in the below table. The differential difference

current conveyor is useful in applications such as analog signal processing,



Automatic control and instrumentation system. The various analog circuits

such as filters, oscillator and CMOS based multiplier; divider can be

implemented with the help of current conveyors.

Table: 1.1.1 Applications to current conveyor to active network synthesis



Table 1.1.2.Application of current conveyor to analog computation

1.3 Chapter Organization

In Chapter 2, the literature review is shown where previous work done in

this field is discussed with problem formulation and objective of the project.

Various types of current conveyor are compared and touched upon in Chapter 3.

Detailed description of current conveyor will be explained in Chapter3.The type

of second generation current conveyor and CMOS representation will be shown

in Chapter4.In Chapter 5 Design of CMOS OP-AMP for second generation



current conveyor and design of Second generation current conveyor (positive

current conveyor and negative current conveyor) will be described. Design of

sinusoidal Oscillator using Second generation current conveyor will be

explained in Chapter 6.The Schematic, Symbol and Simulation results will be

presented in Chapter 7.The conclusion and future scope of the project is in

Chapter 8.



Chapter 2Literature Review



2.1 IEEE Papers Review with Critique

The current conveyor introduced in 1968 by A. S. Sedra and K. C. Smith.

At the time of the introduction of the current conveyor it was not clear what

advantages the current conveyor offered over the conventional op-amp.The

electronics industry was focus its efforts on the creation and application of the

first generation of monolithic op-amps. The second generation current conveyor

CCII introduced by Sedra and Smith is widely used in realization of filters and

oscillators. It is available with both polarity as CCII+ and CCII-. By connecting

CCII+ and CCII- together a dual output CCII (DOCCII) is formed which has

got its importance in current mode filter realizations.

The circuit design principles and techniques for current-mode processing,

such as the Trans linear circuit principal introduced by Barrie Gilbert in 1972 are

becoming powerful tools for the development of high performance analogue

circuits and systems. A further consequence of the development of current mode

analogue signal processing has been the emergence of new analogue building-

blocks ranging from the current conveyor and current-feed back op-amp through

to sampled-data current circuits such as dynamic current-mirrors and analogue

neural networks. It has proved to be functionally flexible and versatile, rapidly

gaining acceptance as a practical device with a wide range of high performance

circuit and system applications. The recent introduction of a commercially

integrated circuit current conveyor is reported and is indeed very timely and

welcome.



The accurate CMOS based Current Conveyor technique for implementing

both positive and negative second generation current conveyor (CCII) is

described by Wanlop Surakampontorn, Reiewruja, Kiattisak Kumwachara,

and Kobchai Dejhan .It can be employed as an element in adigital- to- analog

converter that can provide current source output, or as a current measuring device

in a digital measurent of current, or as a plug-in unit or probe for a digital

voltmeter.

High CMRR and low THD current-Mode Instrumentation amplifier using

current inversion technique is introduced by Behnam Babaei and Sattar

Mirzakuchaki. The current mode instrumentation amplifier based on second

generation current conveyor (CCII) offers many benefit over conventional

instrumentation amplifier architectures. It does not need any matched

components to achieve high CMRR and its bandwidth is not gain-bandwidth

product limited. Therefore, a wideband CMOS current conveyor has been used in

this structure.

A new CMOS realization of Differential difference current conveyor

(DDCC) is presented by Jamping Hu, Yinshui Xia and Tiefeng Xu Huiying

Dong. The negative feedback action is introduced by using a current mirror to

reduce channel length modulation effect of MOS transistors. Furthermore, the

circuit is insensitive to the threshold voltage variation caused by the body effect

of MOS transistors. Comparing with conventional design, the proposed DDCC

circuit has less harmonic distortion and larger linear range. A voltage-mode filter,

which simultaneously provides band pass, high pass, and low pass functions, is

also described.



The Proposed DDCC circuit is quite useful as a powerful building block of

current-mode circuits because of its high performances, and its application

employs less number of passive elements.

A new wideband BiCMOS differential current conveyor is presented by

Hesham. F. Hamed, Ahmed EI-Grafery Mostafa S. A. EI-hakeen The

proposed differential current conveyor has the advantage of a wide bandwidth

(about 1GHz). It can be directly used with MOS transistors operating in the

ohmic region to implement the require analogue functions. As an application of

the proposed (DCCII) a four quadrant current multiplier is presented using

differential current conveyor.

A novel second-generation current conveyor (CCII)- based resistance–

capacitance (RC) sinusoidal oscillator operating over a wide dynamic range is

described Anwar A. Khan, Sadanand Bimal, K. K. Dey, and S. S. Roy. The

circuit proposed makes use of grounded capacitors and is suitable for

implementation with the commercially available integrated circuit chip AD844

from Analog Devices which implements a CCII+. The AD844 devices which

implements a CCII+ is BJT based. The circuit enjoys low sensitivities and is

suitable for integration.

Current conveyors and related current-mode circuits have begun to emerge

as an important class of circuits with properties that enable them to rival their

voltage-mode counterparts in a wide range of applications. The use of current

rather than voltage as the active parameter can result in higher usable gain,

accuracy and bandwidth due to reduced voltage excursion at sensitive nodes.



2.2 Problem Formulation

Accurate, low-cost, rapid-prototyping techniques for analog circuit have been

a long awaited dream for analog designers. However, due to the inherent nature

of analog system, design automation in analog domain is very difficult to realize

and large portion of parasitic into the sensitive analog system, thus degrades the

system performance.

(1) Big influence of technology: Technology and environmental

parameters show a large influence on analog circuits. Process, biasing

or temperature variations and layout parasitic strongly influence the

circuit performance and can even change the functionality of the circuit.

(2) Interactions at the system level: Analog circuit are also very sensitive

to interaction at the system level. The interaction may be between two

analog blocks, or between analog block and digital block of a large

system such as clock noise. Similarly, if several different channel of a

data-acquisition system are integrated on one chip, strong crosstalk may

happen between these channel and cause serious signal integrity issue.

(3) Large spectrum of specifications: More performance specification are

imposed on analog circuit. Additionally, the specifications often impose

conflicting requirement on the design resulting in many trade-offs to be

managed during the design, becoming a multidimensional problem

difficult to handle



(4) Lack of CAD tools: lake of analog CAD tools that can increase the

efficiency of analog circuit and system designers

2.3 Objective of the project

The goal of the presented work is to develop a current conveyor, which is

suitable for implementation of analog circuits. This would enable designers to

show advantages of current conveyor over voltage-mode circuits. The current

conveyor offers several advantages over the conventional op-amp; specifically a

current conveyor circuit can provide a higher voltage gain over a larger signal

bandwidth under small or large signal conditions than a corresponding op-amp

circuit in effect a higher gain –bandwidth-product.

In addition, current conveyors have been extremely successful in the

development of an instrumentation amplifier which does not depends critically

on the matching of external components, instead depends only on the absolute

value of a single component. In applications such as analog signal processing,

automatic control, and instrumentation systems, processing differential voltage

signals is very common, thus a single voltage input terminal is hardly competent.

The proposed DDCC circuit is quite useful as a powerful building block of

current-mode circuits because of its high performances. The DDCC is useful for

processing differential voltages signals.

The conventional current conveyor (CCI and CCII) have apparent

disadvantage of having only one input terminal in the. Differential difference

current conveyor, it have multi input voltage terminal and also have differential



voltage signal at X input current terminal. The proposed current conveyor circuit

is useful for implementation of different filter and generation of oscillation.



Chapter3CMOS based current conveyor

3.1 Type of current conveyorDepartment of Electronics and Instrumentation Engineering, SGSITS, Indore-452003 15


In voltage-mode circuits, the main building block used to add, subtract,

amplify, attenuate, and filter voltage signal is the operational amplifier. In

current-mode circuit, the analogous building block is the current conveyor.

The original current conveyor was a three- terminal device (two input terminal

X and Y and one output terminal Z) with following properties:

1. The potential at its input terminal (X) is equal to the voltage applied at the

other input terminal (Y).

2. An input current that is forced into node X results in an equal amount of

current flowing into node Y.

3. The input current flowing into node X is conveyed to node z, which has

the characteristics of a high output impedance current source.

The term conveyor refers to the third property above; Current is conveyed from

the input terminal to the output terminal, while decoupling the circuits connected

to this terminal.

Fig. 3.1.1 Symbol of current conveyor



3.2 THE FIRST CURRENT CONVEYOR (CCI)

The current conveyor (CCI), as initially introduced, is a 3-port device

whose black–box representation can be seen in figure 3.2.1. the operation of this

device is such that if a voltage is applied to input terminal Y, an equal potential

will appear on the input terminal X. In a similar fashion, an input current I being

forced into terminal X will result in an equal amount of current flowing into

terminal Y. As well, the current I will be conveyed to output terminal Z such that

terminal Z such that terminal Z has the characteristics of a current source , of

value I, with high output impedance. As can be seen, the potential of X, being set

by that of Y, is independent of the current being forced into port X. Similarly, the

current through input Y, being fixed by that of X, is independent of the voltage

applied at Y. Thus the device exhibits a virtual short–circuit input characteristic

at port X and a dual virtual open-circuit input characteristic at port Y.

Fig.3.2.1 Fig.3.2.2

Fig.3.2.1. Black-box representation of the current conveyor

Fig.3.2.2. Nullator-norator representation of CCI. The downward arrow in the

controlled source at Z is for a CCII+, the upward arrow for a CCII-.



In mathematical terms, the input-output characteristics of CCI can be

described by the following hybrid equation:-

Where the variables represent total instantaneous quantities, Note the + sign

applies for the CCI in which both Z and X flow into the conveyor, denoted CCI

into the conveyor, denoted CCI+. The – sign apply for the opposite polarity case,

denoted CCI-.

To visualize the interaction of the port voltages and current described by the

above matrix equation the nullator-norator representation (commonly referred to

as a nullor) shown in figure 3.2.2 may be helpful. In this figure single ellipse is

used to represent the nullator element and two intersecting ellipses to represent

the norator element. The nullator element has constitutive equation V=0 and I=0

whereas the norator has an arbitrary voltage-current relationship. Clearly, the

nullator element is used to represent the virtual short circuit apparent between the

X and Y terminals. Also included in this equivalent circuit are two dependent

current sources. These are used to convey the current at port X to port Y and Z.



The Second generation current conveyor (CCII)

To increase the versatility of the current conveyor, a second version in which no

current flows in terminal, Y was introduced. This building block has since proven

to be more useful than CCI. Utilizing the same block diagram represented of

figure 3.1.1, CCII is described by

Thus terminal Y exhibits a infinite input impedance. The voltage at X

follows that applied to Y, thus X exhibits zero input impedance. The current

conveyed to the high-impedance output terminal Z where it is supplied with

either positive polarity (CCII+) or negative polarity (CCII-).

THE CIRCUIT REALIZATION OF CCII

The CCII may be viewed as an ideal transistor, either bipolar or MOS. To

illustrate this point, consider the NMOS transistor shown in figure 3.3.1 If the

transistor were ideal, its VGS would approach zero. In such a case a voltage

applied to the gate would result in an equal voltage at the source. While the gate

terminal would approximate an open circuit (as the conveyor terminal Y), the

source terminal would exhibit zero input impedance (just as the conveyor

terminal X). A current injected at the source would be conveyed to the drain

where the impedance level would be infinite (just as terminal Z in the

conveyor).It follow that an ideal transistor behaves as a negative current

conveyor (CCII-).



Fig. 3.3.1

Fig. 3.3.1 Comparison of CCII - and NMOS transistor conveyor

Fig3.3.2

Fig. 3.3.2 Negative current conveyor using a ‘super transistor’

To create a more ideal transistor we place the NMOS transistor in the

negative feedback loop of op-amp, as shown in figure 3.3.2. The result is a CCII-

with reasonably good performance.



In this CCII- realization, however, current is restricted to flow out of

terminal X. An alternative CCII realization can be obtained by placing a PMOS

transistor in the negative feedback loop of an op-amp, in which case current will

restricted to flow into the X terminal. It follow that a CCII realization allows

bidirectional current flow can be obtained by placing a complementary pair of

MOS transistors in the op-amp feedback path as. Subsequently, this current is

transferred to the output node via a complementary pair of current mirror.

Observe, however that this circuit is now a CCII+ realization. To obtain a CCII-

circuit two additional complementary current mirrors are required.

3.4 Differential difference current conveyor

Since the first-generation current conveyor (CCI) was proposed, the

second-generation and third-generation current conveyors (CCII and CCIII) have

been introduced. These current conveyors have proven to be very useful building

blocks for current mode circuits. Many references have demonstrated the

universality in the synthesis of almost all known active networks. However,

conventional current conveyors have an apparent disadvantage of having only

one input terminal. In applications such as analog signal processing, automatic

control, and instrumentation systems, processing differential voltage signals is

very common, thus a single voltage input terminal is hardly competent.

Considering this drawback, several new current-mode building blocks to handle

differential signals were presented in recent years. However, the performances of

these building blocks, such as linearity, precision and dynamic range etc, are

dissatisfied compared to the conventional ones. For example, in order to ensure

precision the output dynamic range of DVCC is less than ±0.8V.if the supply

voltages are taken as ±2.5V.



The DDCC is a six port building block as shown in figure 3.4.1. It has

three voltage input terminal Y1, Y2 and Y3 which have high input impedance.

Terminal X is a input low impedance current input terminal. There are two high

impedance current out put terminal Z1 and Z2. The input output characteristics of

the DDCC is defined as

Fig. 3.4.1 Symbol of DDCC

The output currents (Iz+ and Iz-) follow the input current through terminal

X. Iz+ has the same polarity as Ix, and Iz- is in the opposite polarity as Ix. The

voltage of X terminal is related by the three inputs voltage: Vx=VyI-Vy2 +Vy3.

The negative feedback action is introduced by using a current mirror to

reduce channel length modulation effect of MOS transistors. Furthermore, the

circuit is insensitive to the threshold voltage variation caused by the body effect

of MOS transistors. Comparing with conventional design, the proposed DDCC

circuit has less harmonic distortion and larger linear range.

A voltage-mode filter, which simultaneously provides band pass, high

pass, and low pass functions, is also described. The proposed DDCC circuit is

quite useful as a powerful building block of current-mode circuits because of its

high performances, and its application employs less number of passive elements.

A number of applications, such as filters, oscillators, analog-digital converter,

and analogue signal processing blocks based on current conveyors can be

implemented with the use of DDCC.



Chapter 4CMOS based Second generation current

conveyor and DDCC



4.1 Types of second generation current conveyor.

The Second generation current conveyor can be divided in to two types

depending upon the direction of current flow at input current terminal and out put

current terminal. The first type is positive current conveyor in witch the direction

of current at input current terminal and out put current terminal will be same. The

second types of current conveyor is Negative current conveyor in witch the

direction of current at input current terminal and out put current terminal will be

differ.

4.2. Positive current conveyor

The first circuit implemented is the positive current conveyor since negative

current conveyor can be considered an extension of the positive current

conveyor. In the implementation, simple current mirror were used despite their

low output impedance and poor current gain. The reason behind this choice

follows from the allowable signal swing at the X terminal. (Refer to figure 1.6(a))

is determined by the state of transistor M1 while the negative signal swing is

determined by M2.

As long as both transistors remain saturated, the output stage of the op-amp

will perform as expected. Thus the negative signal swing is restricted to Vds sat2

above the negative input bias voltage of the n-channel current mirror while the

positive signal swing is restricted to Vds sat1 below the positive input bias

voltage of the p-channel current conveyor. The circuit implementation of the

positive current conveyor is shown in fig. 4.2.1.



Fig: 4.2.1 Positive current conveyor

4.3 Negative current conveyor

The negative current conveyor circuit can be derived from the positive

current conveyor through addition of two current mirrors. Unlike the current

mirror of the positive current conveyor, the additional current mirrors are not

restricted to small input voltages. As such, either simple or stacked current

mirrors can be used to achieve different current conveyor performances.

Fig.4.3.1 Negative current conveyor



A Negative current conveyor using simple current mirrors was illustrated

in figure 4.3.1. The dimensions of the transistors making up the simple current

mirrors are identical to those used in the positive current conveyor. We depict a

negative current conveyor using stacked current mirror in fig 4.3.1.

The only difference between fig 4.3.2 & fig 4.3.1 is that the second pair of

simple current mirror has been replaced by a pair of stacked current mirrors.

Reduction of the channel length is possible in the stacked current mirrors due to

the high impedance nature of the circuit.

Fig. 4.3.2 Fig. 4.3.3

Fig. 4.3.4



Fig.4.3.2. Negative current conveyor design using stacked current mirrors.

Fig 4.3.3 Measured large-signal voltage characteristics between terminal Y & X

for the positive & Negative current conveyor.

Fig.4.3.4 Measured small-signal magnitude response of the voltage gain between

terminal X &Y.

4.4. CMOS based Differential difference current conveyor.

The DDCC is a six port building block as shown in figure 4.4.1 it has three

voltage input terminal Y1, Y2 and Y3 which have high input impedance.

Terminal X is a input low impedance current input terminal. There are two high

impedance current out put terminal Z1 and Z2. The input output characteristics of

the DDCC is defined as

Fig. 4.4.1 Symbol of DDCC and matrix representation of DDCC



Fig.4.4.2. CMOS realization of differential difference current conveyor.

The output current (Iz+ and Iz-) follow the input current through terminal X. Iz+

has the same polarity as Ix and Iz- is in the opposite polarity as Ix. The voltage of

X terminal is related by the three input voltages

In the CMOS realization of the DDCC all transistor operate in the saturation and

the bulk is connected to the appropriate positive and negative supply rail

Therefore,

From above two equation

Therefore,

The current through terminal X is conveyed to Z+ terminal by the current

mirrors, which consist of transistors M13 ,M15 and M14, M16 by using extra

current mirrors ,current through terminal X is conveyed to Z- terminal with

negative polarity.



Chapter 5Design of CMOS based current conveyor



5.1 Design of CMOS OP-AMP for second generation current conveyor:

To design a two stage operational amplifier to meet the following specification:

1. Open Loop Gain >70dB

2. Power supply = +/- 2.5V

3. Load capacitance = 10pF

4. Slew Rate (pos) = 1.971V parsec

5. Slew Rate (neg) = -2.09Vparsec

6. Unity Gain Freq = 2.2MHz

7. 3dB Frequency = 410Hz

8. Channel Length = 1.5µm

9. Biasing current IB = 25µA

Basic relationship used in the designing process:

1. Voltage Gain of First Stage Av1 = gm1 (ro2 ║ ro4 )

2. Second Stage Gain Av2 = gm6 (ro6 ║ ro7 )

3. The D.C open loop Gain of Op-amp Av = Av1 * Av2

4. The Early voltage for MOSFET is VA = VlA*L

(Where VlA = Early voltage for per unit length)

VA=1/λ (where lambed is channel length modulation)

5. The out put resistance of device is ro=|VA|/ID

6. The transconductance of device gm=2 ID/Vov

(Where Vov is overdrive voltage Vov = (VGS -Vt ))

7. From open loop Gain Av= gm1(ro2║ro4) gm6(ro6║ro7)

= 2(I/2)/ Vov*1/2*( VA/(I/2)*2 ID6/ Vov*1/2* VA/ ID6

= ( VA/ Vov)2

8. Overdrive voltage Vov = (VGS -Vt ) can be determined from equation (7)



9. To obtain the required (W/L) ratio of Q1 and Q2 by

ID1= ½ *Klp*(W/L)1* V2

ov

10. For (W/L) ratio of Q3 and Q4

ID3= ½ *Kln*(W/L)3* V2

ov

(In equation (9) and (10), Klp and Kl

n is transconductance parameter for PMOS

and NMOS.)

11. The (W/L) ratio for Q5 , Q7 , and Q12 is obtained by

ID5,12,7= ½ *Kln*(W/L)5,12,7* V2

ov

12. The (W/L) ratio for Q6 is obtained by

(W/L)6/(W/L)4 =2 (W/L)7/(W/L)5

13. The input common-mode range can be found by

-Vss+ Vov3+ Vt3- |Vtp| ≤VICM ≤ VDD-|Vtp|-|V ov1|-|V ov5|

14. The maximum signal swing allowable at the output is found by

-Vss+ Vov6 | ≤Vo≤ VDD-|V ov7|

15. The output resistance is

Ro= (ro6 ║ ro7 )

16. Frequency Response

C1= Cgd2+ Cdb2+ Cgd4+ Cdb4+ Cgs6 and

C2= Cdb6+ Cdb7+ Cgd7+CL

We know that

Gm1=gm1= gm2

And Gm2=gm6

Then unity gain frequency Ft

Ft = Gm1/2Л Cc or Cc= Ft*2 Л/ Gm1

To achieve the goal of a uniform -20dB/decade gain roll off down to 0 dB the

design must satisfy

Gm1/ Cc< Gm2/ C2 or Gm1< Gm2



17. Slew rate S.R=I/Cc or S.R=2 Л Ft Vov

18. Design of class AB buffer: A class AB based buffer is formed by transistor

M8, M9, M10, and M11. The gate of M7 is biased with a Dc voltage. So that its DC

drain current is equal to the DC current through M6. MOSFET M6 is simply a

current source. The Gate source voltage of M8 and M9 are constant (because of

the constant current provided by M6) and used as the biasing voltage needed to

bias M10 and M11on. This configuration is useful as an output buffer in an op-amp

when the gate of M7 is connected to an active load used in a differential pair and

the gate of M6 is connected to the same biases voltage as used in the differential

amp current source.

Table:5.1.1 CMOS Transistor sizing for two stage Op-amp desing.

Department of Electronics and Instrumentation Engineering, SGSITS, Indore-452003

S.No. Transistor W/L

1. M1,M2 25.7/0.6

2. M3,M4 7.5/1.5

3. M5,M7,M12 22.5/1.5

4. M6 14.25/1.5

5. M8,M10 40/0.755

6. M9 86.25/0.75

7. M11 120.75/.75

32


5.2 Design of CMOS based Positive current conveyor.

In positive current conveyor the design of op-amp is similarly as shown

above and the design of two current mirror units is given below. In current

conveyor the current mirror is formed by transistor MN1, MN2 and MP1, MP2.

The current flow through MP1 corresponding to VGSP1. Since VGSP1=VGSP2, Ideally

the same current or a multiple of the current in MP1 flow through MP2 If the

MOSFET are the same size the same drain current flow in each . MOSFET

provided MP2 stay in the saturation region. The current IMP is given by

IMP1= β1/2*(VGS1 -Vthp )2 5.2.1

IMP2= β2/2*(VGS2 -Vthp )2 5.2.2

IMP1/ IMP2 = (W/L)2/(W/L)1 = β2/ β1 5.2.3

The equation show how to adjust the W/L ratio of the two devices to

achieve the desired output current IMP2..The design of second current mirror is

similarly as explained.


1. M1,M2 25.7/0.6

2. M3,M4 7.5/1.5

3. M5,M7,M12 22.5/1.5

4. M6 14.25/1.5

5. M8,M10 40/0.755

6. M9 86.25/0.75

7. M11 120.75/.75

8. MP1,MP2 54.75/1.5

9. MN1,MN2 30/1.5



Table: 5.2.1 CMOS Transistor sizing for Positive current conveyor.

5.3 Design of CMOS based Negative current conveyor.

In design of CMOS based negative second generation current conveyor the

process for design of op-amp is similarly as explained above and the process for

design of extra current mirror unit is same as explained in positive current

conveyor The negative current conveyor circuit can be derived from the positive

current conveyor through addition of two current mirrors. Unlike the current

mirror of the positive current conveyor, the additional current mirrors are not

restricted to small input voltages. As such, either simple or stacked current

mirrors can be used to achieve different current conveyor performances.


1. M1,M2 25.7/0.6

2. M3,M4 7.5/1.5

3. M5,M7,M12 22.5/1.5

4. M6 14.25/1.5

5. M8,M10 40/0.755

6. M9 86.25/0.75

7. M11 120.75/.75

8. MP1,MP2,MP3,MP4 54.75/1.5

9. MN1,MN2,MN3,MN4 30/1.5

Table: 5.3.1 CMOS Transistor sizing for Negative current conveyor.



5.4 Design of CMOS based Differential difference current conveyor.

The output current (Iz+ and Iz-) follow the input current through terminal

X. Iz+ has the same polarity as Ix and Iz- is in the opposite polarity as Ix. The

voltage of X terminal is related by the three input voltages

In the CMOS realization of the DDCC all transistor operate in the saturation and

the bulk is connected to the appropriate positive and negative supply rail

Therefore,

From above two equation

Therefore,

The current through terminal X is conveyed to Z+ terminal by the current

mirrors, which consist of transistors M13 ,M15 and M14, M16 by using extra

current mirrors ,current through terminal X is conveyed to Z- terminal with

negative polarity.



Chapter 6Design of sinusoidal Oscillator using Second generation current conveyor



6.1 Overview.

A novel second-generation current conveyor (CCII) - based

resistance–capacitance (RC) sinusoidal oscillator operating over

a wide dynamic range is described. The oscillation condition and

the oscillation frequency can be adjusted independently by two

control resistors. The circuit proposed makes use of grounded

capacitors the circuit enjoys low sensitivities and is suitable for

integration. Sinusoidal oscillators of variable frequency find

extensive applications in communication systems,

instrumentation, and measurement. Voltage-mode operational

amplifier (op-amp)-based circuits have been shown to be very

well suited for the generation of sinusoidal waveforms

incorporating resistance–capacitance (RC) networks. The

simplicity in the design approach turns into a disadvantage

when it is desired to change the frequency of oscillation

independent of the necessary and sufficient condition required

to sustain the oscillations. Moreover, the dynamic range of

operation is dictated by the frequency-dependent gain of op-

amp. The composite op-amp configurations are then used to

overcome the shortcomings of one op-amp-based oscillator. The

OTA-C-based circuits, and the current feedback amplifier (CFB

op-amp)-based circuits, have been shown to offer improved

performance over the conventional op-amp-based oscillators. In

recent years the current-mode approach of signal processing

has provided elegant solutions for analogue circuit problems.

The main advantages that this mode of operation exhibits are

wide bandwidth, high slew rate and the fact that the gain can be Department of Electronics and Instrumentation Engineering, SGSITS, Indore-452003 37


realized independent of a constant gain-bandwidth product

constraint.

6.2 Proposed sinusoidal oscillator circuit using positive. Current conveyor

The second-generation current conveyor (CCII) is

sometimes claimed as the standard building block of the current

mode operation which stems largely from the fact that the CCII

offers a useful way of realizing complex circuit functions.

Fig.6.2.1 Symbol of CCII

Fig.6.2.1 shows the symbol of a CCII. Whose terminal

characteristics can be defined by a hybrid matrix giving the

output of the three ports in terms of their corresponding inputs.

The output current , thus, depends only on the input current at

terminal X (Fig.6.2.1) which may be injected directly at X, or it

may be produced by the copy of the input voltage , from

terminal Y, acting across the impedance connected at X. The

sign in (1) indicates whether the conveyor is formulated as an

inverting or noninverting circuit, termed CCII+ or CCII- . By



convention, positive is taken to mean and both flowing

simultaneously toward or away from the conveyor (Fig.6.2.1).

The use of second-generation current conveyors, CCII+ or CCII- ,

for the design of RC sinusoidal oscillator circuits has been

demonstrated to be potentially advantageous in regard to

dynamic range of operation and the overall operational stability.

In recent years, their applications and advantages in the

synthesis of RC sinusoidal oscillators with the salient features of

controlling the frequency of oscillation without affecting the

condition for oscillation have received considerable attention. In

the absence of a commercially available integrated circuit

current conveyor RC sinusoidal oscillator configurations reported

earlier were tested in the laboratory, employing current

conveyor features implemented using op-amps with current

mirrors. The use of second-generation current conveyors, CCII +or CCII -, for

the design of RC sinusoidal oscillator circuits has been demonstrated to be

potentially advantageous in regard to dynamic range of operation and the overall

operational stability .In recent years, their applications and advantages in the

synthesis of RC sinusoidal oscillators with the salient features of controlling the

frequency of oscillation without affecting the condition for oscillation have

received considerable attention. The proposed RC sinusoidal oscillator using

CCII+ with grounded capacitors is depicted in Fig.6.2.2



Fig.6.2.2. Proposed sinusoidal oscillator circuit using positive. Current conveyor

6.3 Unity gain buffer formed with CCII+

The unity gain buffer can be formed with the help of current conveyor.

When Z terminal of current conveyor is connected to earth then unity gain

voltage buffer will be formed. For unity gain current buffer the Y terminal will be

Connected to earth. The W terminal is formed with unity gain buffer .The

positive current conveyor can be used as a unity gain buffer as shown in the fig

6.3.1.

Fig 6.3.1 Unity gain buffer formed with CCII+

Fig 6.3.2 Unity gain buffer with CCII+



6.4 Circuit Description and analysis.

The current conveyor is useful for design of sinusoidal Oscillator. With the

help of property of current conveyor following equation can formed

iz1 = ix1 (1)

iz2 = ix2 (2)

Vo1 = iz1. Z1 (3)

Vo = iz2. Z2 (4)

ix1= Vo1- Vo/Rc (5)

ix2= Vo1/Rf (6)

Where

Z1= (R1\\C1) = R1/1+s R1 C1 (7)

Z2= (R2\\C2) = R2/ 1+s R2 C2 (8)

With s= jω where ω is the angular frequency in rad/s

S2 +2ξ.S +ω2=0 (10)

Where

(11) 2 Rc R1 R2 C1C2

(12) RcRf R1 R2 C1C2

Where ξ and ω are frequently referred to as the attenuation and the natural

angular frequency, respectively. For the sake of convenience let us select the

circuit components such that R1= R2=R and C1= C2=C. Substituting this selection

in (11) and (12), one gets

(13)Rc. RC



And

(14) R2C2

The roots S1 and S2 of (10) are seen to be

S1, S2 = - ζ ± (ζ - ω2 )½ (15)

For sustained oscillation, from (15), one may infer that ζ must be zero. Thus,

from (13) we get

Rc = R/2 (16)

Putting (16) in (14) yields

ω = ω0.(2R/Rf - 1)½ (17)

Where ω0 is the angular frequency in rad/s for Rf = R and is defined as

ω0 = 1/RC (18)

Further, for oscillations to grow, from (15) it may be seen that ζ must be negative

and hence from (13) one gets

Rc < R/2 (20)

The oscillation, on the other hand, will die out when Rc > R/2. From (16) and (17)

it may be seen that the frequency of oscillation can be controlled by the ground

resistor Rf without affecting the condition of oscillations. The value of Rf should,

However, be kept less than or equal to R.



Chapter 7Simulation Results and Discussion



7.1 Simulation Results of Two stage CMOS Op-amp

Fig. 7.1.1 Schematic of two stage CMOS Op-amp

S.NO. Experimental Results

1. Open loop Gain 72.5dB

2. 3dB frequency 410Hz



3. Unity Gain

Frequency

5.22MHz

4. Slew Rate (pos) 1.971V/µsec

5. Slew Rate (neg) 2.09V/ µsec

6. Leakage power 1.35mW

7. Input Offset Voltage 0.0275mV

8. Biasing current 25µA

9. Rbias 353k

10 Coupling capacitor 5.1pf

Table: 7.1.2 Measured parameter of two stage Op-amp

Fig; 7.1.3 Gain and phase response of two stage CMOS Op-amp



The open Loop Gain obtained 72.5dB which conform to the design

parameters we took during the start of the design i.e. Open loop gain should be

grater than 70dB

Fig: 7.1.4 Leakage power consumed by two stage op-amp

The Leakage power consumed by two stage CMOS Op-amp is 1.35mW as

shown in the above figure.



Fig; 7.1.5 the sinusoidal voltage source is applied at in-put

The out –put obtained has sinusoidal amplify voltage when in-put is

sinusoidal voltage source. The Input Offset Voltage is 0.0275mV.



Fig: 7.1.6 In-put and out-put of two stage CMOS op-amp when unity step voltage

source is applied.

For calculation of Slew-rate the unity step voltage source is applied. The

slope of positive edge and negative edge of out-put is slew rate for two stage

CMOS based Op-amp. The measured value of slew rate is 1.971V/µsec for

positive edge and 2.09V/ µsec for negative edge.



7.2 Simulation Results of Second generation CMOS based Positive current

conveyor

Fig: 7.2.1 Schematic of Second generation CMOS based Positive current

conveyor.

Table: 7.2.2 Current at current in-put terminal (X) and current out-put terminal

(Z+)


S.No. Current at

Input

Terminal

(µA)

Current at

Output

Terminal (µA)

1 10 10.63

2 50 50.00

3 100 99.73

4 150 149.94

5 200 200

6 300 297.4

7 350 345.67

49


The above table shown the relationship at current input terminal (X) and

current out -put terminal (Z+). When an input current I being forced into terminal

X will result in an equal amount of current flowing into terminal Z+ with same

polarity up to current range o to 300 µA.

Table 7.2.3 Voltage at terminal Y, X and current at terminal Z+ when 50 µA is

applied at terminal X.

The above table shown that whatever the voltage applied at Y terminal it

will convey to X terminal and independence the value of current applied at X

terminal up to voltage range 1.35 to -1.35.


S.NO.

Voltage at Y

terminal (Vy)

(Volt)

Voltage at X

terminal (Vx)

(Volt)

Current at out

put terminal

(Z+) (µA)

1 1.50 1.35 50.98

2 1.35 1.34 51.11

3 1.25 1.25 50.00

4 1.00 1.00 50.90

5 0.50 0.50 49.9

6 -0.50 -0.50 49.9

7 -1.00 -1.00 49.9

8 -1.50 -1.57 49.9

9 -2.00 -1.57 49.9

10 -2.50 -1.57 49.9

50


S.No. Voltage at X

terminal (Vx)

(Volt)

Current at

Output

Terminal (µA)

Load at Out

put terminal

1 -1 49.98 10 Ω

2 -1 49.98 100 Ω

3 -1 49.98 10000 Ω

4 -1 49.98 10k Ω

5 -1 49.98 15k Ω

6 -1 47.89 20k Ω

7 -1 47.45 25k Ω

8 -1 47.30 30k Ω

9 -1 46.41 35k Ω

Table: 7.2.4 showed the variation of resistive load with out-put current.

The above table show that what the current applied at input terminal X will

be conveyed to current output terminal Z+ up to resistive load 15k Ω .

Fig: 7.2.5 Voltage at current in-put terminal when -1V is applied at Y terminal.



The above figure shown that when in-put voltage at Y terminal is applied

then equal voltage will be appear at X terminal and independence the value of

current applied at X terminal.

Fig: 7.2.6 Current at out-put terminal Z+ when 50 µA is applied at X terminal.

The above figure shown the property of current conveyor Ix =Iz+. Where Ix

is the current at input terminal X and Iz+ is the current at out-put terminal Z+. The

current at input terminal is conveyed to output terminal as shown in figure.



Fig: 7.2.7 the leakage power consumed by positive current conveyor.

The leakage power consumed by CMOS based positive current conveyor is

2.24mW.

Fig: 7.2.8 the variation of voltage at X terminal when sinusoidal voltage source is

applied at in-put terminal Y.



The above figure shown the property Vx =Vy for CMOS based positive

current conveyor when sinusoidal voltage source is applied at in-put terminal Y.

The same voltage will fallow by terminal X.



7.3 Simulation Results of Second generation CMOS based Negative current

conveyor.

Fig: 7.3.1 Schematic of Second generation CMOS based Negative current

conveyor.

S.No. Current at Input

Terminal (µA)

Current at Output

Terminal (µA)

1 20 20.61

2 40 41.98

3 60 61.23

4 80 85.24

5 100 105.81

6 120 126.51

7 140 146.86

8 160 167.08

9 260 267.36

10 280 287.24

11 380 386.40

12 400 405.55

13 440 426.26

Table: 7.3.2 Current at current in-put terminal (X) and current out-put terminal

(Z-)Department of Electronics and Instrumentation Engineering, SGSITS, Indore-452003 55


The above table shown the relationship at current input terminal (X) and

current out -put terminal (Z+). When an input current I being forced into terminal

X will result in an equal amount of current flowing into terminal Z- with opposite

polarity up to current range o to 60µA.

S.NO. Voltage at Y

terminal (Vy)

(Volt)

Voltage at X

terminal (Vx)

(Volt)

Current at out

put terminal

(Z+) (µA)

1 1.50 1.41 20.1

2 1.25 1.24 20.1

3 1 1 20.1

4 -0.25 -0.2487 20.1

5 -0.50 -0.50 20.1

6 -0.75 -0.75 20.1

7 -1.00 -1.00 20.1

8 -1.25 -1.25 20.1

9 -1.50 -1.5 20.1

10 -1.75 -1.53 20.1

Table 7.3.3 Voltage at terminal Y, X and current at terminal Z+ when 20 µA is

applied at terminal X.

The above table shown that whatever the voltage applied at Y terminal it

will convey to X terminal and independence the value of current applied at X

terminal up to voltage range 1.25 to -1.5.



S.No. Voltage at X

terminal (Vx)

(Volt)

Current at

Output

Terminal (µA)

Load at Out

put terminal

1 -1 30.97 10 Ω

2 -1 30.97 100 Ω

3 -1 30.97 10000 Ω

4 -1 30.97 5k Ω

5 -1 30.97 10k Ω

6 -1 30.97 20k Ω

7 -1 29.18 40k Ω

8 -1 28.14 60k Ω

9 -1 23.74 100k Ω

Table: 7.3.4 showed the variation of resistive load with out-put current.

The above table show that what the current applied at input terminal X will

be conveyed to current output terminal Z+ up to resistive load 20k Ω .

Fig: 7.3.5 Voltage at current in-put terminal when -0.725V is applied at Y.



The above figure shown that when in-put voltage at Y terminal is applied

then equal voltage will be appear at X terminal and independence the value of

current applied at X terminal. When input voltage -0.725 is applied at Y terminal

and 20 µA is applied at X terminal than the voltage appeared at X terminal is -

0.725.

Fig: 7.3.6 Current at out-put terminal Z- when 30 µA is applied at X terminal.

The above figure shown the property of current conveyor Ix =Iz-. Where Ix

is the current at input terminal X and Iz- is the current at out-put terminal Z-. The

current at input terminal is conveyed to output terminal as shown in figure. when

30 µA is applied at current input terminal X then equal current is conveyed to

out-put terminal Z- with opposite polarity as shown in the figure



Fig: 7.3.7 the leakage power consumed by Negative current conveyor.

The leakage power consumed by CMOS based positive current conveyor is

6.6mW.

Fig: 7.3.8 the variation of voltage at X terminal when sinusoidal voltage source is

applied at in-put terminal Y for negative current conveyor.



The above figure shown the property Vx =Vy for CMOS based positive

current conveyor when sinusoidal voltage source is applied at in-put terminal Y.

The same voltage will fallow by terminal X

7.4 Simulation Results of sinusoidal Oscillator using Second

generation current conveyor.

Fig.7.4.1. the sinusoidal oscillator circuit using positive. Current conveyor

Fig; 7.4.2 Sustained oscillations for sinusoidal oscillator circuit using positive

Current conveyor.



The simulation results showing growth and sustained oscillation at 200Hz

for R1=R2=R= 9.12kΩ, C1=C2=C=120pF, Rf=9.2 under the condition Rc=4.8k Ω

Fig 7.4.3 Decay of oscillations for sinusoidal oscillator circuit using positive

Current conveyor.

The Simulation results showing decay of oscillation at 200MHz for

R1=R2=R= 9.2k Ω, C1=C2=C=120pF, Rf=3.2, under the condition Rc=5.2k Ω



Chapter 8Conclusion and future work



8.1 Conclusion

The Second generation current conveyor can be divided in to two types

depending upon the direction of current flow at input current terminal and out put

current terminal. The first type is positive current conveyor in witch the direction

of current at input current terminal and out put current terminal will be same. The

second types of current conveyor is Negative current conveyor in witch the

direction of current at input current terminal and out put current terminal will be

differ.

The second-generation current conveyor (CCII) is a versatile analog

building block that presents an alternative method of implementing analog

systems which traditionally have been based on voltage op amps. Conveyor-

based implementations offer improved performance to the voltage op amp based

implementations in terms of accuracy, bandwidth, and convenience due to the

inherent local feedback of the follower based structure of the device and its very

attractive combined voltage–current capabilities.

The proposed circuit follow input-output characteristics of CCII. The output

currents (Iz+ and Iz-.) follow the input current through terminal X. Iz+ has the

same polarity as Ix for CCII+ ,and Iz- is in the opposite polarity as Ix for

CCII- .. The voltage at X follows that applied to Y, thus X exhibits zero input

impedance.

The proposed circuit of Oscillator allows independent control of the

oscillation condition and oscillation frequency. The oscillation frequency is

controlled with a single grounded resistance which in turn allows digital control



Of the frequency if weighted resistors are used.The oscillation condition

and the oscillation frequency can be adjusted independently by

two control resistors.

The proposed DDCC circuit is quite useful as a powerful building block of

current-mode circuits because of its high performances. The DDCC is useful for

processing differential voltages signals.

8.2 Future work

1. Taking the Schematic Design up to layout level:

The layout of the design must be completed, in order to

complete the whole design cycle. After doing Layout Vs

Schematic, we can say that design is ready for fabrication.

2. Improve the performance of Design:

To improve the current capability of second generation current conveyor

and the range of applied input voltage.

3. Reduce the size of proposed circuit:

Design the proposed circuit for less are but fulfil the desired requirements.

4. Reduce the power consumption of circuit:

To Design the second generation current conveyor for less power

consumption as compare to proposed circuit.

5. Implement the other analog circuit with current conveyor:



To design filter, ADC converter and other instrumentation amplifier with

the help of current conveyor and to show there application

References

1. K.C. Smith and A.S. Sidhra, “The current conveyor-a new circuit building

block,” Proc.IEEE,vol 56 pp. 1368 -1369 Aug. 1968

2. J.H.Huijsing and J.De Korte, “Monolithic nullor-a universal active

network element” IEEE Journal of Solid State Circuit, Vol. SC-12, pp.

59-64, Feb. 1977.

3. A.S.Sedra and K.C..Smith, “A second generation current conveyor and its

application,” IEEE Trans Circuit Theory,vol. CT-17,pp. 132-134,1970.

4. M.A.Lbrahim, and H.Kuntman, “A new voltage-mode KHN-BIQUAD

using differential difference current conveyor” Inter. Conf. On Electrical

and Electronics Engineering, Bursa Turkey, Dec. 3-7, 2003.

5. W.Chiu, S. I. Liu, H. W. Tsao, and J. J. Chen, “CMOS differential

difference current conveyor and their application” IEE Proc. Circuit

Device Syst, Vol. 143(2), pp.91-96, 1996.

6. U. KUMAR, “Current Conveyor: A review of state of the art, “IEEE

Circuit & syst, Mag., vol. 3, pp 10-13.1981

7. B. Wilson, “Recent developments in current conveyors and current mode

circuits,” IEE Proc., vol. 137,Pt. G ,pp 63-77,1990.

8. P. Aronhiem and M. S. Bakhtiar, “A current conveyor realization using

operational amplifier,” Int. J. Electron., vol.45.pp283-288,1978.

9. PSPICE, Microsim Corp., Laguna Hills, CA92653, U.S.A., May,1980

10. A Budak and K. Nay, “Operational amplifier circuits for the Wien-Bridge

oscillator,” IEEE Trans. Circuits. Syst., vol. CAS-28, no. 9, pp.930–934,

Sep. 1981.



11. A. Boutin, “Two-new single op-amp RC bridge-T oscillator circuits,” in

Proc. IEEE, vol. 130, Oct. 1983, pp. 222–224.

12. J. V. Vosper, “The Wien Bridge oscillator incorporating an op-amp as the

active element,” Int. J. Elect. Engg. Educ., vol. 25, pp. 125–139, 1988.

13. A. Carlosena, P. Martinez, and S. Porta, “An improved Wien bridge

oscillator,”IEEE Trans. Circuits. Syst., vol. 37, no. 4, pp. 543–546, Apr.

1990.

14. A. Rodriguez-Vazquez, J. L. Huertas, and B. Perez-Verdue, “High

frequency design of the Wien-Bridge oscillator using composite ampli-

fiers,” IEEE Trans. Circuits. Syst., vol. CAS-34, no. 4, pp. 441–443, Apr

1987.

15. S. S. Awad, “Extending the frequency range of a Wien-Bridge

oscillatorusing composite operational amplifiers,” IEEE Trans. Instrum.

Meas., vol. 38, no. 3, pp. 740–744, Jun 1989.

16. A. Carlosena, P. Martinez, and S. Porta, “Wien-Bridge oscillator with

opamp independent oscillation frequency,” IEEE Trans. Instrum. Meas.,

vol. 40, no. 3, pp. 644–646, Jun 1991.

17. “CMOS OTA-C high-frequency sinusoidal oscillators,” IEEE J. Solid-Stae

Circuits, vol. 26, no. 2, pp. 160–165, Feb. 1991.

18. S. Celma, P. A. Martinez, and A. Carlosena, “Current feedback ampli-fier-

based sinusoidal oscillators,” IEEE Trans. Circuits. Syst. I:

Fundam.Theory Applicat., vol. 41, no. 12, pp. 906–908, Dec. 1994.

19. R. Senani and V. K. Singh, “Novel single-resistance controlled-oscillator

configuration using current feedback amplifiers,” IEEE Trans. Circuits.

Syst. I: Fundam. Theory Applicat. vol. 43, no. 8, pp. 698–700, 1996.



20. R. Nandi, “Wien Bridge oscillators using current conveyors,” Proc. IEEE,

vol. 65, no. 11, pp. 1608–1609, Nov. 1977.

21. R. Nandi, “Wien Bridge oscillators using current conveyors,” Proc. IEEE,

vol. 65, no. 11, pp. 1608–1609, Nov. 1977.

22. A. A. Khan, M. A. Al-Turaigi, and M. A. El-Ela, “An improved

currentmode instrumentation amplifier with bandwidth independent of

gain,” IEEE Trans. Instrum. Meas., vol. 44, no. 4, pp. 887–891, Aug.

1995.

23. WILSON, B., LIDGEY, F.J., and TOUMAZOU, C.: ‘Current mode signal

processing circuits’. IEEE International Symposium on Circuits and

Systems, Helsinki, 1988, 3, pp. 266S2668

24. CARLIN, H.J.: ‘Singular network elements’, IEEE Trans., 1964, CT-11,

pp. 67-72

25. DOSTAL, T., and POSPfbIL; J.: ‘Current and voltage conveyors ~a family

of three port immittance convertors’. IEEE International Symposium on

Circuits and Systems, Rome, 1982, pp. 419422

26. SURAKAMPONTORN, W., and THITIMAJSHIMA, P.: ‘Integrable

electronically tunable current conveyors’, IEE Proc. G, 1988,135, (2), pp.

71-77

27. SMITH, K.C., and SEDRA, A.: ‘A new simple wide-band current

measuring device’, IEEE Trans., 1969, IM-18, pp. 125-128

28. BLACK, C.G.A., FRIEDMANN, R.T., and SEDRA, A.: ‘Gyrator

implementation with integrable current conveyors’, IEEE J., 1971,

29. RAO, M.K.N., and HASLETT, J.W.: ‘A modified current mirror with

level shifting capability and low input impedance’, IEEE J., 1979, SC-14,

pp. 762-764



30. HASLETT, J.W., and RAO, M.K.N.: ‘A high quality controlled current

source’, IEEE Trans., 1979, IM-2% pp. 132-140

31. WILSON, B.: ‘Current-mode amplifiers’. IEEE International Symposium

on Circuits and Systems, Portland, USA, 1989, 3, pp. 15761 579

32. WILSON, B.: ‘A low-distortion bipolar feedback current amplifier

technique’, IEEE Proc., 1981.69, pp. 1514-1515

33. NISHIO, M., SATO, H., and SUZUKI, T.: ‘A gyrator constructed by CCII

with variable current transfer ratio’. IEEE International Symposium on

Circuits and Systems, Kyoto, Japan, 1985, 1, pp. 93-96

34. PATRANABIS, D., TRIPATHI, M.P., and ROY, S.B.: ‘A new approach

for lossless floating inductor realisation’, IEEE Trans., 1979, CAS26, pp.

892-893



Appendix-1

Introduction to Tanner

The analog design flow using the tanner. Which include S-edit, T-spice,

W-edit. It includes all the necessary items to the process of creating a schematic,

simulating design and laving out that design. The analog design in S-edit is

simulated by using of T-spice.

Layout Tool (L-Edit) is a layout tool that uses elements drawn on layers to

represent the masks that are used to fabricate an integrated circuit. Layers are

represented by different colours and patterns. L-Edit describes a layout design in

terms of files, cells, instances, and original drawn “primitive” objects. You may

open as many files as you like within the memory constraints of your computer

system. A file may be composed of any number of cells. These cells may be

hierarchically related, as in a typical design, or they may be independent, as in a

“library” file. Cells may contain any number or combination of mask primitives

and instances of other cells. L-Edit is full-featured, high-performance, interactive,

and easy to use. It generates layouts quickly and easily, supports fully

hierarchical designs, and allows an unlimited number of layers, cells, and levels

of hierarchy. It includes all major drawing primitives and supports 90°, 45°, and

all-angle drawing modes.LVS stands for layout versus schematic. This netlist

comparison tool compares two net lists to determine whether they describe the

same circuit. When they do not, LVS works in conjunction with L-Edit to

identify and correct errors.

LVS can be used to determine whether a schematic circuit matches a

layout, or whether two different schematics or layouts implement the same

circuit. Department of Electronics and Instrumentation Engineering, SGSITS, Indore-452003 69


The tools load the user ware of this kit. The user ware is desired in a way

that enables you to use the tool efficiently. The dialog boxes give you the option

to enter the device properties in different combinations.



Appendiex-2

MOSIS PARAMETRIC TEST RESULTS

* RUN: N5BO VENDOR: HP-NI D

* TECHNOLOGY: SCN05H FEATURE SIZE: 0.5 microns

* INTRODUCTION: This report contains the lot average results obtained by

MOSIS

* From measurements of MOSIS test structures on each wafer of

* This fabrication lot. SPICE parameters obtained from similar

* Measurements on a selected wafer are also attached.

* COMMENTS: Hewlett Packard CMOS14TB.

* TRANSISTOR PARAMETERS W/L N-CHANNEL P-CHANNEL

UNITS

* MINIMUM 0.9/0.60

* Vth 0.68 -0.90 Volts

* SHORT 15/0.60

* Vth 0.61 -0.88 Volts

* Vpt 11.4 -9.4 Volts

* Vbkd 11.4 -9.5 Volts

* Idss 396 -188 uA/um

* WIDE 15/0.60

* Ids0 10.5 1.6 pA

* LARGE 5.4/5.4

* Vth 0.69 -0.95 Volts

* Vjbkd 11.5 -10.1 Volts

* Ijlk -19.2 8.1 pA

* Gamma 0.60 0.49 V^0.5

* Delta length 0.14 0.09 micronsDepartment of Electronics and Instrumentation Engineering, SGSITS, Indore-452003 71


* (L_eff = L_drawn-DL)

* Delta width 0.44 0.32 microns

* (W_eff = W_drawn-DW)

* K' (Uo*Cox/2) 72.1 -22.0 uA/V^2

* COMMENTS: Delta L varies with design technology as a result of the

different

* mask biases applied for each technology. Please adjust the delta L

* in this report to reflect the actual design technology of your submission.

* Design Technology Delta L

* ----------------- -------

* SCN_SUBM (lambda=0.3), CMOSH,

* HP_CMOS14TB no adjustment

* SCN (lambda=0.35) add 0.1 um

* FOX TRANSISTORS GATE N+ ACTIVE P+ ACTIVE UNITS

* Vth Poly >15.0 <-15.0 Volts

* PROCESS PARAMETERS N+DIFF P+DIFF POLY METAL1

METAL2 METAL3 UNITS

* Sheet Resistance 2.1 2.0 1.9 0.07 0.07 0.03 ohms/sq

* Width Variation -0.36 -0.29 -0.04 0.16 -0.04 -0.30 microns

* (measured - drawn)

* Contact Resistance 2.3 2.2 2.2 0.82 0.87 ohms

* Gate Oxide Thickness 94 angstroms

* CAPACITANCE PARAMETERS N+DIFF P+DIFF POLY METAL1

METAL2 METAL3 UNITS

* Area (substrate) 546 929 92 47 15 11 aF/um^2

* Area (poly) 59 18 11 aF/um^2

* Area (metal1) 37 14 aF/um^2Department of Electronics and Instrumentation Engineering, SGSITS, Indore-452003 72


* Area (metal2) 33 aF/um^2

* Area (N+active) 3684 aF/um^2

* Area (P+active) 3500 aF/um^2

* Fringe (substrate) 195 234 aF/um

* Fringe (N+active) 105 aF/um

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dheeraj thesis

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