development of an implantable radio identification tag for steller sea lion pups

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Development of an Implantable Radio Identification Tag For Steller Sea Lion Pups. Simon Fraser University. Hamid Meghdadi Summer 2006. Headlines. Simon Fraser University Introduction Tool and Utilities Tests and Measurements Conclusion. Simon Fraser University. - PowerPoint PPT Presentation

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  • Development of an Implantable Radio Identification Tag For Steller Sea Lion PupsHamid MeghdadiSummer 2006Simon Fraser University

  • HeadlinesSimon Fraser UniversityIntroductionTool and UtilitiesTests and MeasurementsConclusion

  • Simon Fraser UniversityLocation: Vancouver, BC, CanadaEstablished: September 1965Students: 25000Annual expenses: $300 millionSchool of engineering science:Since 1983M.Eng, M.Sc, Ph.D

  • IntroductionSteller Sea Lions:Endangered speciesUnknown mortal rateUnknown immigration patternExisting Tags:Glued: fall offLargeSurgically invasiveLimited life span

    Design an Implantable Radio Identification Tag

  • IntroductionDesign Targets:2-3 years life span (power management)IdentityBiocompatibleReport rate (1/hr)3 x 6.5 x 0.3 cmRadio tag$100

  • IntroductionBase StationTag

  • RF Identification TagsSubstrateElectronic componentsLoop antennaLoopAntennaMatchingNetworkIA4420TransceiverMSP430MicrocontrollerJTAG Interface

  • RF Identification Tags

  • Base StationFinalRobustConstructionLink budget (?)Placement(?)

    => Research

    Prototype (Test)Receive dataSave logEvaluate tags efficiencyUse available components

  • Tools and utilitiesMSP430 -ControllerIA 4420 TransceiverMSC-DKLB1 BoardStratixII FPGA BoardLabVIEW

    TI MSP430 Family:Ultra-low-power16 bit RISC CPUIntegrated peripheralsUSARTADC...Flexible clock systemInternalExternalIntegrated EPROM, RAM and Flash memories.

  • Tools and utilitiesMSP430 -ControllerIA 4420 TransceiverMSC-DKLB1 BoardStratixII FPGA BoardLabVIEW

    Integrations IA4420:Multi-channel FSK transceiverUnlicensed use in 315, 433, 868, 915 MHzLow-powerSPI InterfaceVDI, ARSSIWake-up timerInterrupts:PORWake-up timeoutTX Empty or RX Full

  • Tools and utilitiesMSP430 -ControllerIA 4420 TransceiverMSC-DKLB1 BoardStratixII FPGA BoardLabVIEW

    MSC-DKLB1 Evaluation BoardInterface between PC and IA chipSerial RS232 Interface to PCPC End utility:Any terminal simulator program (Hyper Terminal)WDS (User Friendly Interface)Capable of:Sending SPI commands to the chipDriving chip inputs high or lowMonitoring chip outputsReading RX FIFO and Status Registers

  • Tools and utilitiesMSP430 -ControllerIA 4420 TransceiverMSC-DKLB1 BoardStratixII FPGA BoardLabVIEW

    StratixII DSP Development BoardDevelopment platform for high-performance DSP designComponents:A/D and D/AVGA OutputAudio CODECRS-232 InterfaceDual 7 Segment displaySwitches and LEDs

  • Tools and utilitiesMSP430 -ControllerIA 4420 TransceiverMSC-DKLB1 BoardStratixII FPGA BoardLabVIEW

    NI LabVIEWProgramming toolG-Code basedBuilt-in functionsApplications:InstrumentationIndustrial control systems

  • Tests and MeasurementsCommunicating with IA4420DC Power RequirementsPower Consumption TestTransmission Efficiency Test 1Transmission Efficiency Test 2Bit Error Rate Test

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Transmitter Mode)FSKTwo Transmission Modes:FSK Input ActiveData at FSK input is transmittedBit rate controlled manuallyTX register not usedTX Register BufferedFSK input must be highData delivered to chip via SPI linkBit rate controlled internally

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Transmitter Mode)FSKConfiguration Setting CommandPower Management CommandData Rate CommandStatus Read Command

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Transmitter Mode)FSKConfiguration Setting CommandFrequency BandOscillator load capacitorPower Management CommandData Rate CommandStatus Read Command

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Transmitter Mode)FSKConfiguration Setting CommandPower Management CommandReceive/TransmitWake-up timerPA, XTAL, Data Rate CommandStatus Read Command

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Transmitter Mode)FSKConfiguration Setting CommandPower Management CommandData Rate CommandStatus Read Command

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Transmitter Mode)FSKInterrupt Events:TX register readyPORTX register overflowWake-up timer timeoutLow Battery Detect

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Receiver Mode)FSKTwo Reception Modes:FIFO not usedFSK: Received dataDCLK: Data clockRX FIFO not usedFIFO ModeData is stored in a 16 bit FIFOFIFO can be read by SPI linkDCLKVDIARSSI

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Receiver Mode)Interrupt Events:FIFO FullPORFIFO overflowWake-up timer timeoutLow Battery DetectFSKDCLKVDIARSSI

  • Communicating with IA4420IA4420nSELSCKSDInIRQ(Receiver Mode)Data Detection:VDIValid Data IndicatorDigital signalSlowARSSIAnalog Received Signal Strength IndicatorFastFSKDCLKVDIARSSI

  • DC Power RequirementsObjective: Determine the best supply voltage for the tagPowerSupplyTagSpectrumAnalyzerPOutIDCVDD

  • DC Power RequirementsVDD=2.2 V

  • Power Consumption TestObjective: Power consumption of tag in its different states3 Bytes3 Bytes3 Bytes2 Sec2 SecThe Tag will wake up every 2 secondsOn each wake-up event, tag will transmit 24 bitsThe current pass through the tag is measured continuously

  • Power Consumption TestMain ProgramInterrupt Service routine(Wake-up event activated)

  • Power Consumption Test1) Wake-up timer expires2) Micro reads interrupt Interrupt released3) Micro enables transmission5) PA on, transmission starts Max power (I=22 mA)6) One byte is transmitted, TX is empty7) Micro sets next byte for transmission, TX no longer empty8) Transmission finished9) Tag goes back to sleep mode

  • Transmission Efficiency Test 1Objective: Evaluate tags efficiency and reliability3 Bytes3 Bytes3 Bytes2 Sec2 SecThe Tag will wake up every 2 secondsOn each wake-up event, tag will transmit 24 bitsBase station waits for a valid packet and creates a report

  • Transmission Efficiency Test 1Programming phase:Programming tagProgramming FPGAConfiguring IA evaluation boardRunning phase:Tag transmits a packet every 2 secondsIA board receives data and provides DATA, CLK, VDIFPGA reads these lines, detects packet, Sends to PCLabVIEW reads from RS-232, saves report

  • Transmission Efficiency Test 1SearchCommunicateSearches for a packetTimer countsMax LEDData byte 7 SegmentTimer reset to zeroSend character to PC

  • Transmission Efficiency Test 1

  • Transmission Efficiency Test 1LabVIEW Program

  • Transmission Efficiency Test 1Results not very goodRange 1mEfficiency < 90%VDI too slowA better VDI is requiredVDIFPGA will not detectthis packet

  • Transmission Efficiency Test 2

  • Transmission Efficiency Test 2Final test postponedCVDI more reliableResults much betterRange 1 kmEfficiency > 95%Improvements possible

  • Bit Error Rate TestObjective: Estimate the BER of the linkTag will transmit continuouslyBase station will:Receive the dataCompare received data with expected dataCount the number of erred bitsDisplay the BER estimation on request

    One PacketThe tag will transmit this pattern:

  • Bit Error Rate TestFPGA state machine:

  • Bit Error Rate TestBit errorcalculationcircuitSevenSegmentDisplayCircuit

  • Transmission Efficiency Test 2LabVIEW Program

  • ConclusionNext steps for project:A more efficient antenna for base stationEvaluate efficiency of implanted tags when animal moves in different environmentsBattery selectionUsing an array antenna and diversity techniques in base stationCharacterize the link budget by the range and environment Personal advantages:AutonomyTelecommunications knowledgeAntenna matchingFading effectFSK mod/demBit rate & deviation vs. qualityFPGA and microprocessors knowledgeApply basic electronics theory

  • Thank you