definitive guide to the arm cortex-m3

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  • The Definitive Guide to the ARM Cortex-M3

    Second Edition

  • This page intentionally left blank

  • The Definitive Guide to the ARM Cortex-M3

    Second Edition

    Joseph Yiu

    AMSTERDAM BOSTON HEIDELBERG LONDON

    NEWYORK OXFORD PARIS SANDIEGO

    SANFRANCISCO SINGAPORE SYDNEY TOKYO

    NewnesisanimprintofElsevier

  • NewnesisanimprintofElsevier30CorporateDrive,Suite400Burlington,MA01803,USA

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  • v

    Contents

    ForewordbyPaulKimelman.................................................................................xviiForewordbyRichardYork.......................................................................................xxForewordbyWayneLyons.....................................................................................xxiPreface.................................................................................................................. xxiiiAcknowledgments................................................................................................ xxiiiConventions...........................................................................................................xxivTermsandAbbreviations........................................................................................xxv

    CHAPTER 1 Introduction .................................................................................................... 1 1.1 WhatIstheARMCortex-M3Processor?..................................................................1 1.2 BackgroundofARMandARMArchitecture.............................................................2 1.2.1ABriefHistory..................................................................................................2 1.2.2ArchitectureVersions........................................................................................3 1.2.3ProcessorNaming.............................................................................................5 1.3 InstructionSetDevelopment......................................................................................7 1.4 TheThumb-2TechnologyandInstructionSetArchitecture......................................8 1.5 Cortex-M3ProcessorApplications............................................................................9 1.6 OrganizationofThisBook.......................................................................................10 1.7 FurtherReading........................................................................................................10

    CHAPTER 2 Overview of the Cortex-M3 ............................................................................ 11 2.1 Fundamentals...........................................................................................................11 2.2 Registers...................................................................................................................12 2.2.1R0R12:General-PurposeRegisters...............................................................12 2.2.2R13:StackPointers.........................................................................................12 2.2.3R14:TheLinkRegister...................................................................................13 2.2.4R15:TheProgramCounter.............................................................................13 2.2.5SpecialRegisters.............................................................................................14 2.3 OperationModes......................................................................................................14 2.4 TheBuilt-InNestedVectoredInterruptController..................................................15 2.4.1NestedInterruptSupport.................................................................................15 2.4.2VectoredInterruptSupport..............................................................................16 2.4.3DynamicPriorityChangesSupport................................................................16 2.4.4ReductionofInterruptLatency.......................................................................16 2.4.5InterruptMasking............................................................................................16 2.5 TheMemoryMap....................................................................................................16 2.6 TheBusInterface.....................................................................................................17 2.7 TheMPU..................................................................................................................18

  • vi Contents

    2.8 TheInstructionSet...................................................................................................18 2.9 InterruptsandExceptions.........................................................................................19 2.9.1LowPowerandHighEnergyEfficiency........................................................20 2.10 DebuggingSupport..................................................................................................21 2.11 CharacteristicsSummary.........................................................................................22 2.11.1HighPerformance.........................................................................................22 2.11.2AdvancedInterrupt-HandlingFeatures.........................................................22 2.11.3LowPowerConsumption..............................................................................23 2.11.4SystemFeatures.............................................................................................23 2.11.5DebugSupports.............................................................................................23

    CHAPTER 3 Cortex-M3 Basics ......................................................................................... 25 3.1 Registers...................................................................................................................25 3.1.1GeneralPurposeRegistersR0throughR7......................................................25 3.1.2GeneralPurposeRegistersR8throughR12....................................................25 3.1.3StackPointerR13............................................................................................26 3.1.4LinkRegisterR14...........................................................................................28 3.1.5ProgramCounterR15.....................................................................................28 3.2 SpecialRegisters......................................................................................................29 3.2.1ProgramStatusRegisters................................................................................29 3.2.2PRIMASK,FAULTMASK,andBASEPRIRegisters....................................30 3.2.3TheControlRegister.......................................................................................31 3.3 OperationMode.......................................................................................................32 3.4 ExceptionsandInterrupts.........................................................................................35 3.5 VectorTables............................................................................................................36 3.6 StackMemoryOperations........................................................................................36 3.6.1BasicOperationsoftheStack.........................................................................37 3.6.2Cortex-M3StackImplementation...................................................................37 3.6.3TheTwo-StackModelintheCortex-M3........................................................39 3.7 ResetSequence.........................................................................................................40

    CH

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