Decoding double-error-correcting Reed-Solomon codes

S .T. J . Fen n M. Benaissa D.Taylor

Indexing terms: Reed-Solomon codes, Error-correctmng codes

Abstract: The decoding of double-error-correcting (DEC) Reed-Solomon (RS) codes is considered. It is shown that by modifying a well known decoding algorithm for DEC RS codes and solving the error-locator polynomial by Berlekamp’s method for solving quadratic equations, efficient hardware architectures can be derived. Furthermore, these architectures are particularly suited to implementation over the dual basis. As an example, the architecture of a (15, 11) RS codec is described. The approaches discussed here also lend themselves to the decoding of double-error-correcting/triple-error- detecting RS codes and allow for reduced decoding times compared with alternative approaches to decoding these codes.

1 introduction

Reed-Solomon (RS) error-correcting codes have been utilised in a number of applications such as the CD system [l], the Hubble space telescope [2] and the North American Advanced Train Control System (NAATCS) [3]. A subset of RS codes, double-error- correcting (DEC) codes, has received recent attention in the literature [3-61. This is because with DEC RS codes it is possible to derive particularly efficient decoding algorithms as opposed to the more computa- tionally expensive general algebraic decoding algo- rithms. In addition, DEC RS codes have been suggested as appropriate for use in computer memories [4,5] and 16-point modulation schemes [7]. Further- more, both the CD RS codec and the NAATCS RS codec implement DEC RS codes. Hence there is con- siderable motivation in producing high-speed, low- complexity DEC RS decoders.

In decoding DEC RS codes there are three main steps, the calculation of the syndromes, the calculation of the error positions and the calculation of the error magnitudes [8,9]. The calculation of the error positions frequently requires the intermediate values o n and (T to 0 IEE, 1995 IEE Proceedings online no. 19952281 Paper first received 8th September 1994 and in revised form 31st July 1995 The authors are with the Department of Electncal & Electronic Engineer- ing, The University of Huddersfield, Queensgate, Huddersfield, West Yorkshire, HDl 3DH, UK

be generated to obtain the error-locator polynomial. In general algebraic decoding schemes these values are often obtained using techniques such as the Berle- kamp-Massey algorithm or the Euclidian algorithm [8,9]. However, with DEC RS codes it is possible to obtain expressions for these values directly in terms of the syndromes [3,6], and this reduces both the time taken and the hardware required to generate them. Once these values are obtained there are a number of ways of finding the roots of the error-locator polyno- mial, such as through Chien search [IO], with look-up tables [ll], or a combination of these two methods [12]. However, by adopting Berlekamp’s method for solving quadratic equations in a finite field [8], the error-loca- tor polynomial can be solved with a simple circuit in the time taken to perform two multiplications and one division, and so the time complexity of the decoding algorithm is lower than if Chien search was used, for example.

In this paper we illustrate that by modifying the order in which the calculations are carried out the overall delay of the decoder can be reduced still fur- ther. This same approach can also be applied ta dou- ble-error-correcting/triple-error-detecting (DEC/TED) RS codes. Algorithms for decoding such codes have been presented based on calculating the weight of cer- tain syndrome vectors [4,5]. However, by utilising the above methods and calculating the determinant of a 3 x 3 matrix to test for the existence of three errors, DEC/TED RS decoders can again be designed with reduced operation times. Finally, the use of these tech- niques is illustrated in the design of a (15, 11) RS codec.

2 DECRScodes

Consider an (n, n - 4) RS code over GF (2m), where n = 2” - 1. This code can correct all code words contain- ing up to two symbol errors where each symbol com- prises m bits [8]. Let the generator polynomial g(x) of the code be given by

3 3

g(z) = IT(. - aj) = gzzz + x4 (1) 3 =O t=O

where the g, E GF (2m).

2. I Now let ~(x), C ( X ) and e(x) be the received polynomial, the code word polynomial and the error polynomial, respectively, and so these polynomials are related by the expression r(x) = c(x) + e(x). Now define the syn-

DE C RS decoding algorithm

345 IEE Proc.-Commun., Vol. 142, No. 6, December 1995

dromes by S, = ~ ( a 3 (i = 0, 1, 2, 3). Assume that two errors occur in positions il and i2 with error values Yl and Y2, respectively; then

s, = YlX1" + Yzx; (2) (j = 0, 1, 2, 3), where XI = a'' and X, = az2 are the error-location numbers. Now define the error-locator polynomial CT (x) by

where ol, oo E G F (2"), and so 0 ( 2 ) = ( 2 - X,)(lC: - X, ) = x2 + 0 1 2 + oo ( 3 )

01 = XI + X2 and 00 = X1X2 (4) It can then be shown that the values of ol (i = 0, 1) and S' ('j = 0, 1, 2, 3) are related by the equations [SI

sz = S l O l + SOOO

ss = S2O1 + S1Oo

From these we obtain

00 = (S," + S,S,)/($ + S O S 2 1

01 = (S1Sa + SOS3)/(S,2 + SOS21

Y2 = (SOX1 + S l ) / O l

Yl = s o + Y2

(5)

(6 1

(7)

( 8 )

From eqns. 2 and 4 it can be demonstrated that

and

If one error has occurred, then from eqn. 2

S,2 + SOS2 = 0

x1 = &/So Y1 = so

and the error position and magnitude are given by

The condition for no errors having occurred is S, = 0 (i = 0, 1, 2, 3).

Having generated the values of o1 and oo from eqns. 5 and 6 it remains to generate the values of Xl and X,. These values could be obtained from eqn. 3 by means of a Chien search circuit [lo]; however, a Chien search circuit for an (n, k ) RS code takes k clock cycles to yield a result, and in some cases this can prove prohib- itive. The speed of operation of a Chien search circuit can be improved by combining it with an ROM [12] or, alternatively, all the solutions of eqn. 3 can be stored in an ROM and addressed appropriately by the values of o1 and oo [ll]. In some cases, however, it may not be appropriate to use an ROM in solving the error- locator polynomial and so a different approach has to be found. In the following Section we review Berle- kamp's method for solving quadratic equations over GF (2") [8]. It is shown that this approach allows the error-locator polynomial to be solved quickly and with- out recourse to ROMs, and hence is suitable for use in DEC RS decoders.

3 Solving the error-locator polynomial

3. I equations over GF (Zm) Consider the equation

Berlekamp's method of solving quadratic

2 o(2) = 2 + 012 + 00 = 0 over GF (2"). By letting x = oly, this polynomial can be transformed into the equation

where K = oo/o:. It is known that eqn. 9 has a solution y2 + y + K 0 (9)

346

if and only if Tr(K) = 0, where Tr(x) = CTJ x21 for any x E G F (2M) [ X I . Now, let p(x ) be the defining irreduci- ble polynomial for G F (2"); let a be a root of p(x) and choose an integer value of s such that Tr(as) = 1. Then there exist yl E GF (2m) (i = 0, 1, ..., m - 1) such that

Now, let K = CT'dKiai, where Ki E G F (2), and let m-1 -

z=o

then it can be shown that TI is a solution of eqn. 9 [8]. Furthermore if the other root of o(x) is T2, then T2 = Tl + 1. We now illustrate this approach with an exam- ple over G F (24).

Assume it is required to solve the equation y2 + y + K = 0 over G F (24), where p(x) = x4 + x + 1 is the defining irreducible polynomial for the field. Then, if z = ZjL0ziai is an element of G F (24), where a is a root ofp(x), it can be shown that Tr(z) = 2 3 . Hence, taking s = 3 ensures that Tr(as) = 1. From eqn. 10 it remains to find y j E G F (Z4) (i = 0, 1, 2, 3) such that

The conditions in eqn. 11 are satisfied by yo = a5, y1 = a7, y2 = a14 and y3 = 0. Hence, if K = ZjzoKiai and Tl = Ci3=oyi(1)ai, then y3(I) = Kl + K2, y2(l) = KO, yl(') = K 0 + Kl and yo(') = Kl + K2. So, for example, consider the circuit in Fig. 1. This circuit generates the polynomial basis representation of Tl given the polynomial basis representation of K. The polynomial basis representa- tion of T2 is obtained by inverting the least significant bit of TI.

Fig. 1 Circuit for solving y2 + y + K = 0 over GF (2") "

3.2 Application to DEC RS decoders A circuit for the solution of the error location polyno- mial for DEC RS codes is shown in Fig. 2. The values of oo and o1 are obtained from eqns. 5 and 6 and the value of K = oo/of is generated. This allows the quad- ratic equation y2 + y + K = 0 to be solved with a cir- cuit of the form described in Section 3.1. This circuit generates TI and then the value XI = olTl is calculated. X2 can then be obtained easily for X , = olTz = ol(l + Tl) = o1 + XI, and so only one extra finite field adder is required. In total, therefore, this method of solving the error-locator polynomial requires two finite field multipliers, one divider, one adder and one quadratic equation solver. The time complexity of this method of solving the error-locator polynomial is therefore two multiplication cycles plus one division cycle.

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Note that the quadratic equation solver shown in Fig. 1 operates over the polynomial basis but the error- locator polynomial solver circuit shown in Fig. 2 oper- ates over the dual basis. However, if (zo, z l , z2, z3) is the polynomial basis representation of z E GF (24), then (zo, z3, z2, z l ) is the dual basis representation of z . Hence, in this instance, the required dual-to-polyno- mial basis conversion circuit is trivial to implement and needs no extra hardware. In fact, it is possible to find a dual basis which requires little or no extra hardware to be converted into the polynomial basis for all GF (2m) over which RS codes currently operate [13,14].

quadratic

solver

I I

Fig. 2 Error-locator polynomial solver for DEC RS decoders

4

The decoding algorithm reviewed in Section 3 has been used in different forms in a number of applications [3-61. It can be seen that the values of oo and ol have to be generated before the calculation of Xl and X2 can begin, and from eqns. 5 and 6 the time taken to gener- ate these values is at least one multiplication cycle plus one division cycle. However, it is possible to reduce this time complexity, as follows. For consider again eqns. 5 and 6 and let

where a0 = S22 + S1S3, al = S1S2 + SOS3 and b = S12 + SOS2. Hence 0 (x) can be expressed as

Improved DEC RS decoding algorithm

00 = ao/b 01 = a l / b

O(.) = x2 + a1z/b + ao/b

bs2 + a1z + a0 = 0 Now, from B (x) = 0 we obtain

Then, letting x = alz/b yields

where K = aob/a12. As before, if Z1 and 2, are the roots of eqn. 12, then Z2 = Z1 + 1 and so X I = alZl/b and X2 = alZ2/b. To generate the error magnitudes we observe that from eqn. 7

Z 2 f Z + K = O (12)

and then from eqn. 8

Hence, once the syndromes have been calculated, there is only a one multiplication cycle delay involved in the generation of al and a. before the calculation of Z1 and Z2 can begin.

A circuit generating 2 1 is shown in Fig. 3. Compar- ing Figs. 2 and 3 it can be seen that the solution of the error-locator polynomial through this modified method reduces the time complexity by one multiplication cycle. Having then generated Z1, the values of Yl and Y2 are obtained from eqns. 13 and 14. Note that,

Yl = s o + Y2 (14)

IEE Pvoc.-Commun., Vol. 142, No. 6, December 1995

although blal = l/ol is required to generate these error magnitudes, blal can be calculated at the same time as the division in Fig. 3 is being carried out, and so it does not add to the overall time complexity of the decoder.

OO a l - ~ ~ z l divider solver equation

b

quadratic

Fig. 3 Modified error-locator polynomial solver for DEC RS decoders

Once the error magnitudes have been obtained, the received information symbols can then start being passed out of the decoder. It only remains to determine which received symbols should have which error values added to them. This can be achieved by a comparing Xi with d (i = 1, 2) (j = 14, 13 ,... 5, 4) which in turn requires that the values of Xl and X2 be generated. To this end, note that XI = alZl /b and 2, = Z1 + 1, and so X2 = XI + allb. Again, although the value of allb = ol is required to be generated, this calculation can be car- ried out whilst the division in Fig. 3 is being carried out. In total, therefore, once the syndromes have been generated, this improved algorithm has a time com- plexity of three multiplication cycles plus one division cycle, as opposed to the time complexity of five multi- plication cycles plus two division cycles of the algo- rithm listed in Section 3.

5 (15,111 RS codec architecture

The decoding algorithm described in Section 4, together with standard, time domain encoding, has been utilised in the design of a (15, 11) RS codec. This codec operates over GF (24) and makes use of dual basis operators throughout both the encoder and the decoder. This is because hardware efficient dual basis multipliers exist in both bit-parallel and bit-serial forms [13-161 and also because division circuits exist for this basis [17]. For example, the constant multipliers in the encoder and syndrome calculators are bit-serial multi- pliers, whereas the multipliers used to generate the val- ues of al , a. and b are bit-parallel. This results in the decoder having a lower overall delay, since a bit-paral- le1 dual basis multiplier has a multiplication cycle of one clock cycle and a dual basis divider has a division cycle of m clock cycles [17]. Thus, once the 60 code word bits have been received by the decoder there is only a 3 + 4 = 7 clock cycle delay before the first cor- rected information bit is ready to be passed out of the decoder.

The overall architecture of the decoder is shown in Fig. 4. Four dual basis, constant, pipelined multipliers generate the syndrome values, which are then passed on to three product sum circuits. Given the values of a, b, c, d E GF (24), these circuits generate the value of ab + cd with bit-parallel, dual basis multipliers. The values of al, a. and b generated by these circuits are then passed on to the error-locator polynomial solver shown in Fig. 3. Simultaneously, the values of allb and blal are generated. These are required to calculate the error positions and error magnitudes, respectively. The val- ues of Yl and Y2 are then generated by circuits imple- menting eqns. 13 and 14.

347

The two error-position generation circuits each com- prise a comparator and a divide-by-a circuit, where a is a primitive element for the field. (This divide-by-a circuit is made out of four shift registers and a number of XQR gates.) These circuits are then initialised with the dual basis representation of a14 and then clocked every four clock cycles to indicate whether an error value should be added to the current information sym- bol. If only one error is present we have b = 0 and so Xi = So and Yi = Si/So Hence only an extra divider is required to carry out single error correction. This extra circuitry has not been included in Fig. 4. This (15, 11) RS codec has been implemented on a single XILINX XC3090 field programmable gate array.

data-in data-out 1 4

1 U I J

Fig.4 Architecture of (15, 11) RS decoder

6 DEC/TEC RS codes

The above techniques can also be used in the decoding of DEC/TEC RS codes. An (n, n - 5) RS code can cor- rect up to two symbol errors and also detect the pres- ence of a third symbol error. Let the generator polynomial g(x) for the code be

4 4

g(z) = r-( . -aJ) = C g t E z + Z 5

j=U z=o where the g, E GF (2m). This code therefore gives rise to five syndromes S, = r(az) (i = 0, 1, 2, 3, 4). To test for the existence of three symbol errors, the value of

D = sos2s4 + sos,2 + SfS4 + s; is generated. If D # 0 then three errors are assumed to have occurred [ll]. Alternatively, if one or two symbol corrections are being carried out the methods described in Section 5 are followed, and the value of S, is not used in the decoding process. This value of D can be generated in two clock cycles if bit-parallel multipliers are adopted and so does not add to the overall time delay of the decoder.

Approaches for decoding DEC/TEC RS codes based on calculating the Hamming weights of syndrome vec- tors have previously been presented [4,5]. However, these methods require a second set of syndromes to be calculated from the generated error polynomial and then compared with the original syndromes. This method considerably adds to the time complexity of the decoder with no hardware savings over the above approach.

7 Conclusions

In this paper an improved algorithm for decoding RS

codes has been presented. With the addition of no extra hardware the delay of the decoder has been reduced to m + 3 clock cycles once the syndromes have been calculated. An integral component of this decoder is the error-locator polynomial solver. This module uti- lises Berlekamp’s method of solving quadratic equa- tions over a finite field and is particularly suited to the high-speed decoding algorithm presented here. The described methods also apply to DEC/TEC RS codes; all that is further required is the basic circuitry to detect the presence of three errors. An important fea- ture of the illustrated architecture is that it functions over the dual basis, allowing for particularly hardware efficient arithmetic operators to be adopted. However, the decoding time complexity would also be the same if normal basis operators were used [18], although the hardware requirements of the codec would be signifi- cantly larger [14,16]. The motivation behind the work presented in this paper has been to reduce the time Complexity and hardware requirements of DEC RS codecs. Through achieving this, DEC RS codecs can be fitted on to single ASICS and utilised in real-time sys- tems.

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