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DDR3 SDRAMFrom Wikipedia, the free encyclopedia

In computing, DDR3 SDRAM or double-data-rate three SDRAM is a modern kind of dynamicrandom access memory with a high bandwidth interface. It is one of several variants of dynamic RAMand/or associated interface techniques that have been used since the early 1970s, and it is not directlycompatible with any of the earlier types, not even with DDR2 SDRAM. This is due to different signalingvoltages, timings, and other factors.

DDR3 is a DRAM interface specification; the actual DRAM arrays that store the data are similar toearlier types, with similar performance.

The primary benefit of DDR3 SDRAM over its predecessor, DDR2 SDRAM, is the ability to transfer attwice the data rate (8× the speed of its internal memory arrays), enabling higher bandwidth or peak datarates. In addition, the DDR3 standard allows for chip capacities of up to 8 gigabits, thus enabling amemory module size of 16 gigabytes (using 16 chips).

With two transfers per cycle of a quadrupled clock, a 64-bit wide DDR3 module may achieve a transferrate of up to 64 times the memory clock in MB/s.

Contents

1 Overview1.1 Latencies

2 Extensions3 Modules

3.1 JEDEC standard modules

4 Feature summary5 Market penetration6 Successor7 See also8 References

Overview

DDR3 memory provides a reduction in power consumption of30% compared to DDR2 modules due to DDR3's 1.5 V supplyvoltage, compared to DDR2's 1.8 V or DDR's 2.5 V. The 1.5 Vsupply voltage works well with the 90 nanometer fabricationtechnology used in the original DDR3 chips. Some manufacturersfurther propose using "dual-gate" transistors to reduce leakage ofcurrent.[1]

According to JEDEC[2] the maximum recommended voltage is1.575 volts and should be considered the absolute maximumwhen memory stability is the foremost consideration, such as inservers or other mission critical devices. In addition, JEDECstates that memory modules must withstand up to 1.975 voltsbefore incurring permanent damage, although they are notrequired to function correctly at that level.

DDR3L standard for low voltage DDR3 memory introduced byJEDEC, such as DDR3L‐800, DDR3L‐1066, DDR3L‐1333,DDR3L‐1600. DDR3L operated with default voltage 1.35 V. It basically uses up at least 15% less powerthan DDR3 and 40% compared to DDR2. Modules with DDR3L labeled ’’PC3L’’.

The main benefit of DDR3 comes from the higher bandwidth made possible by DDR3's 8-burst-deepprefetch buffer, in contrast to DDR2's 4-burst-deep or DDR's 2-burst-deep prefetch buffer.

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DDR3 modules can transfer data at a rate of 800–2133 MT/s using both rising and falling edges of a400–1066 MHz I/O clock. Sometimes, a vendor may misleadingly advertise the I/O clock rate bylabeling the MT/s as MHz. The MT/s is normally twice that of MHz by double sampling, one on therising clock edge, and the other, on the falling. In comparison, DDR2's current range of data transferrates is 400–1066 MT/s using a 200–533 MHz I/O clock, and DDR's range is 200–400 MT/s based on a100–200 MHz I/O clock. High-performance graphics was an initial driver of such bandwidthrequirements, where high bandwidth data transfer between framebuffers is required.

DDR3 does use the same electric signaling standard as DDR and DDR2, Stub Series Terminated Logic,albeit at different timings and voltages. Specifficaly DDR3 uses SSTL_15.[3].

DDR3 prototypes were announced in early 2005. Products in the form of motherboards appeared on themarket in June 2007[4] based on Intel's P35 "Bearlake" chipset with DIMMs at bandwidths up toDDR3-1600 (PC3-12800).[5] The Intel Core i7, released in November 2008, connects directly tomemory rather than via a chipset. The Core i7 supports only DDR3. AMD's first socket AM3 Phenom IIX4 processors, released in February 2009, were their first to support DDR3.

DDR3 DIMMs have 240 pins, are electrically incompatible with DDR2 and have a different key notchlocation.[6] DDR3 SO-DIMMs have 204 pins.[7]

GDDR3 memory, having a similar name but being from an entirely dissimilar technology, has been in usefor graphic cards. GDDR3 has sometimes been incorrectly referred to as "DDR3".

Latencies

While the typical latencies for a JEDEC DDR2 device were 5-5-5-15, some standard latencies forJEDEC DDR3 devices include 7-7-7-20 for DDR3-1066 and 8-8-8-24 for DDR3-1333.

DDR3 latencies are numerically higher because the I/O bus clock cycles by which they are measured areshorter; the actual time interval is similar to DDR2 latencies (around 10 ns). There is some improvementbecause DDR3 generally uses more recent manufacturing processes, but this is not directly caused by thechange to DDR3.

As with earlier memory generations, faster DDR3 memory became available after the release of theinitial versions. DDR3-2000 memory with 9-9-9-28 latency (9 ns) was available in time to coincide withthe Intel Core i7 release.[8] CAS latency of 9 at 1000 MHz (DDR3-2000) is 9 ns, while CAS latency of 7at 667 MHz (DDR3-1333) is 10.5 ns.

(CAS / Frequency (MHz)) × 1000 = X ns

Example:

(7 / 667) × 1000 = 10.4948 ns

Extensions

Intel Corporation officially introduced the eXtreme Memory Profile (XMP) Specification on March 23,2007 to enable enthusiast performance extensions to the traditional JEDEC SPD specifications forDDR3 SDRAM.[9]

Modules

JEDEC standard modules

Standardname

Memoryclock

(MHz)

Cycletime

(ns)

I/O busclock

(MHz)

Datarate

(MT/s)

Modulename

Peaktransfer

rate

(MB/s)

Timings

(CL-tRCD-tRP)

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DDR3-800DDDR3-800E 100 10 400 800 PC3-6400 6400 5-5-5

6-6-6DDR3-1066EDDR3-1066FDDR3-1066G

133 71/2 533 1066 PC3-8500 85336-6-67-7-78-8-8

DDR3-1333F*DDR3-1333GDDR3-1333HDDR3-1333J*

166 6 667 1333 PC3-10600 10667

7-7-78-8-89-9-9

10-10-10DDR3-1600G*DDR3-1600HDDR3-1600JDDR3-1600K

200 5 800 1600 PC3-12800 12800

8-8-89-9-9

10-10-1011-11-11

DDR3-1866J*DDR3-1866KDDR3-1866L

DDR3-1866M*

233 42/7 933 1866 PC3-14900 14933

10-10-1011-11-1112-12-1213-13-13

DDR3-2133K*DDR3-2133LDDR3-2133MDDR3-2133N*

266 33/4 1066 2133 PC3-17000 17066

11-11-1112-12-1213-13-1314-14-14

CL - Clock cycles between sending a column address to the memory and the beginning of the data inresponse

tRCD - Clock cycles between row activate and reads/writes

tRP - Clock cycles between row precharge and activate

* optional

Note: All above listed are specified by JEDEC as JESD79-3D.[10] All RAM data rates in-between orabove these listed specifications are not standardized by JEDEC—often they are simply manufactureroptimizations using higher-tolerance or overvolted chips. Of these non-standard specifications, thehighest reported speed reached was equivalent to DDR3-2544 as of May 2010.[11]

DDR3-xxx denotes data transfer rate, and describes raw DDR chips, whereas PC3-xxxx denotestheoretical bandwidth (with the last two digits truncated), and is used to describe assembled DIMMs.Bandwidth is calculated by taking transfers per second and multiplying by eight. This is because DDR3memory modules transfer data on a bus that is 64 data bits wide, and since a byte comprises 8 bits, thisequates to 8 bytes of data per transfer.

In addition to bandwidth and capacity variants, modules can

Optionally implement ECC, which is an extra data byte lane used for correcting minor errors anddetecting major errors for better reliability. Modules with ECC are identified by an additionalECC or E in their designation. For example: "PC3-6400 ECC", or PC3-8500E.[12]

1.

Be "registered", which improves signal integrity (and hence potentially clock rates and physicalslot capacity) by electrically buffering the signals with a register, at a cost of an extra clock ofincreased latency. Those modules are identified by an additional R in their designation, whereasnon-registered (a.k.a. "unbuffered") RAM may be identified by an additional U in the designation.PC3-6400R is a registered PC3-6400 module, PC3-6400R ECC is the same module but withadditional ECC.

2.

Be fully buffered modules, which are designated by F or FB and do not have the same notchposition as other classes. Fully buffered modules cannot be used with motherboards that are madefor registered modules, and the different notch position physically prevents their insertion.

3.

Feature summary

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DDR3 SDRAM components

Introduction of asynchronous RESET pinSupport of system-level flight-time compensationOn-DIMM mirror-friendly DRAM pinoutIntroduction of CWL (CAS write latency) per clock binOn-die I/O calibration engineREAD and WRITE calibration

DDR3 modules

Fly-by command/address/control bus with on-DIMM terminationHigh-precision calibration resistorsAre not backwards compatible—DDR3 modules do not fit into DDR2 sockets; forcing them candamage the DIMM and/or the motherboard[13]

Technological advantages compared to DDR2

Higher bandwidth performance, up to 2133 MT/s standardizedSlightly improved latencies as measured in nanosecondsHigher performance at low power (longer battery life in laptops)Enhanced low-power features

Market penetration

Although DDR3 was launched in 2007, DDR3 sales were not expected to overtake DDR2 until the endof 2009, or possibly early 2010, according to Intel strategist Carlos Weissenberg, speaking during theearly part of their roll-out in August 2008[14] (the same view had been stated by market intelligencecompany DRAMeXchange over a year earlier in April 2007.[15]) The primary driving force behind theincreased usage of DDR3 has been new Core i7 processors from Intel and Phenom II processors fromAMD, both of which have internal memory controllers: the latter recommends DDR3, the formerrequires it. IDC stated in January 2009 that DDR3 sales will account for 29 percent of the total DRAMunits sold in 2009, rising to 72% by 2011.[16]

Successor

Main article: DDR4 SDRAM

It was revealed at the Intel Developer Forum in San Francisco 2008 that the successor to DDR3 will beknown as DDR4. It is currently in the design stage, and is expected to be released in 2015.[17] Whenreleased, it is expected to run at 1.2 volts or less,[18][19] versus the 1.5 volts of DDR3 chips and have inexcess of 2 billion data transfers per second.

See also

Dual-channel architectureTriple-channel architectureList of device bandwidths

References^ McCloskey., Alan. "Research: DDR FAQ" (http://www.ocmodshop.com/ocmodshop.aspx?a=868) .http://www.ocmodshop.com/ocmodshop.aspx?a=868. Retrieved 2007-10-18.

1.

^ JEDEC JESD 79-3B (http://www.jedec.org/download/search/JESD79-3B.pdf) (section 6, table 21 andsection 7, table 23)

2.

^ Jaci Chang Design Considerations for the DDR3 Memory Sub-system. Jedex, 2004, p. 4.http://www.jedex.org/images/pdf/samsung%20-%20jaci_chang.pdf

3.

^ Soderstrom, Thomas (2007-06-05). "Pipe Dreams: Six P35-DDR3 Motherboards Compared"(http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/) . Tom'sHardware. http://www.tomshardware.com/2007/06/05/pipe_dreams_six_p35-ddr3_motherboards_compared/.

4.

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^ Fink, Wesley (2007-07-20). "Super Talent & TEAM: DDR3-1600 Is Here!" (http://www.anandtech.com/printarticle.aspx?i=3045) . AnandTech. http://www.anandtech.com/printarticle.aspx?i=3045.

5.

^ "DocMemory" (2007-02-21). "Memory Module Picture 2007" (http://www.simmtester.com/page/news/showpubnews.asp?title=Memory+Module+Picture+2007&num=150) . http://www.simmtester.com/page/news/showpubnews.asp?title=Memory+Module+Picture+2007&num=150.

6.

^ "JEDEC" (2010-12-01). "204-Pin DDR3 SDRAM SO-DIMM Specification" (http://www.jedec.org/download/search/4_20_18R20A.pdf) . http://www.jedec.org/download/search/4_20_18R20A.pdf.

7.

^ Shilov, Anton (2008-10-29). "Kingston Rolls Out Industry’s First 2GHz Memory Modules for Intel Corei7 Platforms" (http://www.xbitlabs.com/news/memory/display/20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms.html) . Xbit Laboratories. http://www.xbitlabs.com/news/memory/display/20081029141143_Kingston_Rolls_Out_Industry_s_First_2GHz_Memory_Modules_for_Intel_Core_i7_Platforms.html. Retrieved 2008-11-02.

8.

^ "Intel Extreme memory Profile (Intel XMP) DDR3 Technology" (http://www.intel.com/assets/pdf/whitepaper/319124.pdf) . http://www.intel.com/assets/pdf/whitepaper/319124.pdf. Retrieved2009-05-29.

9.

^ DDR3 SDRAM STANDARD (http://www.jedec.org/standards-documents/docs/jesd-79-3d)10.^ Kingston's 2,544 MHz DDR3 On Show at Computex (http://news.softpedia.com/news/Kingston-s-2-544-MHz-DDR3-On-Show-at-Computex-143379.shtml)

11.

^ Memory technology evolution: an overview of system memory technologies(http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf) (PDF), Hewlett-Packard, p. 18, http://h20000.www2.hp.com/bc/docs/support/SupportManual/c00256987/c00256987.pdf

12.

^ "DDR3: Frequently Asked Questions" (http://www.kingston.com/channelmarketingcenter/hyperx/literature/MKF_1223_DDR3_FAQ.pdf) . http://www.kingston.com/channelmarketingcenter/hyperx/literature/MKF_1223_DDR3_FAQ.pdf. Retrieved 2009-08-18.

13.

^ "IDF: "DDR3 won't catch up with DDR2 during 2009"" (http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html) . pcpro.co.uk. 19 August 2008. http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html. Retrieved 2009-06-17.

14.

^ Bryan, Gardiner (April 17, 2007). "DDR3 Memory Won't Be Mainstream Until 2009"(http://www.extremetech.com/article2/0,2845,2115031,00.asp) . extremetech.com.http://www.extremetech.com/article2/0,2845,2115031,00.asp. Retrieved 2009-06-17.

15.

^ Salisbury, Andy (2009-01-20). "New 50nm Process Will Make DDR3 Faster and Cheaper This Year"(http://www.maximumpc.com/article/news/new_50nm_process_will_make_ddr3_faster_and_cheaper_this_year) . maximumpc.com.http://www.maximumpc.com/article/news/new_50nm_process_will_make_ddr3_faster_and_cheaper_this_year. Retrieved 2009-06-17.

16.

^ http://www.semiaccurate.com/2010/08/16/ddr4-not-expected-until-2015/17.^ Looking forward to DDR4 (http://www.pcpro.co.uk/news/220257/idf-ddr3-wont-catch-up-with-ddr2-during-2009.html)

18.

^ DDR3 successor (http://www.heise-online.co.uk/news/IDF-DDR4-the-successor-to-DDR3-memory--/111367)

19.

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