DDR2/DDR3 SDRAMController

Programmable support for DDR2 and DDR3 SDRAM.Pipeline access allows con-tinuous data bursting and hidden command execution.Page hit detection supports fast column access and mul-tiple open banks.High speed implementation with standard DFI support for hard DDR PHY.Optional built-in soft PHY for low cost implementation.Extensive general purpose registers for PHY support and calibration. Numerous optional features such as multiple access ports, AHB, AXI, and generic user interface, ECC, and others.User controlled read and write latency.On-die termination (ODT) and Off-Chip Driver impedance adjustment (OCD) supports.Programmable access timing parameters and configura-tions.Automatic refresh generation with programmable refresh intervals.Self-refresh mode to reduce system power consumption.

The EP538 DDR SDRAM Controller supports both DDR2 and DDR3 SDRAM devices. It is an interface between multiple DDR2 or DDR3 SDRAM devices and memory requestor such as processor or DMA controller. The SDRAM Controller allows the user logic to simply reads from or writes to the memory with simple bus request or standard AHB or AXI bus request, without having to be concerned about specific SDRAM control and timing issues. The controller hides the complicated SDRAM behavior and taking advantage of the access charac-teristics of DDR2 and DDR3 SDRAMs to sustain high band-width.

The high speed nature of DDR SDRAM creates very tight timing requirements for data transfer. The SDRAM controller core supports the standard DFI interface for hardware DDR PHY modules to handle physical data transfer.

The SDRAM controller uses multiple schemes to maximize system bandwidth. It automatically keeps track of multiple open pages in the SDRAM and uses CAS only access when possible. The pipeline feature allows the controller to com-pletely hides command execution time and deliver data con-tinuously to the requestor with no interruption.

Configurations

FEATURES

OtherInterface

OtherInterface

UserInterface

Soft PHY orHard PHY

SDRAMControllerArbiter

ControlRegisters

ECC

DDR2/3SDRAM

DDR2/3SDRAM

DDR2/3SDRAM

DDR2/3SDRAM

DDR2/3SDRAM

DDR2/3SDRAM

DDR2/3SDRAM

DDR2/3SDRAM

DDR2/DDR3 SDRAMController

Many optional features to choose from to suit each applica-tion requirement.Available as single port and multiple port SDRAM controller with arbitration scheme include bandwidth guarantee.Supports standard CPU interface such as AHB and AXI.Separate clock domain for user interface and SDRAM clock.Optional Error Correction Code (ECC) support.

Other IP Cores

Verilog or VHDL RTL codeSupports built-in soft PHY and external ASIC hard PHY such DFI standard PHY.Source code license includes test bench and simulation models.Synthesis scriptTop level design templateDocumentation

NAND Flash Controller

DMA Controller

AHB/AXI Bus Interface

SD/MMC Host

SD Development Kit

PCI Bridge

PCMCIA/CompatFlash

PowerPC Bus Interface

PCI Express

SD/MMC Slave

Deliverable

Flexibility

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Silicon proven with over 12 years of track recordsSource code and development kit availableSimple licensing methodCustomization available