A

PRACTICAL FILE

on

G.G.S.I.P.U

NORTHERN INDIA ENGINEERING COLLEGE

Submitted To: Submitted By:

Ms. Lilly Gupta Yogesh Kumar

00915607210

CSE (T2) 3rd year

INTRODUCTION TO VHDL

VHDL is an acronym which stands for VHSIC Hardware Description Language. VHSIC is yet another acronym which stands for Very High Speed Integrated Circuits.

VHDL offers the following advantages for the digital design:-

Standard: VHDL is an IEEE standard. Just like any standard it reduces confusion and makes interface easier.

Support from Industry: With the advent of more powerful and efficient VHDL tools, it has gained more support from the electronic industry.

Modeling Capability: VHDL was developed to model all levels of design. VHDL can accommodate behavioral constructs and mathematical routines that describe the complex models.

Reusability: changing the value of the parameters can reuse generic codes written in VHDL.

WHAT IS LOGIC SYNTHESIS?

Logic synthesis is the process of taking a form of input (VHDL), translating it into form and then optimizing in terms of propagation delay or area. Once the VHDL code is translated into an internal form, the optimization process can be performed based on the nature of constraints such as speed, area, power and So on.

VHDL TERMS :-

Before we go further, let’s define some of the terms that we will be using throughout the file. There are some basic VHDL building blocks that are used in almost every description.

1) Entity: All designs are expressed in terms of entities. An entity is the most basic Building block in a design.

2) Architecture: All entities that can be simulated have an architecture description. The architecture describes the behaviour of the entity.

3) Configuration: A configuration statement is used to bind a component instance to anentity-architecture pair. A configuration can be considered like a part list for a design. It describes which behaviour to use for each entity.

4) Package: A Package is a collection of commonly used data types and subprogram used in a design.

5) Bus: The term bus usually brings to mind a group of signals or a particular

method of communication used in the design of hardware.

6) Driver: This is a source on a signal. If a signal is driven by two tristate inverters,

when both inverters are active, the signal will have two drivers.

7) Process: A Process is the basic unit of execution in VHDL. All operations that are

performed in a simulation of a VHDL description are broken into single or multiple

processes.

8) Generic: A Generic is a VHDL’s term for a parameter that passes information to an entity. For instance, if an entity is a gate level model with a rise and fall delay, values for the rise and fall delays could be passed into the entity with the generics.

EXPERIMENT-1

AIM:

To design and verify all basic gates using VHDL.

THEORY:

First, VHDL code for basic gates was written and block was generated. Code for basic gates is written. The logic function can be realized using only basic gates.

Logic gates :

Digital systems are said to be constructed by using logic gates. These gates are the AND, OR, NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the aid of truth tables.

AND gate:

The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high.  A dot (.) is used to show the AND operation i.e. A.B.  Bear in mind that this dot is sometimes omitted i.e. AB

 

OR gate:

The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are high.  A plus (+) is used to show the OR operation.

 

NOT gate :

The NOT gate is an electronic circuit that produces an inverted version of the input at its output.  It is also known as an inverter.  If the input variable is A, the inverted output is known as NOT A.  This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams below show two ways that the NAND logic gate can be configured to produce a NOT gate. It can also be done using NOR logic gates in the same way.

 

NAND gate:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate.  The outputs of all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small circle on the output. The small circle represents inversion.

 

NOR gate:

This is a NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates are low if any of the inputs are high.

The symbol is an OR gate with a small circle on the output. The small circle represents inversion.

 

EXOR gate :

The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two inputs are high.  An encircled plus sign ( ) is used to show the EOR operation.

EXNOR gate :

The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on the output. The small circle represents inversion.

The NAND and NOR gates are called universal functions since with either one the AND and OR functions and NOT can be generated.

Note:

A function in sum of products form can be implemented using NAND gates by replacing all AND and OR gates by NAND gates.

A function in product of sums form can be implemented using NOR gates by replacing all AND and OR gates by NOR gates.

VHDL code of Basic Gates :

libraryieee;

use ieee.std_logic_1164.all;

entitycheckgates is

port(a,b:instd_logic;

c,d,e,f,g,h,i: out std_logic);

endcheckgates;

architecturear_checkgates of checkgates is

begin

c<=( a and b);

d<=( a or b);

e<=( not a);

f<=( a nor b);

g<=( a nand b);

h<=( a xor b);

i<=(not (a xor b));

endar_checkgates;

RTL VIEW:

SIMULAION WAVEFORM:

CONCLUSION :

1. Truth table for all the basic gates are verified from output waveform.

2. RTL viewer of different basic gates are obtained.

EXPERIMENT 2

AIM:

To design a half adder using Structural modelling.

THEORY:

First, VHDL code for half adder was written and block was generated. Half

adder block as component and basic gates, code for half adder is written. The truthtables are as follows:

HALF ADDER:

Sum = A XOR B ; CARRY = A AND B;

VHDL code of Half Adder :

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity HA is

port(A,B:in STD_LOGIC; Sum, Carry:out STD_LOGIC);

end HA;

architecturestruct of HA is

componentmyXOR

port(in1,in2:in STD_LOGIC; out1:out STD_LOGIC);

end component;

begin

X1: myXOR port map(A,B,Sum);

Carry<=A and B;

endstruct;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSION:

1. Truth table for all the models of half adder is verified from output

waveform.

2. RTL of different models half adder and full adder are obtained.

EXPERIMENT-3

AIM:

To design a full adder using data flow modelling.

THEORY:

First, VHDL code for full adder was written and block was generated. Half

adder block as component and basic gates, code for full adder is written. The truth

tables are as follows:

FULL ADDER:

SUM = A XOR B XOR C; CARRY = AB + AC + BC;

VHDL code of Full Adder:

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity FA_DF is

port(Fx, Fy, Fcin : in BIT; Fs, Fcout : out BIT);

end FA_DF;

architectureFA_dataflow of FA_DF is

begin

Fs<= Fx XOR Fy XOR Fcin;

Fcout<= (Fx AND Fy) OR (Fx AND Fcin) OR (Fy AND Fcin);

endFA_dataflow;

RTL VIEW:

SIMULATION WAVEFORM:

CONCLUSION:

1. Truth table for all the models of full adder are verified from output waveform.

2. RTL of different models full adder are obtained.

EXPERIMENT-4AIM:To design JK flip flop using select statement and case statement.

THEORY:

There are three operations that can be performed with a flip-flop: set it to 1, reset it to 0, or

complement its output. The JK flip-flop performs all three operations. The J input set the flipflopto 1, the K input resets it to 0, and when both inputs are enabled, the output is

complemented. This can be verified by investigating the circuit applied to the D input:

D = JQ’ + K’Q

When J = 1 and K = 0, D = Q’ + Q = 1, so the next clock edge sets the output to 1. When J =

0 and K = 0, so the next clock edge resets the output to 0. When J = K = 1, D = Q’, the next

clock edge complements the output. When both J = K = 0, D = Q, the clock edge leaves the

output unchanged. The truth table for jk flip-flop are as follows:

(a) Logic diagram

(b) Graphical symbol

(c) Transition table

VHDL CODE FOR JK FLIP-FLOP:

libraryieee;

use ieee.std_logic_1164.all;

entityjkff is

port(clock, j, k,reset: in BIT;

Q, Qbar: buffer BIT);

endjkff;

architecturebehv of jkff is

-- define the useful signals here

signal state: std_logic;

signal input: std_logic_vector(1 downto 0);

begin

-- combine inputs into vector

input<= J & K;

p: process(clock, reset) is

begin

if (reset='1') then

state<= '0';

elsif (rising_edge(clock)) then

-- compare to the truth table

case (input) is

when "11" =>

state<= not state;

when "10" =>

state<= '1';

when "01" =>

state<= '0';

when others =>

null;

end case;

end if;

end process;

-- concurrent statements

Q <= state;

Qbar<= not state;

endbehv;

RTL VIEW:

SIMULATION WAVEFORM:

Conclusion:

1.The truth table for JK flip-flop is verified.

2.The RTL was obtained .

EXPERIMENT-5

AIM:

To design 4:1 multiplexer.

THEORY:

A multiplexers is a combinational circuit has selects binary informational from one of many

input lines and directs it to a single output line. The selection of a particular input line is

controlled by a set of selection lines. Normally, there are 2n input lines and n selection lines

whose bit combinations determine which input is selected. The truth table for 4x1 multiplexer

are as follows:

Truth Table for 4:1 Mux

Block Diagram 4:1 Mux

VHDL CODE FOR MULIPLEXER USING WITH SELECT

STATEMENT:

use IEEE.std_logic_1164.all;

library IEEE;

entity mux41v2 is

port(

d0 : in std_logic;

d1 : in std_logic;

d2 : in std_logic;

d3 : in std_logic;

s : in std_logic_vector(1 downto 0);

y : out std_logic

);

end mux41v2;

architecture arch1 of mux41v2 is

begin

with s select

y <= d0 when "00",

d1 when "01",

d2 when "10",

d3 when "11";

end arch1;

VHDL CODE FOR MULIPLEXER USING CASE STATEMENT :

library IEEE;

use IEEE.std_logic_1164.all;

entitymux_logic is

port(A,B,C,D:instd_logic;

ctrl:instd_logic_vector(0 to 1);

z:out std_logic);

endmux_logic;

architecture mux_1 of mux_logic is

constantmux_delay:time:=10 ns;

begin

pmux:process(A,B,C,D,ctrl)

variabletemp:std_logic;

begin

case ctrl is

when "00"=>temp:=A;

when "01"=>temp:=B;

when "10"=>temp:=C;

when "11"=>temp:=D;

when others=>temp:=A;

end case;

z<=temp after mux_delay;

end process pmux;

end mux_1;

VHDL CODE FOR MULIPLEXER USING IF-ELSE STATEMENT :

library IEEE;

use IEEE.std_logic_1164.all;

entity mux2 is

port(A,B,C,D:instd_logic;

ctrl:instd_logic_vector(0 to 1);

z:out std_logic);

end mux2;

architecturemux_logic of mux2 is

begin

p1:process(A,B,C,D,ctrl)

variabletemp:std_logic;

begin

if ctrl="00" then temp:=A;

elsif ctrl="01" then temp:=B;

elsif ctrl="10" then temp:=C;

elsif ctrl="11" then temp:=D;

else temp:='0';

end if;

z<=temp;

end process;

endmux_logic;

RTL VIEW:

SIMULATION WAVEFORM:

Conclusions:

1.4X1 multiplexer was realized using behavioral model as the architecture.

2. The 4X1 multiplexer verified for various combination of inputs.

EXPERIMENT-6

AIM:

To design priority encoder.

THEORY:

A priority encoder is an encoder that includes the priority functions.the operation of the

priority encoder is such that if two or more inputsare equal to 1 at the same time,the inputs

having the highest priority will take precedence.the truth table of a four-input priority encoder

are as follows:

VHDL CODE FOR PRIORITY ENCODER USING CASE,IF-ELSE

STATEMENT:

libraryieee;

use ieee.std_logic_1164.all;

entitypri_encoder_using_if is

port (

enable :in std_logic; -- Enable for the encoder

encoder_in :instd_logic_vector (15 downto 0);-- 16-bit Input

binary_out :outstd_logic_vector (3 downto 0) -- 4 bit binary Output

);

end entity;

architecturebehavior of pri_encoder_using_if is

begin

process (enable, encoder_in) begin

binary_out<= "0000";

if (enable = '1') then

if (encoder_in = "XXXXXXXXXXXXXX10") then

binary_out<= "0001";

elsif (encoder_in = "XXXXXXXXXXXXX100") then

binary_out<= "0010";

elsif (encoder_in = "XXXXXXXXXXXX1000") then

binary_out<= "0011";

elsif (encoder_in = "XXXXXXXXXXX10000") then

binary_out<= "0100";

elsif (encoder_in = "XXXXXXXXXX100000") then

binary_out<= "0101";

elsif (encoder_in = "XXXXXXXXX1000000") then

binary_out<= "0110";

elsif (encoder_in = "XXXXXXXX10000000") then

binary_out<= "0111";

elsif (encoder_in = "XXXXXXX100000000") then

binary_out<= "1000";

elsif (encoder_in = "XXXXXX1000000000") then

binary_out<= "1001";

elsif (encoder_in = "XXXXX10000000000") then

binary_out<= "1010";

elsif (encoder_in = "XXXX100000000000") then

binary_out<= "1011";

elsif (encoder_in = "XXX1000000000000") then

binary_out<= "1100";

elsif (encoder_in = "XX10000000000000") then

binary_out<= "1101";

elsif (encoder_in = "X100000000000000") then

binary_out<= "1110";

else

binary_out<= "1111";

end if;

end if;

end process;

end architecture;

VHDL CODE FOR PRIORITY ENCODER USING WHEN ELSE

STATEMENT:

libraryieee;

use ieee.std_logic_1164.all;

entitypri_encoder_using_when is

port (

enable :in std_logic; -- Enable for the encoder

encoder_in :instd_logic_vector (15 downto 0);-- 16-bit Input

binary_out :outstd_logic_vector (3 downto 0) -- 4 bit binary Output

);

end entity;

architecturebehavior of pri_encoder_using_when is

begin

binary_out<= "0000" when (enable = '0') else

"0000" when (encoder_in = "XXXXXXXXXXXXXXX1") else

"0001" when (encoder_in = "XXXXXXXXXXXXXX10") else

"0010" when (encoder_in = "XXXXXXXXXXXXX100") else

"0011" when (encoder_in = "XXXXXXXXXXXX1000") else

"0100" when (encoder_in = "XXXXXXXXXXX10000") else

"0101" when (encoder_in = "XXXXXXXXXX100000") else

"0110" when (encoder_in = "XXXXXXXXX1000000") else

"0111" when (encoder_in = "XXXXXXXX10000000") else

"1000" when (encoder_in = "XXXXXXX100000000") else

"1001" when (encoder_in = "XXXXXX1000000000") else

"1010" when (encoder_in = "XXXXX10000000000") else

"1011" when (encoder_in = "XXXX100000000000") else

"1100" when (encoder_in = "XXX1000000000000") else

"1101" when (encoder_in = "XX10000000000000") else

"1110" when (encoder_in = "X100000000000000") else

"1111";

end architecture;

RTL VIEW:

SIMULATION WAVEFORM:

Conclusions:

1.Priority Encoder was realized using behavioral model as the architecture.

2. The Priority Encoder verified using simulation waveform.