datasheet - stm32f303xb stm32f303xc - arm®-based cortex ... · arm ®-based cortex®-m4 32b...
TRANSCRIPT
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This is information on a product in full production.
March 2019 DS9911 Rev 9 1/145
STM32F302xB STM32F302xC
Arm®-based Cortex®-M4 32b MCU+FPU, up to 256KB Flash+ 40KB SRAM, 2 ADCs, 1 DAC ch., 4 comp, 2 PGA, timers, 2.0-3.6 V
Datasheet - production data
Features• Core: Arm® Cortex®-M4 32-bit CPU with FPU
(72 MHz max), single-cycle multiplication and HW division, DSP instruction and MPU (memory protection unit)
• Operating conditions:– VDD, VDDA voltage range: 2.0 V to 3.6 V
• Memories– 128 to 256 Kbytes of Flash memory– Up to 40 Kbytes of SRAM, with HW parity
check implemented on the first 16 Kbytes.• CRC calculation unit• Reset and supply management
– Power-on/power-down reset (POR/PDR)– Programmable voltage detector (PVD)– Low-power modes: Sleep, Stop and
Standby– VBAT supply for RTC and backup registers
• Clock management– 4 to 32 MHz crystal oscillator– 32 kHz oscillator for RTC with calibration– Internal 8 MHz RC with x 16 PLL option– Internal 40 kHz oscillator
• Up to 87 fast I/Os– All mappable on external interrupt vectors– Several 5 V-tolerant
• Interconnect matrix• 12-channel DMA controller• Two ADCs 0.20 µS (up to 17 channels) with
selectable resolution of 12/10/8/6 bits, 0 to 3.6 V conversion range, single ended/differential input, separate analog supply from 2 to 3.6 V
• One 12-bit DAC channel with analog supply from 2.4 to 3.6 V
• Four fast rail-to-rail analog comparators with analog supply from 2 to 3.6 V
• Two operational amplifiers that can be used in PGA mode, all terminals accessible with analog supply from 2.4 to 3.6 V
• Up to 24 capacitive sensing channels supporting touchkey, linear and rotary touch sensors
• Up to 11 timers– One 32-bit timer and two 16-bit timers with
up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input
– One 16-bit 6-channel advanced-control timer, with up to 6 PWM channels, deadtime generation and emergency stop
– One 16-bit timer with 2 IC/OCs, 1 OCN/PWM, deadtime generation and emergency stop
– Two 16-bit timers with IC/OC/OCN/PWM, deadtime generation and emergency stop
– Two watchdog timers (independent, window)
– SysTick timer: 24-bit downcounter– One 16-bit basic timer to drive the DAC
• Calendar RTC with Alarm, periodic wakeup from Stop/Standby
• Communication interfaces– CAN interface (2.0B Active)– Two I2C Fast mode plus (1 Mbit/s) with
20 mA current sink, SMBus/PMBus, wakeup from STOP
– Up to five USART/UARTs (ISO 7816 interface, LIN, IrDA, modem control)
LQFP64 (10 × 10 mm)LQFP100 (14 × 14 mm)
LQFP48 (7 × 7 mm)WLCSP100 (0.4 mm pitch)
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– Up to three SPIs, two with multiplexed half/full duplex I2S interface, 4 to 16 programmable bit frames
– USB 2.0 full speed interface– Infrared transmitter
• Serial wire debug, Cortex®-M4 with FPU ETM, JTAG
• 96-bit unique ID
Table 1. Device summary Reference Part number
STM32F302xB STM32F302CB, STM32F302RB, STM32F302VB
STM32F302xC STM32F302CC, STM32F302RC, STM32F302VC
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Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAM . . . . 14
3.2 Memory protection unit (MPU) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.3 Embedded Flash memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.4 Embedded SRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5 Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.6 Cyclic redundancy check (CRC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.7 Power management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163.7.1 Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.2 Power supply supervision . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.7.4 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.8 Interconnect matrix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.9 Clocks and startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.10 General-purpose input/outputs (GPIOs) . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.11 Direct memory access (DMA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.12 Interrupts and events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203.12.1 Nested vectored interrupt controller (NVIC) . . . . . . . . . . . . . . . . . . . . . . 20
3.13 Fast analog-to-digital converter (ADC) . . . . . . . . . . . . . . . . . . . . . . . . . . . 213.13.1 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13.2 Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.13.3 VBAT battery voltage monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.13.4 OPAMP reference voltage (VREFOPAMP) . . . . . . . . . . . . . . . . . . . . . . 22
3.14 Digital-to-analog converter (DAC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.15 Operational amplifier (OPAMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.16 Fast comparators (COMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.17 Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 233.17.1 Advanced timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
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3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17) . . . 24
3.17.3 Basic timer (TIM6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.4 Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17.5 Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.17.6 SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18 Real-time clock (RTC) and backup registers . . . . . . . . . . . . . . . . . . . . . . 25
3.19 Inter-integrated circuit interface (I2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.20 Universal synchronous/asynchronous receiver transmitter (USART) . . . 27
3.21 Universal asynchronous receiver transmitter (UART) . . . . . . . . . . . . . . . 27
3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S) . 28
3.23 Controller area network (CAN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.24 Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.25 Infrared Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.26 Touch sensing controller (TSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.27 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313.27.1 Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.27.2 Embedded trace macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4 Pinouts and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
5 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
6 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 556.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
6.1.6 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
6.1.7 Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
6.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 596.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.3.2 Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . 60
6.3.3 Embedded reset and power control block characteristics . . . . . . . . . . . 60
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6.3.4 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.5 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3.6 Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
6.3.7 External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
6.3.8 Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.9 PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.10 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
6.3.11 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
6.3.12 Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
6.3.13 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
6.3.14 I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
6.3.15 NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
6.3.16 Timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
6.3.17 Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
6.3.18 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.19 DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
6.3.20 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.21 Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 121
6.3.22 Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
6.3.23 VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
7 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1257.1 LQFP100 – 14 x 14 mm, low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
7.2 LQFP64 – 10 x 10 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
7.3 LQFP48 – 7 x 7 mm, low-profile quad flat package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.4 WLCSP100 - 0.4 mm pitch wafer level chip scale package information 134
7.5 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1387.5.1 Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
7.5.2 Selecting the product temperature range . . . . . . . . . . . . . . . . . . . . . . 139
8 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2Table 2. STM32F302xB/STM32F302xC family device features and peripheral counts . . . . . . . . . . 12Table 3. External analog supply values for analog peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16Table 4. STM32F302xB/STM32F302xC peripheral interconnect matrix . . . . . . . . . . . . . . . . . . . . . 17Table 5. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23Table 6. Comparison of I2C analog and digital filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 7. STM32F302xB/STM32F302xC I2C implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26Table 8. USART features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27Table 9. STM32F302xB/STM32F302xC SPI/I2S implementation . . . . . . . . . . . . . . . . . . . . . . . . . . 28Table 10. Capacitive sensing GPIOs available on STM32F302xB/STM32F302xC devices . . . . . . . 30Table 11. No. of capacitive sensing channels available on STM32F302xB/STM32F302xC devices . 30Table 12. Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 13. STM32F302xB/STM32F302xC pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36Table 14. Alternate functions for port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44Table 15. Alternate functions for port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46Table 16. Alternate functions for port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48Table 17. Alternate functions for port D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49Table 18. Alternate functions for port E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50Table 19. Alternate functions for port F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51Table 20. STM32F302xB/STM32F302xC memory map, peripheral register boundary addresses . . 53Table 21. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Table 22. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 23. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58Table 24. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59Table 25. Operating conditions at power-up / power-down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60Table 26. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 60Table 27. Programmable voltage detector characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61Table 28. Embedded internal reference voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 29. Internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62Table 30. Typical and maximum current consumption from VDD supply at VDD = 3.6V . . . . . . . . . . . 63Table 31. Typical and maximum current consumption from the VDDA supply . . . . . . . . . . . . . . . . . . 64Table 32. Typical and maximum VDD consumption in Stop and Standby modes. . . . . . . . . . . . . . . . 65Table 33. Typical and maximum VDDA consumption in Stop and Standby modes. . . . . . . . . . . . . . . 65Table 34. Typical and maximum current consumption from VBAT supply. . . . . . . . . . . . . . . . . . . . . . 66Table 35. Typical current consumption in Run mode, code with data processing running from Flash67Table 36. Typical current consumption in Sleep mode, code running from Flash or RAM. . . . . . . . . 68Table 37. Switching output I/O current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70Table 38. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71Table 39. Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73Table 40. High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Table 41. Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Table 42. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76Table 43. LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78Table 44. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Table 45. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80Table 46. PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Table 47. Flash memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81Table 48. Flash memory endurance and data retention . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
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Table 49. EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82Table 50. EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 51. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83Table 52. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Table 53. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85Table 54. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 55. Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89Table 56. I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90Table 57. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Table 58. TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Table 59. IWDG min/max timeout period at 40 kHz (LSI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 60. WWDG min-max timeout value @72 MHz (PCLK). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 61. I2C timings specification (see I2C specification, rev.03, June 2007) . . . . . . . . . . . . . . . . . 94Table 62. I2C analog filter characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Table 63. SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96Table 64. I2S characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99Table 65. USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Table 66. USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101Table 67. USB: Full-speed electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102Table 68. ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Table 69. Maximum ADC RAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Table 70. ADC accuracy - limited test conditions, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . 108Table 71. ADC accuracy, 100-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110Table 72. ADC accuracy - limited test conditions, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . 112Table 73. ADC accuracy, 64-pin packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114Table 74. ADC accuracy at 1MSPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Table 75. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117Table 76. Comparator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119Table 77. Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121Table 78. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Table 79. Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Table 80. VBAT monitoring characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124Table 81. LQPF100 – 14 x 14 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . 125Table 82. LQFP64 – 10 x 10 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . 128Table 83. LQFP48 – 7 x 7 mm, low-profile quad flat package mechanical data. . . . . . . . . . . . . . . . 131Table 84. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135Table 85. WLCSP100 recommended PCB design rules (0.4 mm pitch) . . . . . . . . . . . . . . . . . . . . . 136Table 86. Package thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138Table 87. Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141Table 88. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
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List of figures STM32F302xB STM32F302xC
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List of figures
Figure 1. STM32F302xB/STM32F302xC block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13Figure 2. Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19Figure 3. Infrared transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29Figure 4. STM32F302xB/STM32F302xC LQFP48 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32Figure 5. STM32F302xB/STM32F302xC LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33Figure 6. STM32F302xB/STM32F302xC LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34Figure 7. STM32F302xB/STM32F302xC WLCSP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35Figure 8. STM32F302xB/STM32F302xC memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52Figure 9. Pin loading conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 10. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55Figure 11. Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56Figure 12. Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57Figure 13. Typical VBAT current consumption (LSE and RTC ON/LSEDRV[1:0] = ’00’) . . . . . . . . . . . 66Figure 14. High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74Figure 15. Low-speed external clock source AC timing diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75Figure 16. Typical application with an 8 MHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77Figure 17. Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79Figure 18. HSI oscillator accuracy characterization results for soldered parts . . . . . . . . . . . . . . . . . . 80Figure 19. TC and TTa I/O input characteristics - CMOS port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Figure 20. TC and TTa I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87Figure 21. Five volt tolerant (FT and FTf) I/O input characteristics - CMOS port. . . . . . . . . . . . . . . . . 88Figure 22. Five volt tolerant (FT and FTf) I/O input characteristics - TTL port . . . . . . . . . . . . . . . . . . . 88Figure 23. I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91Figure 24. Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92Figure 25. I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95Figure 26. SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Figure 27. SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97Figure 28. SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Figure 29. I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Figure 30. I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100Figure 31. USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 101Figure 32. ADC typical current consumption on VDDA pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Figure 33. ADC typical current consumption on VREF+ pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106Figure 34. ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Figure 35. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116Figure 36. 12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118Figure 37. Maximum VREFINT scaler startup time from power down. . . . . . . . . . . . . . . . . . . . . . . . 120Figure 38. OPAMP voltage noise versus frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123Figure 39. LQFP100 – 14 x 14 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . 125Figure 40. LQFP100 – 14 x 14 mm, low-profile quad flat package recommended footprint . . . . . . . 126Figure 41. LQFP100 – 14 x 14 mm, low-profile quad flat package top view example . . . . . . . . . . . . 127Figure 42. LQFP64 – 10 x 10 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . 128Figure 43. LQFP64 – 10 x 10 mm, low-profile quad flat package recommended footprint . . . . . . . . 129Figure 44. LQFP64 – 10 x 10 mm, low-profile quad flat package top view example . . . . . . . . . . . . . 130Figure 45. LQFP48 – 7 x 7 mm, low-profile quad flat package outline . . . . . . . . . . . . . . . . . . . . . . . 131Figure 46. LQFP48 - 7 x 7 mm, low-profile quad flat package recommended footprint. . . . . . . . . . . 132Figure 47. LQFP48 - 7 x 7 mm, low-profile quad flat package top view example . . . . . . . . . . . . . . . 133Figure 48. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
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package outline. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134Figure 49. WLCSP100 – 100L, 4.166 x 4.628 mm 0.4 mm pitch wafer level chip scale
package recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136Figure 50. WLCSP100, 0.4 mm pitch wafer level chip scale package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
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Introduction STM32F302xB STM32F302xC
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1 Introduction
This datasheet provides the ordering information and mechanical device characteristics of the STM32F302xB/STM32F302xC microcontrollers.
This STM32F302xB/STM32F302xC datasheet should be read in conjunction with the STM32F302xx reference manual (RM0365). The reference manual is available from the STMicroelectronics website www.st.com.
For information on the Arm®(a) Cortex®-M4 core with FPU, refer to:• Cortex®-M4 with FPU Technical Reference Manual, available from the
http://www.arm.com website.• STM32F3xxx and STM32F4xxx Cortex®-M4 programming manual (PM0214)
available from our website www.st.com.
a. Arm is a registered trademark of Arm Limited (or its subsidiaries) in the US and/or elsewhere.
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2 Description
The STM32F302xB/STM32F302xC family is based on the high-performance Arm® Cortex®-M4 32-bit RISC core with FPU operating at a frequency of up to 72 MHz, and embedding a floating point unit (FPU), a memory protection unit (MPU) and an embedded trace macrocell (ETM). The family incorporates high-speed embedded memories (up to 256 Kbytes of Flash memory, up to 40 Kbytes of SRAM) and an extensive range of enhanced I/Os and peripherals connected to two APB buses.
The devices offer up to two fast 12-bit ADCs (5 Msps), four comparators, two operational amplifiers, up to one DAC channel, a low-power RTC, up to five general-purpose 16-bit timers, one general-purpose 32-bit timer, and one timer dedicated to motor control. They also feature standard and advanced communication interfaces: up to two I2Cs, up to three SPIs (two SPIs are with multiplexed full-duplex I2Ss), three USARTs, up to two UARTs, CAN and USB. To achieve audio class accuracy, the I2S peripherals can be clocked via an external PLL.
The STM32F302xB/STM32F302xC family operates in the -40 to +85 °C and -40 to +105 °C temperature ranges from a 2.0 to 3.6 V power supply. A comprehensive set of power-saving mode allows the design of low-power applications.
The STM32F302xB/STM32F302xC family offers devices in four packages ranging from 48 pins to 100 pins.
The set of included peripherals changes with the device chosen.
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Table 2. STM32F302xB/STM32F302xC family device features and peripheral counts Peripheral STM32F302Cx STM32F302Rx STM32F302Vx
Flash (Kbytes) 128 256 128 256 128 256
SRAM (Kbytes) on data bus 32 40 32 40 32 40
Timers
Advanced control 1 (16-bit)
General purpose
5 (16-bit)1 (32-bit)
Basic 1 (16-bit)
PWM channels (all) (1)
1. This total number considers also the PWMs generated on the complementary output channels
26
PWM channels (except complementary) 20
Communication interfaces
SPI (I2S)(2)
2. The SPI interfaces can work in an exclusive way in either the SPI mode or the I2S audio mode.
3 (2)
I2C 2
USART 3
UART 0 2
CAN 1
USB 1
GPIOs
Normal I/Os (TC, TTa) 20 27
45 in LQFP10037 in WLCSP100
5-volt tolerant I/Os (FT, FTf) 17 25
42 in LQFP10040 in WLCSP100
DMA channels 12
Capacitive sensing channels 17 18 24
12-bit ADCs
Number of channels
2
9 16 17
12-bit DAC channels 1
Analog comparator 4
Operational amplifiers 2
CPU frequency 72 MHz
Operating voltage 2.0 to 3.6 V
Operating temperature Ambient operating temperature: - 40 to 85 °C / - 40 to 105 °CJunction temperature: - 40 to 125 °C
Packages LQFP48 LQFP64LQFP100
WLCSP100
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Figure 1. STM32F302xB/STM32F302xC block diagram
1. AF: alternate function on I/O pins.
MSv36608V2
Touch Sensing Controller
AH
B d
ecod
er
TIMER 16
2 Channels,1 Comp Channel, BRK as AF
TIMER 17
TIMER 1 / PWM
SPI1MOSI, MISO, SCK,NSS as AF
USART1RX, TX, CTS, RTS, SmartCard as AF
WinWATCHDOG
Bus
Mat
rix
MPU/FPU
Cortex M4 CPU
Fmax: 72 MHz
NVIC
GP DMA1 7 channels
Flas
h in
terfa
ceOB
L
FLASH 256 KB64 bits
JTRSTJTDI
JTCK/SWCLKJTMS/SWDIO
JTDOAs AF
Power
Voltage reg.3.3 V to 1.8V
VDD18
Supply Supervision
POR /PDR
PVD
POR
ResetInt.
VDDIO = 2 to 3.6 VVSS
NRESETVDDAVSSA
Ind. WDG32KStandbyinterface
PLL
@VDDIO
@VDDA
XTAL OSC4 -32 MHz
Reset & clock
control
AHBPCLKAPBP1CLKAPBP2CLK
AHB2APB2
AHB2APB1
CRC
AP
B1
F max
= 3
6 M
Hz
AP
B2
f max
= 7
2 M
Hz
GPIO PORT A
GPIO PORT B
GPIO PORT C
GPIO PORT D
GPIO PORT E
OSC_INOSC_OUT
SPI3/I2S
SCL, SDA, SMBA as AF
USART2
SCL, SDA, SMBA as AF
USART3
RC LS
TIMER6
TIMER 4
SPI2/I2S
12bit DAC1IF
@VDDA
TIMER2 (32-bit/PWM)PA[15:0]
PB[15:0]
PC[15:0]
MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF
4 Channels, ETR as AF
USB_DP, USB_DM
DAC1_CH1 as AF
HCLKFCLK
USARTCLK
RC HS 8MHz
SRAM40 KB
ETMTrace/TrigSWJTAG
TPIU
Ibus
TRADECLKTRACED[0-3]
as AF
Dbus
System
GP DMA2 5 channels
12-bit ADC1
12-bit ADC2
Temp. sensor
VREF+ VREF-
TIMER 15
EXT.ITWKUPXX AF
1 Channel, 1 Comp Channel, BRK as AF
1 Channel, 1 Comp Channel, BRK as AF
4 Channels, 4 Comp channels, ETR, BRK as AF
GPIO PORT F
PD[15:0]
PE[15:0]
USB SRAM 512B
PF[7:0]
IF
I2CCLKADC SAR1/2/3/4 CLK
@VDDIO
@VDDA
@VSW
XTAL 32kHz OSC32_INOSC32_OUT
VBAT = 1.65V to 3.6V
RTCAWU
BackupReg
(64Byte)Backupinterface
ANTI-TAMP
TIMER 3
UART4
UART5
I2C1
I2C2
bx CAN & 512B SRAM
USB 2.0 FS
OpAmp1
OpAmp2
@VDDA
INxx / OUTxx
INxx / OUTxx
INTE
RFA
CESYSCFG CTL
GP Comparator 6GP Comparator 4
GP Comparator 2
CAN TX, CAN RX
4 Channels, ETR as AF
4 Channels, ETR as AF
RX, TX, CTS, RTS, as AF
RX, TX, CTS, RTS, as AF
RX, TX as AF
RX, TX as AF
@VDDA
Xx Ins, 4 OUTs as AF
XX Groups of 4 channels as AF
GP Comparator 1
MOSI/SD, MISO/ext_SD, SCK/CK, NSS/WS, MCLK as AF
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3 Functional overview
3.1 Arm® Cortex®-M4 core with FPU with embedded Flash and SRAMThe Arm Cortex-M4 processor with FPU is the latest generation of Arm processors for embedded systems. It was developed to provide a low-cost platform that meets the needs of MCU implementation, with a reduced pin count and low-power consumption, while delivering outstanding computational performance and an advanced response to interrupts.
The Arm Cortex-M4 32-bit RISC processor with FPU features exceptional code-efficiency, delivering the high-performance expected from an Arm core in the memory size usually associated with 8- and 16-bit devices.
The processor supports a set of DSP instructions which allow efficient signal processing and complex algorithm execution.
Its single precision FPU speeds up software development by using metalanguage development tools, while avoiding saturation.
With its embedded Arm core, the STM32F302xB/STM32F302xC family is compatible with all Arm tools and software.
Figure 1 shows the general block diagram of the STM32F302xB/STM32F302xC family devices.
3.2 Memory protection unit (MPU)The memory protection unit (MPU) is used to separate the processing of tasks from the data protection. The MPU can manage up to 8 protection areas that can all be further divided up into 8 subareas. The protection area sizes are between 32 bytes and the whole 4 gigabytes of addressable memory.
The memory protection unit is especially helpful for applications where some critical or certified code has to be protected against the misbehavior of other tasks. It is usually managed by an RTOS (real-time operating system). If a program accesses a memory location that is prohibited by the MPU, the RTOS can detect it and take action. In an RTOS environment, the kernel can dynamically update the MPU area setting, based on the process to be executed.
The MPU is optional and can be bypassed for applications that do not need it.
3.3 Embedded Flash memoryAll STM32F302xB/STM32F302xC devices feature up to 256 Kbytes of embedded Flash memory available for storing programs and data. The Flash memory access time is adjusted to the CPU clock frequency (0 wait state from 0 to 24 MHz, 1 wait state from 24 to 48 MHz and 2 wait states above).
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3.4 Embedded SRAMSTM32F302xB/STM32F302xC devices feature up to 40 Kbytes of embedded SRAM with hardware parity check on first 16 Kbytes of SRAM. The memory can be accessed in read/write at CPU clock speed with 0 wait states.
3.5 Boot modesAt startup, Boot0 pin and Boot1 option bit are used to select one of three boot options:• Boot from user Flash• Boot from system memory• Boot from embedded SRAMThe boot loader is located in the system memory. It is used to reprogram the Flash memory by using USART1 (PA9/PA10), USART2 (PD5/PD6) or USB (PA11/PA12) through DFU (device firmware upgrade).
3.6 Cyclic redundancy check (CRC)The CRC (cyclic redundancy check) calculation unit is used to get a CRC code using a configurable generator polynomial value and size.
Among other applications, CRC-based techniques are used to verify data transmission or storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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3.7 Power management
3.7.1 Power supply schemes• VSS, VDD = 2.0 to 3.6 V: external power supply for I/Os and the internal regulator. It is
provided externally through VDD pins.• VSSA, VDDA = 2.0 to 3.6 V: external analog power supply for ADC, DAC, comparators
operational amplifiers, reset blocks, RCs and PLL. The minimum voltage to be applied to VDDA differs from one analog peripheral to another. Table 3 provides the summary of the VDDA ranges for analog peripherals. The VDDA voltage level must be always greater or equal to the VDD voltage level and must be provided first.
• VBAT = 1.65 to 3.6 V: power supply for RTC, external clock 32 kHz oscillator and backup registers (through power switch) when VDD is not present.
3.7.2 Power supply supervisionThe device has an integrated power-on reset (POR) and power-down reset (PDR) circuits. They are always active, and ensure proper operation above a threshold of 2 V. The device remains in reset mode when the monitored supply voltage is below a specified threshold, VPOR/PDR, without the need for an external reset circuit.• The POR monitors only the VDD supply voltage. During the startup phase it is required
that VDDA should arrive first and be greater than or equal to VDD.• The PDR monitors both the VDD and VDDA supply voltages, however the VDDA power
supply supervisor can be disabled (by programming a dedicated Option bit) to reduce the power consumption if the application design ensures that VDDA is higher than or equal to VDD.
The device features an embedded programmable voltage detector (PVD) that monitors the VDD power supply and compares it to the VPVD threshold. An interrupt can be generated when VDD drops below the VPVD threshold and/or when VDD is higher than the VPVD threshold. The interrupt service routine can then generate a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.7.3 Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR), and power-down.• The MR mode is used in the nominal regulation mode (Run)• The LPR mode is used in Stop mode.• The power-down mode is used in Standby mode: the regulator output is in high
impedance, and the kernel circuitry is powered down thus inducing zero consumption.The voltage regulator is always enabled after reset. It is disabled in Standby mode.
Table 3. External analog supply values for analog peripherals Analog peripheral Minimum VDDA supply Maximum VDDA supply
ADC / COMP 2.0 V 3.6 V
DAC / OPAMP 2.4 V 3.6V
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3.7.4 Low-power modesThe STM32F302xB/STM32F302xC supports three low-power modes to achieve the best compromise between low-power consumption, short startup time and available wakeup sources:• Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can wake up the CPU when an interrupt/event occurs.
• Stop modeStop mode achieves the lowest power consumption while retaining the content of SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC and the HSE crystal oscillators are disabled. The voltage regulator can also be put either in normal or in low-power mode.The device can be woken up from Stop mode by any of the EXTI line. The EXTI line source can be one of the 16 external lines, the PVD output, the USB wakeup, the RTC alarm, COMPx, I2Cx or U(S)ARTx.
• Standby modeThe Standby mode is used to achieve the lowest power consumption. The internal voltage regulator is switched off so that the entire 1.8 V domain is powered off. The PLL, the HSI RC and the HSE crystal oscillators are also switched off. After entering Standby mode, SRAM and register contents are lost except for registers in the Backup domain and Standby circuitry.The device exits Standby mode when an external reset (NRST pin), an IWDG reset, a rising edge on the WKUP pin or an RTC alarm occurs.
Note: The RTC, the IWDG and the corresponding clock sources are not stopped by entering Stop or Standby mode.
3.8 Interconnect matrixSeveral peripherals have direct connections between them. This allows autonomous communication between peripherals, saving CPU resources thus power supply consumption. In addition, these hardware connections allow fast and predictable latency.
Table 4. STM32F302xB/STM32F302xC peripheral interconnect matrix
Interconnect source Interconnect destination Interconnect action
TIMx
TIMx Timers synchronization or chaining
ADCxDAC1
Conversion triggers
DMA Memory to memory transfer trigger
Compx Comparator output blanking
COMPx TIMx Timer input: OCREF_CLR input, input capture
ADCx TIMx Timer triggered by analog watchdog
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Note: For more details about the interconnect actions, please refer to the corresponding sections in the reference manual (RM0365.
3.9 Clocks and startupSystem clock selection is performed on startup, however the internal RC 8 MHz oscillator is selected as default CPU clock on reset. An external 4-32 MHz clock can be selected, in which case it is monitored for failure. If failure is detected, the system automatically switches back to the internal RC oscillator. A software interrupt is generated if enabled. Similarly, full interrupt management of the PLL clock entry is available when necessary (for example with failure of an indirectly used external oscillator).
Several prescalers allow to configure the AHB frequency, the high speed APB (APB2) and the low speed APB (APB1) domains. The maximum frequency of the AHB and the high speed APB domains is 72 MHz, while the maximum allowed frequency of the low speed APB domain is 36 MHz.
GPIORTCCLKHSE/32MC0
TIM16 Clock source used as input channel for HSI and LSI calibration
CSSCPU (hard fault)COMPxPVDGPIO
TIM1, TIM15, 16, 17
Timer break
GPIO
TIMx External trigger, timer break
ADCxDAC1
Conversion external trigger
DAC1 COMPx Comparator inverting input
Table 4. STM32F302xB/STM32F302xC peripheral interconnect matrix (continued)
Interconnect source Interconnect destination Interconnect action
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Figure 2. Clock tree
/32
4-32 MHzHSE OSC
OSC_IN
OSC_OUT
OSC32_IN
OSC32_OUT
8 MHzHSI RC
IWDGCLKto IWDG
PLLx2,x3,..
x16
PLLMUL
AHB APB1prescaler
/1,2,4,8,16
HCLK
PLLCLK
to AHB bus, core, memory and DMA
LSE
LSI
HSI
HSI
HSE
to RTC
PLLSRC SW /8
SYSCLK
RTCCLK
RTCSEL[1:0]
to TIM 2,3,4,6,7
If (APB1 prescaler =1) x1 else x2
FLITFCLKto Flash programming interface
to I2Cx (x = 1,2)
to U(S)ARTx (x = 2..5)
LSEHSI
SYSCLK
/2
PCLK1
SYSCLK
HSI
PCLK1
MS19989V5
to I2Sx (x = 2,3)
USBCLKto USB interface
to cortex System timer FHCLK Cortex free running clock to APB1 peripherals
AHBprescaler/1,2,..512
CSS/2,/3,.../16
LSE OSC32.768kHz
LSI RC 40kHz
USBprescaler
/1,1.5
APB2prescaler
/1,2,4,8,16
to TIM 15,16,17If (APB2 prescaler =1) x1 else x2
to USART1
LSEHSI
SYSCLKPCLK2
PCLK2 to APB2 peripherals
TIM1/8
ADCPrescaler
/1,2,4 to ADCxy(xy = 12, 34)
ADCPrescaler
/1,2,4,6,8,10,12,16,32,64,128,256
I2SSRC
SYSCLK
Ext. clockI2S_CKIN
x2
MCO
Main clockoutput
/2 PLLCLKHSI
HSE
MCOSYSCLK
LSI
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3.10 General-purpose input/outputs (GPIOs)Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the GPIO pins are shared with digital or analog alternate functions. All GPIOs are high current capable except for analog inputs.
The I/Os alternate function configuration can be locked if needed following a specific sequence in order to avoid spurious writing to the I/Os registers.
Fast I/O handling allows I/O toggling up to 36 MHz.
3.11 Direct memory access (DMA)The flexible general-purpose DMA is able to manage memory-to-memory, peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports circular buffer management, avoiding the generation of interrupts when the controller reaches the end of the buffer.
Each of the 12 DMA channels is connected to dedicated hardware DMA requests, with software trigger support for each channel. Configuration is done by software and transfer sizes between source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, general-purpose timers, DAC and ADC.
3.12 Interrupts and events
3.12.1 Nested vectored interrupt controller (NVIC)The STM32F302xB/STM32F302xC devices embed a nested vectored interrupt controller (NVIC) able to handle up to 66 maskable interrupt channels and 16 priority levels.
The NVIC benefits are the following:• Closely coupled NVIC gives low latency interrupt processing• Interrupt entry vector table address passed directly to the core• Closely coupled NVIC core interface• Allows early processing of interrupts• Processing of late arriving higher priority interrupts• Support for tail chaining• Processor state automatically saved• Interrupt entry restored on interrupt exit with no instruction overhead
The NVIC hardware block provides flexible interrupt management features with minimal interrupt latency.
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3.13 Fast analog-to-digital converter (ADC)Two fast analog-to-digital converters 5 MSPS, with selectable resolution between 12 and 6 bit, are embedded in the STM32F302xB/STM32F302xC family devices. The ADCs have up to 17 external channels (5 channels multiplexed between ADC1 and ADC2). Channels can be configured to be either single-ended input or differential input. The ADCs can perform conversions in single-shot or scan modes. In scan mode, automatic conversion is performed on a selected group of analog inputs.
The ADCs have also internal channels: Temperature sensor connected to ADC1 channel 16, VBAT/2 connected to ADC1 channel 17, Voltage reference VREFINT connected to the 2 ADCs channel 18, VREFOPAMP1 connected to ADC1 channel 15 and VREFOPAMP2 connected to ADC2 channel 17.
Additional logic functions embedded in the ADC interface allow:• Simultaneous sample and hold• Interleaved sample and hold• Single-shunt phase current reading techniques.
The ADC can be served by the DMA controller. 3 analog watchdogs per ADC are available.
An analog watchdog feature allows very precise monitoring of the converted voltage of one, some or all selected channels. An interrupt is generated when the converted voltage is outside the programmed thresholds.
The events generated by the general-purpose timers and the advanced-control timer (TIM1) can be internally connected to the ADC start trigger and injection trigger, respectively, to allow the application to synchronize A/D conversion and timers.
3.13.1 Temperature sensorThe temperature sensor (TS) generates a voltage VSENSE that varies linearly with temperature.
The temperature sensor is internally connected to the ADC1_IN16 input channel which is used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall accuracy of the temperature measurement. As the offset of the temperature sensor varies from chip to chip due to process variation, the uncalibrated internal temperature sensor is suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is individually factory-calibrated by ST. The temperature sensor factory calibration data are stored by ST in the system memory area, accessible in read-only mode.
3.13.2 Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the ADC and Comparators. VREFINT is internally connected to the ADCx_IN18, x=1...2 input channel. The precise voltage of VREFINT is individually measured for each part by ST during production test and stored in the system memory area. It is accessible in read-only mode.
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3.13.3 VBAT battery voltage monitoring
This embedded hardware feature allows the application to measure the VBAT battery voltage using the internal ADC channel ADC1_IN17. As the VBAT voltage may be higher than VDDA, and thus outside the ADC input range, the VBAT pin is internally connected to a bridge divider by 2. As a consequence, the converted digital value is half the VBAT voltage.
3.13.4 OPAMP reference voltage (VREFOPAMP)Every OPAMP reference voltage can be measured using a corresponding ADC internal channel: VREFOPAMP1 connected to ADC1 channel 15, VREFOPAMP2 connected to ADC2 channel 17.
3.14 Digital-to-analog converter (DAC)A single 12-bit buffered DAC channel can be used to convert digital signals into analog voltage signal outputs. The chosen design structure is composed of integrated resistor strings and an amplifier in inverting configuration.
This digital interface supports the following features:• One DAC output channel • 8-bit or 10-bit monotonic output• Left or right data alignment in 12-bit mode• Noise-wave generation• Triangular-wave generation• DMA capability • External triggers for conversion
3.15 Operational amplifier (OPAMP)The STM32F302xB/STM32F302xC embeds two operational amplifiers with external or internal follower routing and PGA capability (or even amplifier and filter capability with external components). When an operational amplifier is selected, an external ADC channel is used to enable output measurement.
The operational amplifier features:• 8.2 MHz bandwidth• 0.5 mA output capability• Rail-to-rail input/output• In PGA mode, the gain can be programmed to be 2, 4, 8 or 16.
3.16 Fast comparators (COMP)The STM32F302xB/STM32F302xC devices embed four fast rail-to-rail comparators with programmable reference voltage (internal or external), hysteresis and speed (low speed for low-power) and with selectable output polarity.
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The reference voltage can be one of the following:• External I/O• DAC output pin• Internal reference voltage or submultiple (1/4, 1/2, 3/4). Refer to Table 28: Embedded
internal reference voltage on page 62 for the value and precision of the internal reference voltage.
All comparators can wake up from STOP mode, generate interrupts and breaks for the timers and can be also combined per pair into a window comparator
3.17 Timers and watchdogsThe STM32F302xB/STM32F302xC includes one advanced control timer, up to six general-purpose timers, one basic timer, two watchdog timers and a SysTick timer. The table below compares the features of the advanced control, general purpose and basic timers.
Note: TIM1/8 can have PLL as clock source, and therefore can be clocked at 144 MHz.
Table 5. Timer feature comparison
Timer type Timer Counter resolutionCounter
typePrescaler
factor
DMA request
generation
Capture/compare Channels
Complementary outputs
Advanced TIM1 16-bit Up, Down, Up/Down
Any integer between 1 and 65536
Yes 4 Yes
General-purpose TIM2 32-bit
Up, Down, Up/Down
Any integer between 1 and 65536
Yes 4 No
General-purpose TIM3, TIM4 16-bit
Up, Down, Up/Down
Any integer between 1 and 65536
Yes 4 No
General-purpose TIM15 16-bit Up
Any integer between 1 and 65536
Yes 2 1
General-purpose TIM16, TIM17 16-bit Up
Any integer between 1 and 65536
Yes 1 1
Basic TIM6 16-bit UpAny integer between 1 and 65536
Yes 0 No
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3.17.1 Advanced timer (TIM1)The advanced-control timer, TIM1, can be seen as a three-phase PWM multiplexed on six channels. It has a complementary PWM output with programmable inserted dead-times. It can also be seen as a complete general-purpose timer. The four independent channels can be used for:• Input capture• Output compare• PWM generation (edge or center-aligned modes) with full modulation capability (0-
100%)• One-pulse mode output
In debug mode, the advanced-control timer counter can be frozen and the PWM outputs disabled to turn off any power switches driven by these outputs.
Many features are shared with those of the general-purpose TIM timers (described in Section 3.17.2 using the same architecture, so the advanced-control timers can work together with the TIM timers via the Timer Link feature for synchronization or event chaining.
3.17.2 General-purpose timers (TIM2, TIM3, TIM4, TIM15, TIM16, TIM17)There are up to six synchronizable general-purpose timers embedded in the STM32F302xB/STM32F302xC (see Table 5 for differences). Each general-purpose timer can be used to generate PWM outputs, or act as a simple time base.• TIM2, 3, and TIM4
These are full-featured general-purpose timers:– TIM2 has a 32-bit auto-reload up/downcounter and 32-bit prescaler– TIM3 and 4 have 16-bit auto-reload up/downcounters and 16-bit prescalers.These timers all feature 4 independent channels for input capture/output compare, PWM or one-pulse mode output. They can work together, or with the other general-purpose timers via the Timer Link feature for synchronization or event chaining.The counters can be frozen in debug mode.All have independent DMA request generation and support quadrature encoders.
• TIM15, 16 and 17These three timers general-purpose timers with mid-range features:They have 16-bit auto-reload upcounters and 16-bit prescalers.– TIM15 has 2 channels and 1 complementary channel– TIM16 and TIM17 have 1 channel and 1 complementary channelAll channels can be used for input capture/output compare, PWM or one-pulse mode output.The timers can work together via the Timer Link feature for synchronization or event chaining. The timers have independent DMA request generation.The counters can be frozen in debug mode.
3.17.3 Basic timer (TIM6)This timer is mainly used for DAC trigger generation. It can also be used as a generic 16-bit time base.
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3.17.4 Independent watchdog (IWDG)The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is clocked from an independent 40 kHz internal RC and as it operates independently from the main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog to reset the device when a problem occurs, or as a free running timer for application timeout management. It is hardware or software configurable through the option bytes. The counter can be frozen in debug mode.
3.17.5 Window watchdog (WWDG)The window watchdog is based on a 7-bit downcounter that can be set as free running. It can be used as a watchdog to reset the device when a problem occurs. It is clocked from the main clock. It has an early warning interrupt capability and the counter can be frozen in debug mode.
3.17.6 SysTick timerThis timer is dedicated to real-time operating systems, but could also be used as a standard down counter. It features:• A 24-bit down counter• Autoreload capability• Maskable system interrupt generation when the counter reaches 0.• Programmable clock source
3.18 Real-time clock (RTC) and backup registersThe RTC and the 16 backup registers are supplied through a switch that takes power from either the VDD supply when present or the VBAT pin. The backup registers are sixteen 32-bit registers used to store 64 bytes of user application data when VDD power is not present.
They are not reset by a system or power reset, or when the device wakes up from Standby mode.
The RTC is an independent BCD timer/counter.It supports the following features:• Calendar with subsecond, seconds, minutes, hours (12 or 24 format), week day, date,
month, year, in BCD (binary-coded decimal) format.• Reference clock detection: a more precise second source clock (50 or 60 Hz) can be
used to enhance the calendar precision.• Automatic correction for 28, 29 (leap year), 30 and 31 days of the month.• Two programmable alarms with wake up from Stop and Standby mode capability. • On-the-fly correction from 1 to 32767 RTC clock pulses. This can be used to
synchronize it with a master clock. • Digital calibration circuit with 1 ppm resolution, to compensate for quartz crystal
inaccuracy. • Three anti-tamper detection pins with programmable filter. The MCU can be woken up
from Stopand Standby modes on tamper event detection.• Timestamp feature which can be used to save the calendar content. This function can
be triggered by an event on the timestamp pin, or by a tamper event. The MCU can be woken up from Stop and Standby modes on timestamp event detection.
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• 17-bit Auto-reload counter for periodic interrupt with wakeup from STOP/STANDBY capability.
The RTC clock sources can be:• A 32.768 kHz external crystal• A resonator or oscillator• The internal low-power RC oscillator (typical frequency of 40 kHz) • The high-speed external clock divided by 32.
3.19 Inter-integrated circuit interface (I2C)Up to two I2C bus interfaces can operate in multimaster and slave modes. They can support standard (up to 100 KHz), fast (up to 400 KHz) and fast mode + (up to 1 MHz) modes.
Both support 7-bit and 10-bit addressing modes, multiple 7-bit slave addresses (2 addresses, 1 with configurable mask). They also include programmable analog and digital noise filters.
In addition, they provide hardware support for SMBUS 2.0 and PMBUS 1.1: ARP capability, Host notify protocol, hardware CRC (PEC) generation/verification, timeouts verifications and ALERT protocol management. They also have a clock domain independent from the CPU clock, allowing the I2Cx (x=1,2) to wake up the MCU from Stop mode on address match.
The I2C interfaces can be served by the DMA controller.
Refer to Table 7 for the features available in I2C1 and I2C2.
Table 6. Comparison of I2C analog and digital filters Analog filter Digital filter
Pulse width of suppressed spikes 50 ns
Programmable length from 1 to 15 I2C peripheral clocks
Benefits Available in Stop mode1. Extra filtering capability vs. standard requirements.2. Stable length
Drawbacks Variations depending on temperature, voltage, process
Wakeup from Stop on address match is not available when digital filter is enabled.
Table 7. STM32F302xB/STM32F302xC I2C implementation I2C features(1) I2C1 I2C2
7-bit addressing mode X X
10-bit addressing mode X X
Standard mode (up to 100 kbit/s) X X
Fast mode (up to 400 kbit/s) X X
Fast Mode Plus with 20mA output drive I/Os (up to 1 Mbit/s) X X
Independent clock X X
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3.20 Universal synchronous/asynchronous receiver transmitter (USART)The STM32F302xB/STM32F302xC devices have three embedded universal synchronous/asynchronous receiver transmitters (USART1, USART2 and USART3).
The USART interfaces are able to communicate at speeds of up to 9 Mbits/s.
They provide hardware management of the CTS and RTS signals, they support IrDA SIR ENDEC, the multiprocessor communication mode, the single-wire half-duplex communication mode and have LIN Master/Slave capability. The USART interfaces can be served by the DMA controller.
3.21 Universal asynchronous receiver transmitter (UART)The STM32F302xB/STM32F302xC devices have 2 embedded universal asynchronous receiver transmitters (UART4, and UART5). The UART interfaces support IrDA SIR ENDEC, multiprocessor communication mode and single-wire half-duplex communication mode. The UART4 interface can be served by the DMA controller.
Refer to Table 8 for the features available in all U(S)ART interfaces.
SMBus X X
Wakeup from STOP X X
1. X = supported.
Table 7. STM32F302xB/STM32F302xC I2C implementation (continued)I2C features(1) I2C1 I2C2
Table 8. USART features USART modes/features(1) USART1 USART2 USART3 UART4 UART5
Hardware flow control for modem X X X - -
Continuous communication using DMA X X X X -
Multiprocessor communication X X X X X
Synchronous mode X X X - -
Smartcard mode X X X - -
Single-wire half-duplex communication X X X X X
IrDA SIR ENDEC block X X X X X
LIN mode X X X X X
Dual clock domain and wakeup from Stop mode X X X X X
Receiver timeout interrupt X X X X X
Modbus communication X X X X X
Auto baud rate detection X X X - -
Driver Enable X X X - -
1. X = supported.
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3.22 Serial peripheral interface (SPI)/Inter-integrated sound interfaces (I2S)Up to three SPIs are able to communicate up to 18 Mbits/s in slave and master modes in full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode frequencies and the frame size is configurable from 4 bits to 16 bits.
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) supporting four different audio standards can operate as master or slave at half-duplex and full duplex communication modes. They can be configured to transfer 16 and 24 or 32 bits with 16-bit or 32-bit data resolution and synchronized by a specific signal. Audio sampling frequency from 8 kHz up to 192 kHz can be set by 8-bit programmable linear prescaler. When operating in master mode it can output a clock for an external audio component at 256 times the sampling frequency.
Refer to Table 9 for the features available in SPI1, SPI2 and SPI3.
3.23 Controller area network (CAN)The CAN is compliant with specifications 2.0A and B (active) with a bit rate up to 1 Mbit/s. It can receive and transmit standard frames with 11-bit identifiers as well as extended frames with 29-bit identifiers. It has three transmit mailboxes, two receive FIFOs with 3 stages and 14 scalable filter banks.
3.24 Universal serial bus (USB)The STM32F302xB/STM32F302xC devices embed an USB device peripheral compatible with the USB full-speed 12 Mbs. The USB interface implements a full-speed (12 Mbit/s) function interface. It has software-configurable endpoint setting and suspend/resume support. The dedicated 48 MHz clock is generated from the internal main PLL (the clock source must use a HSE crystal oscillator). The USB has a dedicated 512-bytes SRAM memory for data transmission and reception.
Table 9. STM32F302xB/STM32F302xC SPI/I2S implementation SPI features(1)
1. X = supported.
SPI1 SPI2 SPI3
Hardware CRC calculation X X X
Rx/Tx FIFO X X X
NSS pulse mode X X X
I2S mode - X X
TI mode X X X
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3.25 Infrared TransmitterThe STM32F302xB/STM32F302xC devices provide an infrared transmitter solution. The solution is based on internal connections between TIM16 and TIM17 as shown in the figure below.
TIM17 is used to provide the carrier frequency and TIM16 provides the main signal to be sent. The infrared output signal is available on PB9 or PA13.
To generate the infrared remote control signals, TIM16 channel 1 and TIM17 channel 1 must be properly configured to generate correct waveforms. All standard IR pulse modulation modes can be obtained by programming the two timers output compare channels.
Figure 3. Infrared transmitter
3.26 Touch sensing controller (TSC)The STM32F302xB/STM32F302xC devices provide a simple solution for adding capacitive sensing functionality to any application. These devices offer up to 24 capacitive sensing channels distributed over 8 analog I/O groups.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which is protected from direct touch by a dielectric (glass, plastic, ...). The capacitive variation introduced by the finger (or any conductive object) is measured using a proven implementation based on a surface charge transfer acquisition principle. It consists of charging the sensor capacitance and then transferring a part of the accumulated charges into a sampling capacitor until the voltage across this capacitor has reached a specific threshold. To limit the CPU bandwidth usage this acquisition is directly managed by the hardware touch sensing controller and only requires few external components to operate.
The touch sensing controller is fully supported by the STMTouch touch sensing firmware library which is free to use and allows touch sensing functionality to be implemented reliably in the end application.
MSv30365V1
TIMER 16
(for envelop)
TIMER 17
(for carrier)
OC
OC
PB9/PA13
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Table 10. Capacitive sensing GPIOs available on STM32F302xB/STM32F302xC devices
Group Capacitive sensing signal namePin
name GroupCapacitive sensing
signal namePin
name
1
TSC_G1_IO1 PA0
5
TSC_G5_IO1 PB3
TSC_G1_IO2 PA1 TSC_G5_IO2 PB4
TSC_G1_IO3 PA2 TSC_G5_IO3 PB6
TSC_G1_IO4 PA3 TSC_G5_IO4 PB7
2
TSC_G2_IO1 PA4
6
TSC_G6_IO1 PB11
TSC_G2_IO2 PA5 TSC_G6_IO2 PB12
TSC_G2_IO3 PA6 TSC_G6_IO3 PB13
TSC_G2_IO4 PA7 TSC_G6_IO4 PB14
3
TSC_G3_IO1 PC5
7
TSC_G7_IO1 PE2
TSC_G3_IO2 PB0 TSC_G7_IO2 PE3
TSC_G3_IO3 PB1 TSC_G7_IO3 PE4
TSC_G3_IO4 PB2 TSC_G7_IO4 PE5
4
TSC_G4_IO1 PA9
8
TSC_G8_IO1 PD12
TSC_G4_IO2 PA10 TSC_G8_IO2 PD13
TSC_G4_IO3 PA13 TSC_G8_IO3 PD14
TSC_G4_IO4 PA14 TSC_G8_IO4 PD15
Table 11. No. of capacitive sensing channels available on STM32F302xB/STM32F302xC devices
Analog I/O groupNumber of capacitive sensing channels
STM32F302Vx STM32F302Rx STM32F302Cx
G1 3 3 3
G2 3 3 3
G3 3 3 2
G4 3 3 3
G5 3 3 3
G6 3 3 3
G7 3 0 0
G8 3 0 0
Number of capacitive sensing channels 24 18 17
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3.27 Development support
3.27.1 Serial wire JTAG debug port (SWJ-DP)The Arm SWJ-DP Interface is embedded, and is a combined JTAG and serial wire debug port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG TMS and TCK pins are shared respectively with SWDIO and SWCLK and a specific sequence on the TMS pin is used to switch between JTAG-DP and SW-DP.
3.27.2 Embedded trace macrocell™ The Arm embedded trace macrocell provides a greater visibility of the instruction and data flow inside the CPU core by streaming compressed data at a very high rate from the STM32F302xB/STM32F302xC through a small number of ETM pins to an external hardware trace port analyzer (TPA) device. The TPA is connected to a host computer using a high-speed channel. Real-time instruction and data flow activity can be recorded and then formatted for display on the host computer running debugger software. TPA hardware is commercially available from common development tool vendors. It operates with third party debugger software tools.
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4 Pinouts and pin description
Figure 4. STM32F302xB/STM32F302xC LQFP48 pinout
MSv40448V1
47 46 45 44 43 42 41
VS
S
BO
OT0
PB
5
40 39 38 37363534333231302928272625
21 22 23 24
PB
4P
B3
VDDVSS
PA12
PB15PB14PB13PB12
PB
10
VS
SP
B11
VD
D
48
13
23
456 7 8 9 1011
VBAT
PC14/OSC32_INPC15/OSC32_OUT
NRSTVSSA/VREF-
VDDAPA0PA1PA2
VD
D
PF0/OSC_INPF1/OSC_OUT
PC13
12
1
14 15 16 17 18 19 20
PA7
PB
1P
B2
LQFP48
PA13
PA11PA10PA9PA8
PA3
PA4
PA5
PA6
PB
0
PB
9P
B8
PB
7P
B6
PA15
PA14
-
DS9911 Rev 9 33/145
STM32F302xB STM32F302xC Pinouts and pin description
54
Figure 5. STM32F302xB/STM32F302xC LQFP64 pinout
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 4948474645444342414039383736353433
17 18 19 20 21 22 23 24 29 30 31 3225 26 27 28
123456 7 8 9 10111213141516
VBAT
PC14/OSC32_INPC15/OSC32_OUT
NRSTPC0PC1PC2PC3
VSSA/VREF-VDDA
PA0PA1PA2
VD
D
PD
2
PC
12P
C11
PC
10
VDDVSS
PC8PC7PC6
PB12
PF4PA
3
VD
D
PC
4P
C5
PB
2P
B10
PF1/OSC_OUTPF0/OSC_IN
PC13
VS
S
PB
11V
SS
VD
D
LQFP64
MS40449V2
PA13PA12PA11PA10PA9PA8PC9
PB15PB14PB13
PA4
PA5
PA6
PA7
PB
0P
B1
PB
9P
B8
BO
OT0
PB
7P
B6
PB
5P
B4
PB
3
PA15
PA14
-
Pinouts and pin description STM32F302xB STM32F302xC
34/145 DS9911 Rev 9
Figure 6. STM32F302xB/STM32F302xC LQFP100 pinout
100
99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
12345678910111213141516171819202122232425
75747372717069686766656463626160595857565554535251
PE2PE3PE4PE5PE6
VBAT
PC14/OSC32_INPC15/OSC32_OUT
PF9PF10
PF0/OSC_IN
NRSTPC0PC1PC2PC3PF2
VSSA/VREF-VREF+VDDA
PA0PA1PA2
VDDVSSPF6PA13 PA12 PA11 PA10 PA9 PA8 PC9 PC8 PC7 PC6 PD15 PD14 PD13 PD12 PD11 PD10 PD9 PD8 PB15 PB14 PB13 PB12
PA3
PF4
VD
DPA
4PA
5PA
6PA
7P
C4
PC
5P
B0
PB
1P
B2
PE
7P
E8
PE
9P
E10
PE11
PE
12P
E13
PE
14P
E15
PB
10
VS
SV
DD
VD
DV
SS
PE
1
PE
0
PB
9
PB
8
BO
OT0
P
B7
P
B6
P
B5
P
B4
P
B3
P
D7
P
D6
P
D5
P
D4
P
D3
P
D2
P
D1
P
D0
P
C12
P
C11
P
C10
PA
15
PA14
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MS40450V1
LQFP100
PC13
PF1/OSC_OUT
PB11
-
DS9911 Rev 9 35/145
STM32F302xB STM32F302xC Pinouts and pin description
54
Figure 7. STM32F302xB/STM32F302xC WLCSP100 pinout
MSv40453V1
A
B
C
D
E
F
G
H
J
K
PA2
PA3
PA5
PA4
PA7
7
BOOT0
PE0
VSS
PE3
PE6
PA8
PE12
PE11
VDD
PB2
5
PB3
PB4
PB7
PB8
PA9
PC5
PC4
PA6
PB0
PB1
6
PB5
PB6
PB9
PE2
PE8
PC6
PD9
PB15
PB12
PB10
4
PD2
PD3
PD4
PD7
PC10
PC12
PA13
PC9
PD13
PD10
PB13
PB11
3
PD0
PD1
PC11
PC7
PD14
PD11
PB14
VSS
2
VSS
PA15
PA14
VDD
PA11
PC8
PD15
PD12
VSS
VSS
1
VSS
VSS
PF6
PA12
PA10
PC2
VSSA
VREF+
VDD
PE7
8
PE1
VDD
PE4
VBAT
PF2
PF0OSCIN
PC0
PC3
VDDA
VSS
10
VDD
VDD
PC14OSC32IN
PF9
PF10
PC13
PC15OSC32OUT
NRST
PC1
PA0
PA1
VSS
PF1OSCOUT
9
VDD
PE5
-
Pinouts and pin description STM32F302xB STM32F302xC
36/145 DS9911 Rev 9
Table 12. Legend/abbreviations used in the pinout table Name Abbreviation Definition
Pin name Unless otherwise specified in brackets below the pin name, the pin function during and after reset is the same as the actual pin name
Pin type
S Supply pin
I Input only pin
I/O Input / output pin
I/O structure
FT 5 V tolerant I/O
FTf 5 V tolerant I/O, FM+ capable
TTa 3.3 V tolerant I/O directly connected to ADC
TC Standard 3.3V I/O
B Dedicated BOOT0 pin
RST Bidirectional reset pin with embedded weak pull-up resistor
Notes Unless otherwise specified by a note, all I/Os are set as floating inputs during and after reset
Pin functions
Alternate functions Functions selected through GPIOx_AFR registers
Additional functions Functions directly selected/enabled through peripheral registers
Table 13. STM32F302xB/STM32F302xC pin definitions Pin number
Pin name (function
after reset) P
in ty
pe
I/O s
truc
ture
Not
es
Pin functions
WLC
SP10
0
LQFP
100
LQFP
64
LQFP
48
Alternate functions Additional functions
D6 1 - - PE2 I/O FT (1) TRACECK, TIM3_CH1, TSC_G7_IO1, EVENTOUT -
D7 2 - - PE3 I/O FT (1) TRACED0, TIM3_CH2, TSC_G7_IO2, EVENTOUT -
C8 3 - - PE4 I/O FT (1) TRACED1, TIM3_CH3, TSC_G7_IO3, EVENTOUT -
B9 4 - - PE5 I/O FT (1) TRACED2, TIM3_CH4, TSC_G7_IO4, EVENTOUT -
E7 5 - - PE6 I/O FT (1) TRACED3, EVENTOUT WKUP3, RTC_TAMP3
D8 6 1 1 VBAT S - - Backup power supply
-
DS9911 Rev 9 37/145
STM32F302xB STM32F302xC Pinouts and pin description
54
C9 7 2 2 PC13(2) I/O TC - TIM1_CH1N WKUP2, RTC_TAMP1, RTC_TS, RTC_OUT
C10 8 3 3PC14(2)
OSC32_IN(PC14)
I/O TC - - OSC32_IN
D9 9 4 4
PC15(2) OSC32_
OUT(PC15)
I/O TC - - OSC32_OUT
D10 10 - - PF9 I/O FT (1) TIM15_CH1, SPI2_SCK, EVENTOUT -
E10 11 - - PF10 I/O FT (1) TIM15_CH2, SPI2_SCK, EVENTOUT -
F10 12 5 5PF0-
OSC_IN (PF0)
I/O FTf - TIM1_CH3N, I2C2_SDA, OSC_IN
F9 13 6 6PF1-
OSC_OUT (PF1)
I/O FTf - I2C2_SCL OSC_OUT
E9 14 7 7 NRST I/O RST Device reset input / internal reset output (active low)
G10 15 8 - PC0 I/O TTa (1) EVENTOUT ADC12_IN6
G9 16 9 - PC1 I/O TTa (1) EVENTOUT ADC12_IN7
G8 17 10 - PC2 I/O TTa (1) EVENTOUT ADC12_IN8
H10 18 11 - PC3 I/O TTa (1) TIM1_BKIN2, EVENTOUT ADC12_IN9
E8 19 - - PF2 I/O TTa (1) EVENTOUT ADC12_IN10
H8 20 12 8 VSSA/VREF- S - - Analog ground/Negative reference voltage
J8 21 - - VREF+(3) S - - Positive reference voltage
J10 22 - - VDDA S - - Analog power supply
- - 13 9 VDDA/VREF+ S - - Analog power supply/Positive reference voltage
H9 23 14 10 PA0 I/O TTa (4)USART2_CTS, TIM2_CH1_ETR, TSC_G1_IO1, COMP1_OUT, EVENTOUT
ADC1_IN1, COMP1_INM, RTC_ TAMP2, WKUP1
Table 13. STM32F302xB/STM32F302xC pin definitions (continued)Pin number
Pin name (function
after reset) P
in ty
pe
I/O s
truc
ture
Not
es
Pin functions
WLC
SP10
0
LQFP
100
LQFP
64
LQFP
48
Alternate functions Additional functions
-
Pinouts and pin description STM32F302xB STM32F302xC
38/145 DS9911 Rev 9
J9 24 15 11 PA1 I/O TTa (4)USART2_RTS_DE, TIM2_CH2, TSC_G1_IO2, TIM15_CH1N, RTC_REFIN, EVENTOUT
ADC1_IN2, COMP1_INP, OPAMP1_VINP
F7 25 16 12 PA2 I/O TTa(4)(5)
USART2_TX, TIM2_CH3, TIM15_CH1, TSC_G1_IO3, COMP2_OUT, EVENTOUT
ADC1_IN3, COMP2_INM, OPAMP1_VOUT
G7 26 17 13 PA3 I/O TTa (4)USART2_RX, TIM2_CH4, TIM15_CH2, TSC_G1_IO4, EVENTOUT
ADC1_IN4, OPAMP1_VINP, COMP2_INP, OPAMP1_VINM
- 27 18 - PF4 I/O TTa(1)(4) COMP1_OUT, EVENTOUT ADC1_IN5
K9, K10 - - - VSS S - - Digital ground
K8 28 19 - VDD S - - Digital power supply
J7 29 20 14 PA4 I/O TTa(4)(5)
SPI1_NSS, SPI3_NSS,I2S3_WS, USART2_CK, TSC_G2_IO1, TIM3_CH2, EVENTOUT
ADC2_IN1, DAC1_OUT1, COMP1_INM, COMP2_INM, COMP4_INM, COMP6_INM
H7 30 21 15 PA5 I/O TTa(4)(5)
SPI1_SCK, TIM2_CH1_ETR, TSC_G2_IO2, EVENTOUT
ADC2_IN2 OPAMP1_VINP, OPAMP2_VINM COMP1_INM, COMP2_INM, COMP4_INM, COMP6_INM
H6 31 22 16 PA6 I/O TTa(4)(5)
SPI1_MISO, TIM3_CH1, TIM1_BKIN, TIM16_CH1, COMP1_OUT, TSC_G2_IO3, EVENTOUT
ADC2_IN3, OPAMP2_VOUT
K7 32 23 17 PA7 I/O TTa (4)SPI1_MOSI, TIM3_CH2, TIM17_CH1, TIM1_CH1N, , TSC_G2_IO4, COMP2_OUT, EVENTOUT
ADC2_IN4, COMP2_INP, OPAMP2_VINP, OPAMP1_VINP
G6 33 24 - PC4 I/O TTa(1)(4) USART1_TX, EVENTOUT ADC2_IN5
F6 34 25 - PC5 I/O TTa (1) USART1_RX, TSC_G3_IO1, EVENTOUTADC2_IN11, OPAMP2_VINM, OPAMP1_VINM
J6 35 26 18 PB0 I/O TTa - TIM3_CH3, TIM1_CH2N, TSC_G3_IO2, EVENTOUT COMP4_INP, OPAMP2_VINP
Table 13. STM32F302xB/STM32F302xC pin definitions (continued)Pin number
Pin name (function
after reset) P
in ty
pe
I/O s
truc
ture
Not
es
Pin functions
WLC
SP10
0
LQFP
100
LQFP
64
LQFP
48
Alternate functions Additional functions
-
DS9911 Rev 9 39/145
STM32F302xB STM32F302xC Pinouts and pin description
54
K6 36 27 19 PB1 I/O TTa(4)(5)
TIM3_CH4, TIM1_CH3N, COMP4_OUT, TSC_G3_IO3, EVENTOUT
-
K5 37 28 20 PB2 I/O TTa - TSC_G3_IO4, EVENTOUT ADC2_IN12, COMP4_INM
F8 38 - - PE7 I/O TTa (1) TIM1_ETR, EVENTOUT COMP4_INP
E6 39 - - PE8 I/O TTa (1) TIM1_CH1N, EVENTOUT COMP4_INM
- 40 - - PE9 I/O TTa(4)(1) TIM1_CH1, EVENTOUT
- 41 - - PE10 I/O TTa (1) TIM1_CH2N, EVENTOUT
H5 42 - - PE11 I/O TTa (1) TIM1_CH2, EVENTOUT
G5 43 - - PE12 I/O TTa (1) TIM1_CH3N, EVENTOUT
- 44 - - PE13 I/O TTa (1) TIM1_CH3, EVENTOUT
- 45 - - PE14 I/O TTa(4)(1)
TIM1_CH4, TIM1_BKIN2, EVENTOUT
- 46 - - PE15 I/O TTa(4)(1)
USART3_RX, TIM1_BKIN, EVENTOUT
K4 47 29 21 PB10 I/O TTa - USART3_TX, TIM2_CH3, TSC_SYNC, EVENTOUT
K3 48 30 22 PB11 I/O TTa - USART3_RX, TIM2_CH4, TSC_G6_IO1, EVENTOUT COMP6_INP
K1, J1, K2
49 31 23 VSS S - - Digital ground
J5 50 32 24 VDD S - - Digital power supply
J4 51 33 25 PB12 I/O TTa(4)(5)
SPI2_NSS, I2S2_WS,I2C2_SMBA, USART3_CK, TIM1_BKIN, TSC_G6_IO2, EVENTOUT
J3 52 34 26 PB13 I/O TTa (4)SPI2_SCK,I2S2_CK,USART3_CTS, TIM1_CH1N, TSC_G6_IO3, EVENTOUT
J2 53 35 27 PB14 I/O TTa (4)SPI2_MISO,I2S2ext_SD,USART3_RTS_DE, TIM1_CH2N, TIM15_CH1, TSC_G6_IO4, EVENTOUT
OPAMP2_VINP
Table 13. STM32F302xB/STM32F302xC pin definitions (continued)Pin number
Pin name (function
after reset) P
in ty
pe
I/O s
truc
ture
Not
es
Pin functions
WLC
SP10
0
LQFP
100
LQFP
64
LQFP
48
Alternate functions Additional functions
-
Pinouts and pin description STM32F302xB STM32F302xC
40/145 DS9911 Rev 9
H4 54 36 28 PB15 I/O TTa (4)SPI2_MOSI, I2S2_SD, TIM1_CH3N, RTC_REFIN, TIM15_CH1N, TIM15_CH2, EVENTOUT
COMP6_INM
- 55 - - PD8 I/O TTa (1) USART3_TX, EVENTOUT
G4 56 - - PD9 I/O TTa (1) USART3_RX, EVENTOUT
H3 57 - - PD10 I/O TTa (1) USART3_CK, EVENTOUT COMP6_INM
H2 58 - - PD11 I/O TTa (1) USART3_CTS, EVENTOUT COMP6_INP
H1 59 - - PD12 I/O TTa (1)USART3_RTS_DE, TIM4_CH1, TSC_G8_IO1, EVENTOUT
G3 60 - - PD13 I/O TTa (1) TIM4_CH2, TSC_G8_IO2, EVENTOUT
G2 61 - - PD14 I/O TTa (1) TIM4_CH3, TSC_G8_IO3, EVENTOUT OPAMP2_VINP
G1 62 - - PD15 I/O TTa (1) SPI2_NSS, TIM4_CH4, TSC_G8_IO4, EVENTOUT
F4 63 37 - PC6 I/O FT (1) I2S2_MCK, COMP6_OUT TIM3_CH1, EVENTOUT -
F2 64 38 - PC7 I/O FT (1) I2S3_MCK, TIM3_CH2, EVENTOUT -
F1 65 39 - PC8 I/O FT (1) TIM3_CH3, EVENTOUT -
F3 66 40 - PC9 I/O FT (1) TIM3_CH4, I2S_CKIN, EVENTOUT -
F5 67 41 29 PA8 I/O FT -
I2C2_SMBA, I2S2_MCK, USART1_CK, TIM1_CH1, TIM4_ETR, MCO, EVENTOUT
-
E5 68 42 30 PA9 I/O FTf -
I2C2_SCL, I2S3_MCK, USART1_TX, TIM1_CH2, TIM2_CH3, TIM15_BKIN, TSC_G4_IO1, EVENTOUT
-
E1 69 43 31 PA10 I/O FTf -
I2C2_SDA, USART1_RX, TIM1_CH3, TIM2_CH4, TIM17_BKIN, TSC_G4_IO2, COMP6_OUT, EVENTOUT
-
Table 13. STM32F302xB/STM32F302xC pin definitions (continued)Pin number
Pin name (function
after reset) P
in ty
pe
I/O s
truc
ture
Not
es
Pin functions
WLC
SP10
0
LQFP
100
LQFP
64
LQFP
48
Alternate functions Additional functions
-
DS9911 Rev 9 41/145
STM32F302xB STM32F302xC Pinouts and pin description
54
E2 70 44 32 PA11 I/O FT -
USART1_CTS, USB_DM, CAN_RX, TIM1_CH1N, TIM1_CH4, TIM1_BKIN2, TIM4_CH1, COMP1_OUT, EVENTOUT
-
D1 71 45 33 PA12 I/O FT -
USART1_RTS_DE, USB_DP, CAN_TX, TIM1_CH2N, TIM1_ETR, TIM4_CH2, TIM16_CH1, COMP2_OUT, EVENTOUT
-
E3 72 46 34 PA13 I/O FT -