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10CS 33 LOGIC DESIGN UNIT – 3 Data Processing Circuits

B. S. Umashankar, BNMIT

Unit – 3

Session - 9

Data-Processing Circuits

Objectives

• Design of multiplexer circuits

• Discuss multiplexer applications

• Realization of higher order multiplexers using lower orders (multiplexer trees)

Introduction

Data-processing circuits are logic circuits that process binary data. Such circuits may be multiplexers,

demultiplexers, encoder, decoder, EX-OR gates. First we consider multiplexers.

Multiplexer

Multiplex means many into one. In digital computer networks, multiplexing is a method by which

multiple digital data streams are combined into one signal over a shared medium. A digital circuit that

performs the multiplexing of digital signals is called a multiplexer (or MUX in short). Multiplexer is a

combinational logic circuit that can select one of many inputs. Multiplexer is also called a data selector.

A simple 2-to-1 multiplexer block diagram and the switch equivalent circuit are as shown:

It has two inputs but only one output. By suitable control input or select input (sel) we can steer any

input to the output.

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10CS 33 LOGIC DESIGN


The general multiplexer block diagram is as shown below:

Design of 4-to-1 Multiplexer

The 4-to-1 multiplexer has four data inputs.

control inputs. The block diagram is as shown below:

The truth table describing the behavior of the 4


The general multiplexer block diagram is as shown below:

1 multiplexer has four data inputs. To steer the four data inputs to the output we need two

am is as shown below:

The truth table describing the behavior of the 4-to-1 multiplexer is as shown below:

Control Inputs Output

A B Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3

3 Data Processing Circuits

to the output we need two





From the truth table we obtain the logic equation

Y = A’B’D0 + A’BD1 + AB’D2 + ABD

The equation cannot be further simplified

The 74150

The 74150 is a 16-to-1 TTL multiplexer

disables or enables the multiplexer. If

The block diagram is as shown below:

The 74151

The 74151 is an 8-to-1 TTL multiplexer


From the truth table we obtain the logic equation

+ ABD3

The equation cannot be further simplified. The logic circuit realization is as shown below:

Y = A’B’D0 + A’BD1 + AB’D

TTL multiplexer. It has active low output. It has a STROBE, an input signal that

. If STROBE = 0, MUX is enabled and if STROBE = 1, MUX is disabled


1 TTL multiplexer. It has complementary outputs.


. The logic circuit realization is as shown below:

+ AB’D2 + ABD3

It has a STROBE, an input signal that

STROBE = 1, MUX is disabled.






The 74153

The 74153 is a dual 4-to-1 TTL multiplexer

multiplexer and common select lines

The 74157

The 74157 is a quad 2-to-1 TTL multiplexer IC


low:

1 TTL multiplexer. It has non-inverting outputs. It has separate enable for each

ommon select lines.

1 TTL multiplexer IC. The block diagram is as shown below:


eparate enable for each





Multiplexer Applications

Multiplexer’s important application is in sharing the circuits, ports, devices and resources

can be used in design of combinational logic circuits

Nibble Multiplexer

Nibble Multiplexer is used when we want to

nibbles, A3A2A1A0 and B3B2B1B0. The 74157 IC is used to realize the nibble multiplexer as shown below:

The control signal SELECT determines which nibble is transmitted to output

When SELECT is low, the left nibble is steered to the o

Y3Y2Y1Y0 = A3A2A1A0

When SELECT is high, the right nibble is steered to the output.

Y3Y2Y1Y0 = B3B2B1B0

Multiplexer Logic

We can use multiplexer to realize a given

because a 2n-to-1 multiplexer can be used to design solution for any n

Example 1:

Realize Y = A’B + B’C’ + ABC using an 8

Solution:

First we express Y in canonical SOP form


Multiplexer’s important application is in sharing the circuits, ports, devices and resources

can be used in design of combinational logic circuits.

Nibble Multiplexer is used when we want to select one of two input nibbles. Consider the two input

The 74157 IC is used to realize the nibble multiplexer as shown below:

The control signal SELECT determines which nibble is transmitted to output. STROBE input is

When SELECT is low, the left nibble is steered to the output. We have,

nibble is steered to the output. We have,

We can use multiplexer to realize a given Boolean equation. Multiplexer is called universal logic circuit

1 multiplexer can be used to design solution for any n-variable truth table

using an 8-to-1 multiplexer

in canonical SOP form


Multiplexer’s important application is in sharing the circuits, ports, devices and resources. Multiplexers

. Consider the two input

The 74157 IC is used to realize the nibble multiplexer as shown below:

STROBE input is made 0.

Multiplexer is called universal logic circuit

variable truth table.





Y = A’B + B’C’ + ABC

= A’B.1 + 1.B’C’ + ABC

= A’B.(C’ + C) + (A’ + A).B’C’ + ABC

= A’BC’ + A’BC + A’B’C’ + AB’C’ + ABC

= Σ m (2, 3, 0, 4, 7)

= Σ m (0, 2, 3, 4, 7)

Consider the 8-to-1 multiplexer truth table as shown below:

A B C Y

0 0 0 D0

0 0 1 D1

0 1 0 D2

0 1 1 D3

1 0 0 D4

1 0 1 D5

1 1 0 D6

1 1 1 D7

From the truth table we have,

Y = A’B’C’D0 + A’B’CD1 + A’BC’D2 + A’BCD3 + AB’C’D4 + AB’CD5 + ABC’D6 + ABCD7

Y = moD0 + m1D1 + m2D2 + m3D3 + m4D4 + m5D5 + m6D6 + m7D7

The given equation is Y = f(A, B, C) = Σ m (0, 2, 3, 4, 7). The variables A, B, & C are used as select inputs.

Comparing multiplexer output expression with the given logic equation in canonical SOP form we find by

substituting D0 = D2 = D3 = D4 = D7 = 1 and D1 = D5 = D6 = 0 we have the realization as shown.





The truth table for the given logic equation is shown below:

Example 2:

Realize Y = A’B + B’C’ + ABC using 4-

Solution:

We consider variables A and B as selector

input. Given logic equation Y = A’B + B’C’ + ABC in canonical form

is as shown.


The truth table for the given logic equation is shown below:

A B C Y

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

-to-1 multiplexer.

as selector inputs in 4-to-1 multiplexer and variable C in given as data

Given logic equation Y = A’B + B’C’ + ABC in canonical form is Y= Σ m (0, 2, 3, 4, 7)


1 multiplexer and variable C in given as data

m (0, 2, 3, 4, 7). The truth table





A B C Y

0 0 0 1

0 0 1 0

0 1 0 1

0 1 1 1

1 0 0 1

1 0 1 0

1 1 0 0

1 1 1 1

Similar to procedure adopted in entered variable map, output Y is written in terms of variable C.

A B C Y Y

0 0 0 1 C’

0 0 1 0

0 1 0 1 1

0 1 1 1

1 0 0 1 C’

1 0 1 0

1 1 0 0 C

1 1 1 1

Comparing with equation of 4-to-1 multiplexer we see

D0 = C’

D1 = 1

D2 = C’

D3 = C

generate the given logic function.





The given logic equation is realized using the 4

Example 3:

Realize Y = Σ m(0, 2, 3, 4 ,5, 8, 9, 10, 11, 12, 13, 15) using 8

Solution:

The truth table for the given expression is as shown below:


The given logic equation is realized using the 4-to-1 multiplexer as shown below:

A B Y

0 0 C’

0 1 1

1 0 C’

1 1 C

m(0, 2, 3, 4 ,5, 8, 9, 10, 11, 12, 13, 15) using 8-to-1 multiplexer.

The truth table for the given expression is as shown below:






The logic expression is realized using 8

Multiplexer Trees

A number of m-to-1 multiplexers can be arranged in tree topology to obtain a bigger n

(n > m).

Example 1:

Design a 4-to-1 multiplexer using 2

Solution:

The 2-to-1 multiplexer truth table is as

Two units of 2-to-1 multiplexers are used together to realize 4 inputs, and another unit of 2

multiplexer is used to steer the inputs to a single output. The multiplexer tree is realized as shown:


The logic expression is realized using 8-to-1 multiplexer as shown below:

1 multiplexers can be arranged in tree topology to obtain a bigger n

1 multiplexer using 2-to-1 multiplexers.

1 multiplexer truth table is as shown:

1 multiplexers are used together to realize 4 inputs, and another unit of 2


A B Y

0 0 D0

0 1 D1

1 0 D2

1 1 D3


-to-1 multiplexer

1 multiplexers are used together to realize 4 inputs, and another unit of 2-to-1






Example 2:

Design a 32-to-1 multiplexer using two 16

Solution:

Questions

1. What is a multiplexer? Design 4

2. Implement the given Boolean function by using

f(A, B, C, D) = ∑m(0, 1, 3, 5, 7, 11, 12, 13, 14)


1 multiplexer using two 16-to-1 multiplexers and one 2-to-1 multiplexer

1. What is a multiplexer? Design 4-to-1 multiplexer and implement using gates.

2. Implement the given Boolean function by using 8:1 multiplexer.

∑m(0, 1, 3, 5, 7, 11, 12, 13, 14)


1 multiplexer.





3. Realize the Boolean expression f(w, x, y, z) = ∑m(4, 6, 7, 8, 10, 12, 15) using a 4 to 1 line multiplexer

and external gates.

4. Write the truth table of a 4-bit Binary to Gray code converter and realize the same using four 74151

ICs (8-to-1 multiplexer).

5. Show how two 1-to-16 demultiplexers can be connected to get a 1-to-32 demultiplexer.

6. Design a 32-to-1 multiplexer using two 16-to-1 multiplexer and one 2-to-1 multiplexer.



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