csc258: computer organization microarchitecturepeters43/258/lectures/w8/... · 2 wednesday, march...

CSC258: Computer Organization

Microarchitecture

1

Wednesday, March 4, 2015

Clear your desk!

• Please protect your work.

• Keep your own eyes on your paper or stare up to the sky.

• When you’re done, fold your paper with the answer inside.

• Please write legibly.

• I have awful handwriting, too, but that doesn’t help me read bad handwriting.

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Week 8 Quiz

1. (2 points) Design a greater-than-or-equal-to comparator for 32-bit numbers. You may use any combinational building block (adders, logic gates, muxes or demuxes) that you wish except for another comparator. Sketch the schematic for your comparator.

2. In one sentence, succinctly define the role of the datapath of a processor.

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Administrivia

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CUPE 3902 Unit 1 on Strike

• The goal is to minimize impact on you.

• There will have to be some changes.

• Labs will be running with only one TA in support. (As far as I know.)

• Marking will be delayed.

• Please see the discussion board for details.

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Why Continue the Labs?

• Anonymous has been very concerned about the labs running without support or with reduced support.

• My stance: It’s better, in terms of providing opportunities to learn the material, to have a reduced lab than to have no lab.

• Let’s do a thought experiment:If we had a snow day EVERY Monday, so we never got to meet for lecture, what would be on the final exam? Would it be blank? Would it look like the final exam from last year?

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Why Continue the Labs?

• Anonymous has been very concerned about the labs running without support or with reduced support.

• My stance: It’s better, in terms of providing opportunities to learn the material, to have a reduced lab than to have no lab.

• This course has established content. You’re responsible for knowing the material, lab or no lab, and the labs provide hands-on experience, which can only help.

• Trust me on lab marks. Assessment has focused on effort and preparation and will continue to do so.

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CUPE 3902 Unit 1 on Strike

• The goal is to minimize impact on you.

• There will have to be some changes.

• Labs will be running with only one TA in support.

• Marking will be delayed.

• Please see the discussion board for details.

8


No Friday Office Hours

• I am scheduled to be out of the office at a particularly unfortunate time.

• There are no office hours on Friday, March 6.

• ... and I can’t check in on the labs on the Mar 4-5.

• I will be checking the discussion board frequently.

• If you need to meet, please send me an email, and we can set up a skype chat.

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Anonymous

• “I am mainly writing you this feedback because I can't seem to find motivation to do any CSC258 work; I'm hoping that getting some of my thoughts out via feedback would help.”

• If this is you (or it feels like you) or if you feel you didn’t do well on the midterm, we should talk.

• Drop me an email or drop by outside of office hours.

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Microarchitecture

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Key Questions

• Do I understand the datapath of the ALU in figure 5.15?

• What is the difference between data and control?

• How do I compute the performance of a processor?

• Do I understand the development of the single-cycle MIPS datapath?

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ALU Schematic: Figure 5.15

from DDCA

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The Processor from Lab

• This circuit is a FSM.

• The state is the register file.

• The ALU provides flexible computation.

• What is control?

• And where does the data go?

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Control: Instruction Fetch and Decode• The instruction decoder is fed instructions one at a

time.

• It outputs the control necessary to make the processor execute the user’s instruction.

• In essence, it’s a very fancy decoder.

• It could even be a FSM in its own right: some instructions are microcoded to be implemented by more than one smaller instruction.

• But where do the instructions come from and what do they look like?

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Control: Instruction Fetch and Decode• The instruction decoder is fed instructions one at a

time.

• It outputs the control necessary to make the processor execute the user’s instruction.

• In essence, it’s a very fancy decoder.

• It could even be a FSM in its own right: some instructions are microcoded to be implemented by more than one smaller instruction.

• But where do the instructions come from and what do they look like?

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Instructions? From where?

• Instructions are encoded in binary. The compiler tool chain translates a user’s program into machine code.

• The program (in machine code form) is stored in memory.

• Memory is a very large storage device. It contains the program as well as data created as the program runs.

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0x08048000

Stack

0x40000000

Code (Text Segment)

Static Data (Data Segment)

Heap(created at runtime by malloc)User

Addresses

SP

PC

Kernel virtual memory0xC0000000

0xFFFFFFFF

Memory mapped regionfor shared libraries

Unused0x0

brk

Memory Layout (Linux, x86)


The Stack and Heap

• Memory contains two structures that the program can use for extra storage: the stack and heap.

• The pointer to the top of the stack is contained in a hardware register: the stack pointer (SP)

• It is the program’s responsibility to manage the stack.

• Whenever stack space is allocated, it should be deallocated later by the same function

• The operating system manages heap allocation.

• Whenever you malloc, you’re getting heap space.19


Instructions and Data

• Everything in memory is stored in binary.

• There is no good way to determine if an arbitrary binary word is data ... or an instruction.

• Many hacks use this to their advantage.

• This is actually a feature, not a bug. It means that we can treat instructions and data in the same way.

• They’re both data ... we just use instructions to run the machine.

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Single-Cycle MIPS (Credit: DDCA)

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Key Questions

• Do I understand the datapath of the ALU in figure 5.15?

• What is the difference between data and control?

• How do I compute the performance of a processor?

• Do I understand the development of the single-cycle MIPS datapath?

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Executing an “Immediate” Instruction(Credit: DDCA)

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Executing with Two Registers as Inputs (Credit: DDCA)

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Determining the Next Instruction(Credit: DDCA)

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Executing a Program

• First, load the program into memory.

• Set the program counter (PC) to the first instruction in memory and set the SP to the first empty space on the stack

• Let instruction fetch/decode do the work! The processor can control what instruction is executed next.

• When the process needs support from the operating system (OS), it will “trap” (“throw an exception”)

• Traps include “print” and “halt”26


Single-Cycle MIPS (Credit: DDCA)

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csc258: computer organization microarchitecturepeters43/258/lectures/w8/... · 2 wednesday, march...

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