cs61c l21 pipelining i (1) chae, summer 2008 © ucb albert chae, instructor...

CS61C L21 Pipelining I (1) Chae, Summer 2008 © UCB

Albert Chae, Instructor

inst.eecs.berkeley.edu/~cs61c CS61C : Machine Structures

Lecture #21 – Pipelining I

2008-7-28Minesweeper circuits

http://www.claymath.org/Popular_Lectures/Minesweeper/

http://for.mat.bham.ac.uk/R.W.Kaye/minesw/ASE2003.pdf


°5 steps to design a processor• 1. Analyze instruction set datapath requirements• 2. Select set of datapath components & establish clock

methodology• 3. Assemble datapath meeting the requirements• 4. Analyze implementation of each instruction to

determine setting of control points that effects the register transfer.

• 5. Assemble the control logic

°Control is the hard part°MIPS makes that easier

• Instructions same size• Source registers always in same place• Immediates same size, location• Operations always on registers/immediates

Review: Single cycle datapath

Control

Datapath

Memory

ProcessorInput

Output


RegDst = add + subALUSrc= ori + lw + swMemtoReg = lwRegWrite = add + sub + ori + lwMemWrite = swnPCsel = beqJump = jump ExtOp = lw + swALUctr[0] = sub + beq (assume ALUctr is 0 ADD, 01: SUB, 10: OR)ALUctr[1] = or

where,

rtype = ~op5 ~op4 ~op3 ~op2 ~op1 ~op0, ori = ~op5 ~op4 op3 op2 ~op1 op0

lw = op5 ~op4 ~op3 ~op2 op1 op0

sw = op5 ~op4 op3 ~op2 op1 op0

beq = ~op5 ~op4 ~op3 op2 ~op1 ~op0

jump = ~op5 ~op4 ~op3 ~op2 op1 ~op0

add = rtype func5 ~func4 ~func3 ~func2 ~func1 ~func0

sub = rtype func5 ~func4 ~func3 ~func2 func1 ~func0

With control breaking apart code to run on the datapath, what does this

mean?

addsuborilwswbeqjump

RegDstALUSrcMemtoRegRegWriteMemWritenPCselJumpExtOpALUctr[0]ALUctr[1]

“AND” logic “OR” logic

opcode func

How We Build The Controller


lw $t0, 0($2)lw $t1, 4($2)sw $t1, 0($2)sw $t0, 4($2)

High Level Language Program (e.g., C)

Assembly Language Program (e.g.,MIPS)

Machine Language Program (MIPS)

Hardware Architecture Description (e.g., block diagrams)

Compiler

Assembler

Machine Interpretation

temp = v[k];

v[k] = v[k+1];

v[k+1] = temp;

0000 1001 1100 0110 1010 1111 0101 10001010 1111 0101 1000 0000 1001 1100 0110 1100 0110 1010 1111 0101 1000 0000 1001 0101 1000 0000 1001 1100 0110 1010 1111

Logic Circuit Description(Circuit Schematic Diagrams)

Architecture Implementation

Call home, we’ve made HW/SW contact!


An Abstract View of the Critical Path Critical Path (Load Instruction) =

Delay clock through PC (FFs) + Instruction Memory’s Access Time + Register File’s Access Time, + ALU to Perform a 32-bit Add + Data Memory Access Time + Stable Time for Register File Write

clk

5

Rw Ra Rb

RegisterFile

Rd

Data In

DataAddr Ideal

DataMemory

Instruction

InstructionAddress

IdealInstruction

Memory

PC

5Rs

5Rt

32

323232

A

B

Nex

t A

dd

ress

clk clk

AL

U(Assumes a fast controller)


Processor Performance

• Can we estimate the clock rate (frequency) of our single-cycle processor? We know:

• 1 cycle per instruction•lw is the most demanding instruction.

• Assume approximate delays for major pieces of the datapath:

- Instr. Mem, ALU, Data Mem : 2ns each, regfile 1ns

- Instruction execution requires: 2 + 1 + 2 + 2 + 1 = 8ns

125 MHz

• What can we do to improve clock rate?

• Will this improve performance as well?• We want increases in clock rate to result in programs

executing quicker.


Ways to Improve Clock Frequency

• Smaller Process Size• Smallest feature possible in silicon fabrication• Smaller process is faster because of EE

reasons, and is smaller so things are closer

• Optimize Logic• Re-arrange CL to be faster• Sometimes more logic (more hardware) can be

used to reduce delay

• Parallel• Do more at once - later…

• Cut Down Length of Critical Path• Inserting registers (pipelining) to break up CL


Gotta Do Laundry

° Ann, Brian, Cathy, Dave each have one load of clothes to wash, dry, fold, and put away

A B C D

° Dryer takes 30 minutes

° “Folder” takes 30 minutes

° “Stasher” takes 30 minutes to put clothes into drawers

° Washer takes 30 minutes


Sequential Laundry

• Sequential laundry takes 8 hours for 4 loads

Task

Order

B

C

D

A

30Time

3030 3030 30 3030 3030 3030 3030 3030

6 PM 7 8 9 10 11 12 1 2 AM


Pipelined Laundry

• Pipelined laundry takes 3.5 hours for 4 loads!

Task

Order

B

C

D

A

12 2 AM6 PM 7 8 9 10 11 1

Time303030 3030 3030


General Definitions• Latency: time to completely execute a certain task (delay)

• for example, time to read a sector from disk is disk access time or disk latency

• Throughput: amount of work that can be done over a period of time (rate)


Pipelining Lessons (1/2)

• Pipelining doesn’t help latency of single task, it helps throughput of entire workload

• Multiple tasks operating simultaneously using different resources

• Potential speedup = Number pipe stages

• Time to “fill” pipeline and time to “drain” it reduces speedup:2.3X v. 4X in this example

6 PM 7 8 9

Time

B

C

D

A

303030 3030 3030Task

Order


Pipelining Lessons (2/2) • Suppose new

Washer takes 20 minutes, new Stasher takes 20 minutes. How much faster is pipeline?

• Pipeline rate limited by slowest pipeline stage

• Unbalanced lengths of pipe stages reduces speedup

6 PM 7 8 9

Time

B

C

D

A

303030 3030 3030Task

Order


Steps in Executing MIPS1) IFtch: Instruction Fetch, Increment PC

2) Dcd: Instruction Decode, Read Registers

3) Exec: Mem-ref: Calculate Address Arith-log: Perform Operation

4) Mem: Load: Read Data from Memory Store: Write Data to Memory

5) WB: Write Data Back to Register


Pipelined Execution Representation

• Every instruction must take same number of steps, also called pipeline “stages”, so some will go idle sometimes

IFtch Dcd Exec Mem WB






Time


Review: Datapath for MIPS

• Use datapath figure to represent pipelineIFtch Dcd Exec Mem WB

AL

U I$ Reg D$ Reg

PC

inst

ruct

ion

me

mor

y+4

rtrs

rd

regi

ste

rs

ALU

Da

tam

em

ory

imm

1. InstructionFetch

2. Decode/ Register Read

3. Execute 4. Memory5. Write

Back


Graphical Pipeline Representation

Instr.

Order

Load

Add

Store

Sub

Or

I$

Time (clock cycles)

I$

AL

U

Reg

Reg

I$

D$

AL

U

AL

U

Reg

D$

Reg

I$

D$

RegA

LU

Reg Reg

Reg

D$

Reg

D$

AL

U

(In Reg, right half highlight read, left half write)

Reg

I$


Example

• Suppose 2 ns for memory access, 2 ns for ALU operation, and 1 ns for register file read or write; compute instr rate

• Nonpipelined Execution:•lw : IF + Read Reg + ALU + Memory + Write Reg = 2 + 1 + 2 + 2 + 1 = 8 ns•add: IF + Read Reg + ALU + Write Reg = 2 + 1 + 2 + 1 = 6 ns (recall 8ns for single-cycle processor)

• Pipelined Execution:• Max(IF,Read Reg,ALU,Memory,Write Reg) = 2 ns


Administrivia

• HW5 due Tuesday 7/29

• Quiz9 due Wednesday 7/30

• HW6 due Friday 8/1

• Proj3 out soon, due next Tuesday 8/5• Will be hand graded in person, signups will be posted soon

• Midterm regrades due 7/29

• Proj1 grades out, proj2 hopefully soon• appeals due 7/31


Administrivia• Lab on polling/interrupts is cancelled

• We will give everyone 4 pts on that lab

• Drop or grading option deadline• August 1

• summer.berkeley.edu for more details


Pipeline Hazard: Matching socks in later load

A depends on D; stall since folder tied up

Task

Order

B

C

D

A

E

F

bubble

12 2 AM6 PM 7 8 9 10 11 1

Time303030 3030 3030


Problems for Pipelining CPUs

• Limits to pipelining: Hazards prevent next instruction from executing during its designated clock cycle

• Structural hazards: HW cannot support some combination of instructions (single person to fold and put clothes away)

• Control hazards: Pipelining of branches causes later instruction fetches to wait for the result of the branch

• Data hazards: Instruction depends on result of prior instruction still in the pipeline (missing sock)

• These might result in pipeline stalls or “bubbles” in the pipeline.


Structural Hazard #1: Single Memory (1/2)

Read same memory twice in same clock cycle

I$

Load

Instr 1

Instr 2

Instr 3

Instr 4A

LU I$ Reg D$ Reg

AL

U I$ Reg D$ Reg

AL

U I$ Reg D$ RegA

LUReg D$ Reg

AL

U I$ Reg D$ Reg

Instr.

Order

Time (clock cycles)


Structural Hazard #1: Single Memory (2/2)• Solution:

• infeasible and inefficient to create second memory

• (We’ll see more later this week)

• so simulate this by having two Level 1 Caches (a temporary smaller [of usually most recently used] copy of memory)

• have both an L1 Instruction Cache and an L1 Data Cache

• need more complex hardware to control when both caches miss


Structural Hazard #2: Registers (1/2)

Can we read and write to registers simultaneously?

I$

sw

Instr 1

Instr 2

Instr 3

Instr 4A

LU I$ Reg D$ Reg

AL

U I$ Reg D$ Reg

AL

U I$ Reg D$ RegA

LUReg D$ Reg

AL

U I$ Reg D$ Reg

Instr.

Order

Time (clock cycles)


Structural Hazard #2: Registers (2/2)• Two different solutions have been used:

1) RegFile access is VERY fast: takes less than half the time of ALU stage

- Write to Registers during first half of each clock cycle

- Read from Registers during second half of each clock cycle

2) Build RegFile with independent read and write ports

• Result: can perform Read and Write during same clock cycle


Data Hazards (1/2)

add $t0, $t1, $t2

sub $t4, $t0 ,$t3

and $t5, $t0 ,$t6

or $t7, $t0 ,$t8

xor $t9, $t0 ,$t10

• Consider the following sequence of instructions


Data-flow backward in time are hazards

Data Hazards (2/2)

sub $t4,$t0,$t3

AL

UI$ Reg D$ Reg

and $t5,$t0,$t6

AL

UI$ Reg D$ Reg

or $t7,$t0,$t8 I$

AL

UReg D$ Reg

xor $t9,$t0,$t10

AL

UI$ Reg D$ Reg

add $t0,$t1,$t2IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg

Instr.

Order

Time (clock cycles)


• Forward result from one stage to another

Data Hazard Solution: Forwarding

sub $t4,$t0,$t3

AL

UI$ Reg D$ Reg

and $t5,$t0,$t6A

LUI$ Reg D$ Reg

or $t7,$t0,$t8 I$

AL

UReg D$ Reg

xor $t9,$t0,$t10

AL

UI$ Reg D$ Reg

add $t0,$t1,$t2IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg

“or” hazard solved by register hardware


• Dataflow backwards in time are hazards

Data Hazard: Loads (1/4)

sub $t3,$t0,$t2A

LUI$ Reg D$ Reg

lw $t0,0($t1)IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg

• Can’t solve all cases with forwarding• Must stall instruction dependent on load, then forward (more hardware)


• Hardware stalls pipeline• Called “interlock”


sub $t3,$t0,$t2A

LUI$ Reg D$ Reg

bubble

and $t5,$t0,$t4

AL

UI$ Reg D$ Regbubble

or $t7,$t0,$t6 I$

AL

UReg D$bubble

lw $t0, 0($t1)IF ID/RF EX MEM WBA

LUI$ Reg D$ Reg



• Instruction slot after a load is called “load delay slot”

• If that instruction uses the result of the load, then the hardware interlock will stall it for one cycle.

• If the compiler puts an unrelated instruction in that slot, then no stall

• Letting the hardware stall the instruction in the delay slot is equivalent to putting a nop in the slot (except the latter uses more code space)


Data Hazard: Loads (4/4)• Stall is equivalent to nop

sub $t3,$t0,$t2

and $t5,$t0,$t4

or $t7,$t0,$t6 I$

AL

UReg D$

lw $t0, 0($t1)

AL

UI$ Reg D$ Reg

bubble

bubble

bubble

bubble

bubble

AL

UI$ Reg D$ Reg

AL

UI$ Reg D$ Reg

nop


Historical Trivia

• First MIPS design did not interlock and stall on load-use data hazard

• Real reason for name behind MIPS: Microprocessor without Interlocked Pipeline Stages

• Word Play on acronym for Millions of Instructions Per Second, also called MIPS


Peer Instruction

A. Thanks to pipelining, I have reduced the time it took me to wash my shirt.

B. Longer pipelines are always a win (since less work per stage & a faster clock).

C. We can rely on compilers to help us avoid data hazards by reordering instrs.

ABC0: FFF1: FFT2: FTF3: FTT4: TFF5: TFT6: TTF7: TTT


Peer Instruction Answer

A. Thanks to pipelining, I have reduced the time it took me to wash my shirt.

B. Longer pipelines are always a win (since less work per stage & a faster clock).

C. We can rely on compilers to help us avoid data hazards by reordering instrs.

F A L S EF A L S E

A. Throughput better, not execution time

B. “…longer pipelines do usually mean faster clock, but branches cause problems!

C. “they happen too often & delay too long.” Forwarding! (e.g, Mem ALU)

F A L S E

ABC0: FFF1: FFT2: FTF3: FTT4: TFF5: TFT6: TTF7: TTT


Things to Remember• Optimal Pipeline

• Each stage is executing part of an instruction each clock cycle.

• One instruction finishes during each clock cycle.

• On average, execute far more quickly.

• What makes this work?• Similarities between instructions allow us to use same stages for all instructions (generally).

• Each stage takes about the same amount of time as all others: little wasted time.

cs61c l21 pipelining i (1) chae, summer 2008 © ucb albert chae, instructor...

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