computer organization lab

Computer Organization Lab, Department of ECE, K L University 13EM201

B.Tech IVth

Year, Semester VII, 2014-2015

Computer Organization Lab Experiments List

List of Experiments intended as basic experiments of the course:-

1) Design of Carry-Look-Ahead Adder

2) Implementation of Boolean expressions using multiplexers

3) Design of 4-bit Universal shift register using D-FF

4) Design of 4-bit ALU

5) Design of combinational multiplier

List of Experiments supposed to finish in Open Lab Sessions:-

6) Design of Ripple carry Adder

7) Design of logic circuit to implement 10’s complement of BCD

8) Design of Associative Cache memory

9) Design of 4X4 RAM cell

10) Design of Booth’s multiplier

Few Sample Project Ideas:-

1) Design of 1:16 demultiplexer using 1:8 and 1:4 demultiplexers

2) 9-bit odd/even parity generator/checker

3) Design of mod-16 synchronous counter using T-FF

4) Design of 8 bit Divider circuit

5) 4 bit odd/even sequence generator using JK-FF

6) Implementation of full adder using PLA having 3 I/P’s, 8 product terms and two O/P’s

7) Design of 8X4 bit ROM using MOSFET’s

8) Design of 2KX8 memory using two 1KX8 IC’s

9) Design and Implementation of UART.

10) Design and Implementation of FIFO.

11) Design a Melay FSM to generate sequence of Odd Numbers [0001, 0011…1111] and

Implement using FPGA.

12) Design a FSM for Traffic Light Controller.

13) Design and Interface of LIFO & FILO with 2x1 Multiplexer and Implement using

FPGA.

14) Design and Implementation of Serial in Parallel out Register.

15) Design a Shift Register which shifts the given Input Sequence either Left or Right using

Mode Control.

16) Design and Implementation of Carry Look Ahead Adder using CPLD.

17) Design and Implementation of Hamming Error Detection Techniques.

18) Design and Implementation of Digital Clock Using Seven Segment Display.

19) Design and Interface Binary to Gray & Gray to Binary Code Converters with 2x1

Multiplexer and Implement using FPGA.

20) Design a 2 to 4 Decoder and Interface with Seven Segment Display and Implement using

FPGA.

Objectives:

The Objective is to expose the students to the various key aspects of Computer Organisation &

Architecture by enabling them to perform FPGA based prototyping of experiments with support of a

design and simulation in Logisim and Xilinx.

Learning Objectives:

1. Design concepts implementation and model development using the Logisim tool.

2. Logical programming knowledge improvement through active HDL and Xilinx tools.

3. Application verification by dumping program in FPGA’s and testing the workbench.

4. Hardware implementation based on the knowledge gained by the student

Pre-requisites:

1. Basic knowledge regarding digital logic design

2. Basic knowledge regarding memory organization

3. Awareness regarding any simulation tool

4. Awareness regarding any programming language like ‘C’

5. Disciplined learning with positive attitude.

The execution of project based lab planned in two phases:-

Phase I: Experiments Based: First six weeks student need to work out and execute the list of

programs /experiments as decided by the instructor. These lists of programs /Experiments must cover

all the basics required to implement any project in the concerned course.

Phase II: Project Based: After six weeks student needs to work out on the project on the concerned

course designed by faculty or he/she may be allowed to do implement his/her own idea in the

concerned course.

Proposed Dates:-

09/07/2014 to 16/08/2014:- Overview and Basic Experiments of the Lab

18/08/2014 to 23/08/2014:- Abstracts collection and ZEROth review

Third week of September, 2014:- First review

Second week of October, 2014:- Second review

Last week of October, 2014:- Final review

Assessment Approach:-

The Project based Lab will be undertaken through External and Internal evaluation. The following

Table reflects various evaluation components that will be used to assess the performance of the

students.

Type of

Evaluation

Max Marks

allocated

Evaluation

component

Marks

allocated

Subdivision of

the evaluation

component

Marks

Allocated

External

Evaluation 60

End Semester

External

evaluation

60

Report 20

Viva Voce 20

Execution 10

*Demonstration 10

Internal

Evaluation 40

Attendance 05 - 5

Continuous

Assessment 15

Viva Voce 10

Record 05

End Semester

Internal

examination 20

Report 5

Viva Voce 5

Execution 5

Demonstration 5

*A part of the project work done should be assessed in the End Semester External evaluation to

identify the capability of the student “Hands on experience &Practical knowledge” gained in the Lab.

No student of the same batch (project based lab experiment batch) shall be tested by allotting the same

experiment.

Signature of course coordinator Signature of HOD

1. Design of Carry-Look-Ahead Adder

Aim: - To design Carry-Look-Ahead Adder using Logisim and simulate the operation.

Tools required: - Logisim

Objective: - 1. Understanding behaviour of carry look ahead adder from module designed by the

student as part of the experiment

2. Understanding the concept of reducing computation time with respect of ripple carry adder by

using carry generate and propagate functions

3. The adder will add two 4 bit numbers

Theory:-

To reduce the computation time, there are faster ways to add two binary numbers by using carry look

ahead adders. They work by creating two signals P and G known to be Carry Propagator and Carry

Generator. The carry propagator is propagated to the next level whereas the carry generator is used to

generate the output carry, regardless of input carry. The block diagram of a 4-bit Carry Look ahead

Adder is shown here below -

The number of gate levels for the carry propagation can be found from the circuit of full adder. The

signal from input carry Cin to output carry Cout requires an AND gate and an OR gate, which

constitutes two gate levels. So if there are four full adders in the parallel adder, the output carry C5

would have 2 X 4 = 8 gate levels from C1 to C5. For an n-bit parallel adder, there are 2n gate levels to

propagate through.

Design Issues:

The corresponding Boolean expressions are given here to construct a carry look ahead adder. In the

carry-look ahead circuit we need to generate the two signals carry propagator (P) and carry generator

(G),

Pi = Ai ⊕ Bi

Gi = Ai · Bi

The output sum and carry can be expressed as

Sumi = Pi ⊕ Ci

Ci+1 = Gi + ( Pi · Ci)

Having these we could design the circuit. We can now write the Boolean function for the carry output

of each stage and substitute for each Ci its value from the previous equations:

C1 = G0 + P0 · C0

C2 = G1 + P1 · C1 = G1 + P1 · G0 + P1 · P0 · C0

C3 = G2 + P2 · C2 = G2 P2 · G1 + P2 · P1 · G0 + P2 · P1 · P0 · C0

C4 = G3 + P3 · C3 = G3 P3 · G2 P3 · P2 · G1 + P3 · P2 · P1 · G0 + P3 · P2 · P1 · P0 · C0

Circuit Diagram:-

Procedure:-

To insert a logic gate, expand the folder Gates and click on the desired logic gate.

Once the gate is selected, the mouse will turn into the shape of the selected gate.

Place the gate in the circuit area on the right.

To connect the gates, select the arrow icon on to p ( ).

Then drag from the output of one gate to the input of another gate.

You can connect to any of the small blue dots on the gate symbol.

To create an input to the circuit, select the “Add Pin” icon with an outline of a square ( ).

Similarly, add an output to the circuit by using the “Add Pin” icon with an outline of a circle

( ).

To assign a name to the input/output pin, click on the pin while the arrow icon ( ) is selected.

You may then add the label for the pins.

Once you have connected the circuit, you will notice the color of the wire changes.

A dark green color means that the current value on the wire is a logical ‘0’, while a light green color

signifies a ‘1’.

Other wire colours: blue = unknown value, gray = unconnected, red = conflict.

Observations and Result:

2. Implementation of Boolean expressions using Multiplexers

Aim:- To design a scheme to implement Boolean expression with help of multiplexer using Logisim

and simulate the operation


Objective:-

To observe Multiplexer active one output pin is also Boolean function with literal variables at the

channel select pins and each input corresponding to one min term . For n terms, use '' n'' input lines

= 1 0r 0 at multiplexer and m-input channel select pins for ''m ''literals of an SOP Boolean function .

Theory:-

While Multiplexers are primarily thought of as “data selectors” because they select one of several

Inputs to be logically connected to the output, they can also be used to implement Boolean functions.

Similarly, while n-bit Decoders are primarily thought of as n-bit binary to 1 of 2n code converters or

as Demultiplexers, they can also be used to implement Boolean functions of n variables. Consider the

following truth table that describes a function of 4 Boolean variables. A 16 to 1 Multiplexer with A,

B,C, and D applied to its S3, S2, S1, and S0 inputs respectively would select one of its 16 inputs for

each of the 16 possible combinations of A, B,C, and D. We can implement the function described by

the truth table by connecting a voltage source for logic level 1 or ground for a logic level 0 to each of

the Multiplexer inputs corresponding to the required value of the function associated with the

combination of A, B, C, and D that selected the input. Therefore, the inputs to the Multiplexer will be

the same as the F entries in the truth table provided A, B,C, and D are connected to the Multiplexer

select inputs in the right order.

Circuit Diagram:-

Procedure:-

The design procedure of a combinational logic circuit using multiplexers is as follows.

1. Identify the decimal number corresponding to each min term in the expression.

2. The input lines corresponding to these numbers are to be connected to logic 1 level and all other

input lines are connected to logic 0.

3. Then the select inputs are to be applied to the select lines.

Using Logisim, to insert a logic gate, expand the folder Gates and click on the desired logic gate.








( ).

To assign a name to the input/output pin, click on the pin while the arrow icon ( ) is selected.



A dark green color means that the current value on the wire is a logical ‘0’, while a light green color

signifies a ‘1’.



3. Design of 4-bit Universal Shift Register using D-FF

Aim: - To design a 4-bit unidirectional shift register using D-flip-flops using logisim and

simulate the operation of the same.


Objective:-

The Shift Register is another type of sequential logic circuit that is used for the storage or

transfer of data in the form of binary numbers. To understand the behaviour and flow of data

is the objective of this experiment.

Theory:-

The Shift Register is a type of sequential logic circuit that is used for the storage or

transfer of data in the form of binary numbers. This sequential device loads the data present

on its inputs and then moves or “shifts” it to its output once every clock cycle, hence the

name “shift register”. A shift register basically consists of several single bit “D-Type Data

Latches”, one for each data bit, either a logic “0” or a “1”, connected together in a serial or

daisy-chain arrangement so that the output from one data latch becomes the input of the next

latch and so on. The data bits may be fed in or out of a shift register serially, that is one after

the other from either the left or the right direction, or all together at the same time in parallel.

The number of individual data latches required to make up a single Shift Register device is

usually determined by the number of bits to be stored with the most common being 8-bits

(one byte) wide constructed from eight individual data latches.

The Shift Register is used for data storage or data movement and are used in calculators or

computers to store data such as two binary numbers before they are added together, or to

convert the data from either a serial to parallel or parallel to serial format. The individual data

latches that make up a single shift register are all driven by a common clock (Clk) signal

making them synchronous devices.

Shift register IC’s are generally provided with a clear or reset connection so that they can be

“SET” or “RESET” as required.

The effect of data movement from left to right through a shift register can be presented

graphically as:

Also, the directional movement of the data through a shift register can be either to the left,

(left shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right

shifting within the same register thereby making it bidirectional. In this tutorial it is assumed

that all the data shifts to the right, (right shifting).

Universal Shift Register :-

Universal shift registers are very useful digital devices. They can be configured to respond to

operations that require some form of temporary memory, delay information such as the SISO

or PIPO configuration modes or transfer data from one point to another in either a serial or

parallel format. Universal shift registers are frequently used in arithmetic operations to shift

data to the left or right for multiplication or division.

Circuit Diagram:-

Procedure:-

Using Logisim, to insert a logic gate, expand the folder Gates and click on the desired logic

gate.








( ).

To assign a name to the input/output pin, click on the pin while the arrow icon ( ) is

selected.



A dark green color means that the current value on the wire is a logical ‘0’, while a light

green color signifies a ‘1’.



4. Design of 4-bit ALU

Aim: Designing an arithmetic logic unit for given parameter,

Examining behaviour of arithmetic logic unit for the working module and module designed

by the student as part of the experiment.

Components: To build any 4 bit ALU, we need

AND gate, OR gate, XOR gate

Full Adder,

4-to-1 MUX

Simulator or Logisim.

Objective: Understanding behaviour of arithmetic logic unit from working module and the

module designed by the student as part of the experiment

In case of counters the number of flip-flops depends on the number of different states in the

counter.

ALU or Arithmetic Logical Unit is a digital circuit to do arithmetic operations like addition,

subtraction, division, multiplication and logical operations like and, or, Ex-or, NAND, NOR

etc. A simple block diagram of a 4 bit ALU for operations and, or, Ex-or and Add is shown

The 4-bit ALU block is combined using 4 1-bit ALU block

Design Issues:

The circuit functionality of a 1 bit ALU is shown here, depending upon the control signal

S1 and S0 the circuit operates as follows:

For Control signal S1 = 0, S0 = 0, the output is A And B,

For Control signal S1 = 0, S0 = 1, the output is A Or B,

For Control signal S1 = 1, S0 = 0, the output is A Xor B,

For Control signal S1 = 1, S0 = 1, the output is A Add B.

The truth table for 16-bit ALU with capabilities similar to 74181 is shown here:

Required functionality of ALU (inputs and outputs are active high)

Mode Select Fn for active HIGH operands

Inputs Logic Arithmetic (note 2)

S3 S2 S1 S0 (M = H) (M = L) (Cn=L)

L L L L A' A

L L L H A'+B' A+B

L L H L A'B A+B'

L L H H Logic 0 minus 1

L H L L (AB)' A plus AB'

L H L H B' (A + B) plus AB'

L H H L A ⊕ B A minus B minus 1

L H H H AB' AB minus 1

H L L L A'+B A plus AB

H L L H (A ⊕ B)' A plus B

H L H L B (A + B') plus AB

H L H H AB AB minus 1

H H L L Logic 1 A plus A (Note 1)

H H L H A+B' (A + B) plus A

H H H L A+B (A + B') plus A

H H H H A A minus 1

Loading data in the arithmetic logic unit (refer to procedure tab for further detail and

experiment manual for pin numbers):

Load the two input numbers as:

o A(A3 A2 A1 A0): A3=1, A2=1, A1=0, A0=0

o B(B3 B2 B1 B0): B3=1, B2=0, B1=0, B0=1

o carry in(C0)=0

Examining the AND behaviour:

load data in select input as:

o S1=0, S0=0 `

check output:

o F3=1, F2=0, F1=0, F0=0

o cout=0 `

Examining the OR behaviour:


o S1=0, S0=1 `

check output:

o F3=1, F2=1, F1=0, F0=1

o cout=0 `

Examining the XOR behaviour:


o S1=1, S0=0 `

check output:

o F3=0, F2=1, F1=0, F0=1

o cout=0 `

Examining the ADD behaviour:


o S1=1, S0=1 `

check output:

o F3=0, F2=1, F1=0, F0=1

o cout=1

Likewise the 16 bit arithmetic logic unit can be designed and tested

by cascading 4 bit ALUs only the carry will propagate to the next level for ADD

operation

Test plan:

1. Set inputs 0101 and 0011 and check output for all possible select input combinations.

2. Set any two 16-bit number and check output for all possible select input

combinations.

Use Display units for checking output. Try to use minimum number of components to build.

The pin configuration of the canned components is shown when mouse hovered over a

component.

Circuit diagram of 4 bit ALU:

Screenshot of Design of 4 bit ALU:

Assignment Statements:

1. Design a 4 bit ALU comprising only the AND, OR, XOR and Add operations.

2. Design a 16-bit ALU with capabilities similar to 74181


Combinational Multiplier

Aim: To construct a 4x4 combinational multiplier from an array of AND gates, half-adders

and full-adders.

Components: To build a Combinational Multiplier, we need

1. 16 2-input AND Gates

2. 4 half adders

3. 8 full adders

4. Display unit to show the outputs.

5. Simulator or Logisim.

Objective: Examining behaviour of combinational multiplier for the working module and

module designed by the student as part of the experiment

1. understanding behaviour of combinational multiplier from module designed by the

student as part of the experiment

2. understanding the scheme implemented for the multiplication which is as follows

(along with the logic diagram bellow):

o it can be designed by unrolling the multiplier loop

o instead of handling the carry out of partial product summation bit, the carry

out can be sent to the next bit of the next step

o this scheme of handling the carry is called carry save addition

Combinational Multipliers do multiplication of two unsigned binary numbers. Each bit of the

multiplier is multiplied against the multiplicand, the product is aligned according to the

position of the bit within the multiplier, and the resulting products are then summed to form

the final result. Main advantage of binary multiplication is that the generation of intermediate

products are simple: if the multiplier bit is a 1, the product is an appropriately shifted copy of

the multiplicand; if the multiplier bit is a 0, the product is simply 0.The design of a

combinational multiplier to multiply two 4-bit binary number is illustrated below

If two n-bit numbers are multiplied then the output will be less than or equals to 2n bits.

Some features of the multiplication scheme:

it can be designed by unrolling the multiplier loop

instead of handling the carry out of partial product summation bit, the carry out can be

sent to the next bit of the next step

this scheme of handling the carry is called carry save addition

this scheme is more regular and modular

Logic diagram:

Loading data in the combinational multiplier, load the two input numbers as:

o multiplicand A(A3 A2 A1 A0): A3=1, A2=1, A1=0, A0=0

o multiplier B(B3 B2 B1 B0): B3=1, B2=0, B1=0, B0=1

Examining the behaviour:

check output sum:

o sum(S7 S6 S5 S4 S3 S2 S1 S0): S7=0, S6=1, S5=1, S4=0, S3=1, S2=1, S1=0,

S0=0

at any level check how the carry propagates to the next level

Test plan:

1. Set one input to zero (0) and check the output.

2. Set one input to one (1) and check the output.

3. Give proper inputs to check the identity, commutativity, associativity of

multiplication operation with interchanging input values.

Use Display units for checking output. Try to use minimum number of components to build.

The pin configuration of the canned components is shown when mouse hovered over a

component.

Circuit diagram of Combinational Multiplier:

Assignment Statements:

1. Create a combinational multiplier circuit to multiply two 4-bit binary numbers. Use

half adders, full adders and logic gates and test it by giving proper input.


computer organization lab

Documents

design of carry

design of mod

design of 8x4

design of ripple

design concepts implementation

design of 2kx8 memory

design of logic circuit

digital logic design