computer architecture and the fetch-execute cycle

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Computer Computer Architecture and the Architecture and the Fetch-Execute Cycle Fetch-Execute Cycle The Fetch-Decode- The Fetch-Decode- Execute-Reset Cycle Execute-Reset Cycle

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Computer Architecture and the Fetch-Execute Cycle. The Fetch-Decode-Execute-Reset Cycle. Learning Objectives. Describe in simple terms the fetch / decode / execute / reset cycle and the effects of the stages of the cycle on specific registers. The Fetch-Decode-Execute-Reset Cycle. - PowerPoint PPT Presentation

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Page 1: Computer Architecture and the Fetch-Execute Cycle

Computer Architecture and Computer Architecture and the Fetch-Execute Cyclethe Fetch-Execute Cycle

The Fetch-Decode-Execute-The Fetch-Decode-Execute-Reset CycleReset Cycle

Page 2: Computer Architecture and the Fetch-Execute Cycle

Learning ObjectivesLearning Objectives

Describe in simple terms the fetch / decode / execute / reset cycle and the effects of the stages of the cycle on specific registers.

Page 3: Computer Architecture and the Fetch-Execute Cycle

The Fetch-Decode-Execute-The Fetch-Decode-Execute-Reset CycleReset Cycle

The following is an algorithm in The following is an algorithm in diagrammatic form that shows the steps in diagrammatic form that shows the steps in the cycle.the cycle.It is the control unit which controls and It is the control unit which controls and synchronises this cycle.synchronises this cycle. Loads Loads / copies / places / passes/ copies / places / passes, decodes and , decodes and

executes. executes.

At the end the cycle is reset and the At the end the cycle is reset and the algorithm repeated. algorithm repeated.

Page 4: Computer Architecture and the Fetch-Execute Cycle

Key for following slides:Key for following slides:

PC PC / SQR/ SQR Program Counter Program Counter / Sequence Control Register/ Sequence Control Register

MARMAR Memory Address RegisterMemory Address Register

MDR MDR / MBR/ MBR Memory Data Register Memory Data Register / Memory Buffer Register/ Memory Buffer Register

CIRCIR Current Instruction RegisterCurrent Instruction Register

ACCACC AccumulatorAccumulator

Page 5: Computer Architecture and the Fetch-Execute Cycle

Idle RegistersIdle Registers

Note that during the Fetch - Decode – Note that during the Fetch - Decode – Execute - Reset cycle demonstrated on Execute - Reset cycle demonstrated on the following slides, some registers are the following slides, some registers are idle (not being used).idle (not being used).

This will be discussed and resolved in the This will be discussed and resolved in the next lesson.next lesson.

Page 6: Computer Architecture and the Fetch-Execute Cycle

PC MAR

MDR

CIR

Memory CPU

Copy of address of Copy of address of next instructionnext instruction

IInstructionnstruction

Copy of Copy of instruction in instruction in

memory memory address held in address held in

MARMAR

Fetch

Control UnitControl Unit

PC incremented PC incremented by 1 by 1

ACC

ALUALU

Page 7: Computer Architecture and the Fetch-Execute Cycle

CPU Decode

PC MAR

MDR

CIR

Control UnitControl Unit

Split instruction into operation Split instruction into operation code & address if present.code & address if present. Then decode operation code.Then decode operation code.

ACC

ALUALU

Page 8: Computer Architecture and the Fetch-Execute Cycle

CIR

CPU

Execute instructionExecute instruction((What is involved in this What is involved in this

depends on the instruction depends on the instruction being executed being executed - demonstrated - demonstrated

on the following slideson the following slides).).

Execute

PC MAR

MDR Control UnitControl Unit

ACC

ALUALU

Page 9: Computer Architecture and the Fetch-Execute Cycle

Jump

Input / Load (number directly)

Input / Load (from memory)

Store

Output (directly from accumulator)

Output (from memory)

Click an instruction or move on to see each instruction in turn.

Add (a number directly)

Add (a number from memory)

Page 10: Computer Architecture and the Fetch-Execute Cycle

Jump instructionJump instruction

Execute DiagramExecute Diagram

Page 11: Computer Architecture and the Fetch-Execute Cycle

PC

CIR

CPU Execute Jump

MAR

MDR Control UnitControl Unit

Copy of address part instruction

Copy of address part instruction

(address to jump to).

(address to jump to).

ACC

ALUALU

Page 12: Computer Architecture and the Fetch-Execute Cycle

PC

CIR

CPU Copy of address part instructionCopy of address part instruction

(address to jump to).(address to jump to).

Execute Jump

MAR

MDR

Back to list of instructions

Control UnitControl Unit

ACC

ALUALU

Page 13: Computer Architecture and the Fetch-Execute Cycle

Input / Load Input / Load (number directly)(number directly) into accumulator instructioninto accumulator instruction

Execute DiagramExecute Diagram

Page 14: Computer Architecture and the Fetch-Execute Cycle

CPU

Copy of number in MDR.

Copy of number in MDR.

Execute

MDR CIR Number inputted / to be loaded.Number inputted / to be loaded.

Input / Load (number directly) into accumulator

PC MAR

Back to list of instructions

Control UnitControl Unit

ACC

ALUALU

Page 15: Computer Architecture and the Fetch-Execute Cycle

Reason for the CIR & MDRReason for the CIR & MDRAs you can see the As you can see the MDRMDR is used to store the is used to store the number number inputted / to be inputted / to be loaded during the loaded during the execution of this execution of this Input / LoadInput / Load instruction. instruction.Therefore, if there was no Therefore, if there was no CIRCIR to hold the to hold the Input / LoadInput / Load instruction and, as no register can instruction and, as no register can hold more than one hold more than one “thing”“thing” at a time, the control at a time, the control unit would unit would “lose”“lose” the the Input / LoadInput / Load instruction. instruction. i.e. It would no longer i.e. It would no longer “know”“know” what it was supposed to what it was supposed to

do.do.

You will find that the contents of the MDR may You will find that the contents of the MDR may be modified for similar reasons during other later be modified for similar reasons during other later instructions.instructions.

Back to list of instructions

Page 16: Computer Architecture and the Fetch-Execute Cycle

Load Load (from memory)(from memory) instructioninstruction

Execute Diagram Execute Diagram

Page 17: Computer Architecture and the Fetch-Execute Cycle

MDR

Memory CPU Copy of Copy of data data in address in address

held in MARheld in MAR

Load (from memory)

MAR

Execute

Copy of Copy of data in MDR

data in MDR

Back to list of instructions

CIR

PC

Control UnitControl UnitAddress part o

f instruction

Address part of in

struction

(of data to be loaded).

(of data to be loaded).

ACC

ALUALU

Page 18: Computer Architecture and the Fetch-Execute Cycle

Reason for the PC & MARReason for the PC & MAR

As you can see the As you can see the MARMAR is now used to store is now used to store the the addressaddress part of instruction during the part of instruction during the execution of this execution of this Load Load (from memory)(from memory) instruction.instruction.Therefore if there was no Therefore if there was no MARMAR the the PCPC would be would be used to hold this address so the control unit used to hold this address so the control unit would no longer know the correct address of the would no longer know the correct address of the next instruction.next instruction.

You will find that the contents of the MAR You will find that the contents of the MAR may be modified for similar reasons during may be modified for similar reasons during other later instructions.other later instructions.

Back to list of instructions

Page 19: Computer Architecture and the Fetch-Execute Cycle

Add Add (a number directly)(a number directly) instructioninstruction

Execute DiagramExecute Diagram

Assume a number has already been Assume a number has already been inputted or loaded inputted or loaded (directly or from memory)(directly or from memory)

into the accumulator.into the accumulator.

Page 20: Computer Architecture and the Fetch-Execute Cycle

CIR

CPU

Execute

MDR

Number to be added.Number to be added.

Add Add number in MDR to number

number in MDR to number

already in accumulator.

already in accumulator.

NB. The ALU now does the arithmetic.NB. The ALU now does the arithmetic.Accumulator value is now the result of the addition.Accumulator value is now the result of the addition.i.e. Accumulator = Accumulator + contents of MDRi.e. Accumulator = Accumulator + contents of MDR

Add (a number directly)

PC MAR

Back to list of instructions

Control UnitControl Unit

ACC

ALUALU

Page 21: Computer Architecture and the Fetch-Execute Cycle

Add Add (a number from (a number from

memory)memory) instruction instructionExecute DiagramExecute Diagram

(Assume a number has already been (Assume a number has already been inputted or loaded into the inputted or loaded into the

accumulator.)accumulator.)

Page 22: Computer Architecture and the Fetch-Execute Cycle

CIR

CPU Add (from memory)

Execute

MDR

Memory

Copy of Copy of number number in memory in memory

address held in address held in MARMAR

Add Add number in MDR to number

number in MDR to number

already in accumulator.already in accumulator.

MAR

NB. The ALU now does the arithmetic.NB. The ALU now does the arithmetic.Accumulator value is now the result of the addition.Accumulator value is now the result of the addition.i.e. Accumulator = Accumulator + contents of MDRi.e. Accumulator = Accumulator + contents of MDR

PC

Back to list of instructions

Control UnitControl Unit

Address part of instruction

Address part of instruction

(of number to add).

(of number to add).

Control UnitControl Unit

ACC

ALUALU

Page 23: Computer Architecture and the Fetch-Execute Cycle

Store instructionStore instructionExecute DiagramExecute Diagram

Assume data has either been inputted, loaded Assume data has either been inputted, loaded (directly or from memory)(directly or from memory) or a calculation has been or a calculation has been performed.performed.

Any of the above will mean there is data in the Any of the above will mean there is data in the accumulator and it is this data that will be stored.accumulator and it is this data that will be stored.

Page 24: Computer Architecture and the Fetch-Execute Cycle

MAR

CIR

CPU

Address part of instruction

Address part of instruction

(to store in).

(to store in).

Store

Execute

MDR

Memory

Copy of Copy of data in data in MDR stored in MDR stored in

memory address memory address held in MARheld in MAR

Copy of Copy of data in accumulatordata in accumulator

PC

Back to list of instructions

Control UnitControl Unit

ACC

ALUALU

Page 25: Computer Architecture and the Fetch-Execute Cycle

Output Output (directly from (directly from

accumulator)accumulator) instruction instruction

Execute DiagramExecute Diagram

Page 26: Computer Architecture and the Fetch-Execute Cycle

CPU

Output data in Output data in accumulatoraccumulator

Execute

Output (directly from accumulator)

CIR MDR

PC MAR

Back to list of instructions

Control UnitControl Unit

ACC

ALUALU

Page 27: Computer Architecture and the Fetch-Execute Cycle

Output Output (from memory)(from memory) instructioninstruction

Execute DiagramExecute Diagram

Page 28: Computer Architecture and the Fetch-Execute Cycle

CIR

CPU Output (from memory)

Execute

MDR

Memory

Copy of Copy of data in data in memory address memory address

held in MARheld in MAR

Output data in Output data in accumulatoraccumulator

Copy of Copy of data in memory

data in memory

address held in MAR

address held in MAR

MAR PC

Back to list of instructions

Control UnitControl Unit

Address part of in

struction

Address part of in

struction

(of data to output).

(of data to output).

ACC

ALUALU

Page 29: Computer Architecture and the Fetch-Execute Cycle

CPU

Reset

PC

Cycle is reset (restarted) by passing Cycle is reset (restarted) by passing control back to the PC.control back to the PC.

Page 30: Computer Architecture and the Fetch-Execute Cycle

The CIR changes:The CIR changes:

1.1. When an instruction is loaded into it from When an instruction is loaded into it from the MDR.the MDR.

2.2. When the address in the instruction in When the address in the instruction in the CIR is modified by the addition of the the CIR is modified by the addition of the contents of an Index register (IR):contents of an Index register (IR):

A previously unmentioned register which is A previously unmentioned register which is covered in more detail in the next covered in more detail in the next Special Special Registers and Memory Addressing Registers and Memory Addressing Techniques PresentationTechniques Presentation..

Page 31: Computer Architecture and the Fetch-Execute Cycle

Idle RegistersIdle Registers

Note that during the Fetch - Decode – Note that during the Fetch - Decode – Execute - Reset cycle demonstrated on Execute - Reset cycle demonstrated on the previous slides, some registers were the previous slides, some registers were idle (not being used).idle (not being used).

This will be discussed and resolved in the This will be discussed and resolved in the next lesson.next lesson.

Page 32: Computer Architecture and the Fetch-Execute Cycle

Fetch – Decode - Execute – Reset Fetch – Decode - Execute – Reset Cycle in writingCycle in writing

The following slides describe the cycle in The following slides describe the cycle in writing.writing.

Page 33: Computer Architecture and the Fetch-Execute Cycle

1.1. Load the address of Load the address of next instructionnext instruction in the PC into in the PC into the MAR.the MAR. So that the control unit can fetch the instruction from the So that the control unit can fetch the instruction from the

right part of the memoryright part of the memory..2.2. Increment the PC by 1.Increment the PC by 1.

So that it contains the address of the next instruction, So that it contains the address of the next instruction, assuming that the instructions are in consecutive locations.assuming that the instructions are in consecutive locations.

3.3. Copy the instruction/data that is in the memory Copy the instruction/data that is in the memory address given by the MAR into the MDR.address given by the MAR into the MDR. MDR is used whenever anything is to go from the CPU to MDR is used whenever anything is to go from the CPU to

main memory, or vice versa. main memory, or vice versa.

4.4. Load the instruction/data that is now in the MDR Load the instruction/data that is now in the MDR into the CIR.into the CIR. Thus the next instruction is copied from memory -> MDR -Thus the next instruction is copied from memory -> MDR -

> CIR. > CIR.

5.5. Contents of CIR split into operation code and Contents of CIR split into operation code and address if present e.g. store, add or jump address if present e.g. store, add or jump instructions.instructions.

6.6. Decode the instruction that is in the CIR.Decode the instruction that is in the CIR.

Fetch

Decode

Page 34: Computer Architecture and the Fetch-Execute Cycle

6.6. Execute the instruction but what is involved in this Execute the instruction but what is involved in this depends on the instruction being executed (there depends on the instruction being executed (there are several different instructions you need to know are several different instructions you need to know about).about).

If the instruction is a jump instruction thenIf the instruction is a jump instruction then Load the address part of the instruction in the CIR into the Load the address part of the instruction in the CIR into the

PC.PC.

If the instruction is an input / load (directly) If the instruction is an input / load (directly) instruction then take data input and place in instruction then take data input and place in accumulator.accumulator.

If the instruction is a load (from memory) instruction.If the instruction is a load (from memory) instruction. Copy address part of the instruction (to load from) in the Copy address part of the instruction (to load from) in the

CIR into MAR.CIR into MAR. Copy data from memory address held in MAR to MDR.Copy data from memory address held in MAR to MDR. Copy data in MDR into accumulator.Copy data in MDR into accumulator.

Execute

Page 35: Computer Architecture and the Fetch-Execute Cycle

If the instruction is a store instruction then:If the instruction is a store instruction then: Copy address part of the instruction (to store in) in the Copy address part of the instruction (to store in) in the

CIR into MAR.CIR into MAR. Copy data in accumulator to MDR.Copy data in accumulator to MDR. Copy data in MDR into memory address held in MAR.Copy data in MDR into memory address held in MAR.

If the instruction is an add instruction then:If the instruction is an add instruction then: Copy address part of the instruction (of number to add) in Copy address part of the instruction (of number to add) in

the CIR into MAR.the CIR into MAR. Copy number from memory address held in MAR into Copy number from memory address held in MAR into

MDR.MDR. Add number in MDR to number in accumulator Add number in MDR to number in accumulator

(accumulator will now hold the result).(accumulator will now hold the result).

If the instruction is an output (directly from If the instruction is an output (directly from accumulator) then output number in accumulator.accumulator) then output number in accumulator.

Execute

Page 36: Computer Architecture and the Fetch-Execute Cycle

If the instruction is an output (from memory) If the instruction is an output (from memory) instruction then:instruction then:

Copy address part of part of the instruction (of data to Copy address part of part of the instruction (of data to output) in CIR into MAR.output) in CIR into MAR.

Output contents of MDR.Output contents of MDR.

7.7. Cycle is reset (restarted) by passing control back Cycle is reset (restarted) by passing control back to the PC (step 1).to the PC (step 1).

Execute

Reset

Page 37: Computer Architecture and the Fetch-Execute Cycle

PlenaryPlenary

Describe the fetch / decode part of the fetch / decode / execute / reset cycle, explaining the purpose of any special registers that you have mentioned.

Page 38: Computer Architecture and the Fetch-Execute Cycle

PlenaryPlenary

Contents of PC loaded into MARPC is incrementedContents of address stored in MAR loaded into MDRContents of MDR loaded into CIRInstruction in CIR is decoded.PC (program counter) stores the address of the next instruction to be executed.MAR (memory address register) holds the address in memory that is currently being usedMDR (memory data register) holds the data (or instruction) that is being stored in the address accessed by the MAR.CIR (current instruction register) holds the instruction which is currently being executed.