competing system-on-chip bus standardsens.ewi.tudelft.nl/education/courses/et4351/axi_bus.pdf ·...
TRANSCRIPT
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Bus Developed by High-PerformanceShared Bus
PeripheralShared
Bus
Point-to-PointBus
AMBA v3 ARM AHB APB
AMBA v4 ARM AXI4 AXI4-Lite AXI4-Stream
Coreconnect IBM PLB OPB
Wishbone SiliCore Corp.
Crossbar Topology
SharedTopology
Point to PointTopology
Avalon Altera Avalon-MM Avalon-MM Avalon-ST
AMBA: Advanced Microcontroller Bus ArchitectureAXI: Advanced eXtensible InterfaceAHB: AMBA High-speed BusAPB: AMBA Peripheral BusPLB: Processor Local BusOPB: On-chip Peripheral BusMM: Memory MappedST: Streaming
Competing System-on-Chip Bus Standards
Source: A Practical Introduction toHardware/Software Codesign
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Source: M.S. Sadri, Zynq Training
Additional Information Exchanged BetweenAXI Master and AXI Slave
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Source: M.S. Sadri, Zynq Training
Five Channels of AXI Interface
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AXI4 Interface
Write Address Channel
Write Data Channel
Write Response Channel
Read Address Channel
Read Data Channel
Source: The Zynq Book
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(Shared Bus)
(Point-to-Point Bus)
(Peripheral)
(High-Performance)
Source: M.S. Sadri, Zynq Training
AXI Interfaces
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AXI4-lite Signal Names
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AXI4 Write
Source: The Zynq Book
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AXI4-lite Write Data, Response Channel
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Write Cycle
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Source: ARM AMBA AXI Protocol v1.0: Specification
Write Transaction Handshake Dependencies
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AXI4 Read
Source: The Zynq Book
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Read Transaction Handshake Dependencies
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AXI4-lite Read, Data and Response Channel
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Read Cycle