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COM20051
Integrated Microcontroller andARCNET (ANSI 878.1) Interface
FEATURES
• High Performance/Low Cost• Microcontroller Based on Popular 8051
Architecture• Intel 8051 Instruction Set Compatible• Drop-In Replacement for 80C32 PLCC• Network Supports up to 255 Nodes• Powerful Network Diagnostics• Maximum 507 Byte Packets• Duplicate Node ID Detection• Self-Configuring Network Protocol
• Retains all 8051 Peripherals Including SerialI/O and Two Timers
• Utilizes ARCNET® Token Bus NetworkEngine
• Requires No Special Emulators• 5 Mbps to 156 Kbps Network Data Rate• Network Interface Supports RS-485, Twisted
Pair, Coaxial, and Fiber Optic Interfaces• Receive All Mode Allows Any Packet to Be
Received
GENERAL DESCRIPTION
The COM20051 is a low-cost, highly-integratedmicrocontroller incorporating a high-performancenetwork controller based on the ARCNET TokenBus Standard (ANSI 878.1). The COM20051 isbased around the popular Intel 8051architecture. The device is implemented using amicrocontroller core compatible with the Intel80C32 ROMless version of the 8051architecture. The COM20051 is ideal fordistributed control networking applications suchas those found in industrial/machine controls,building/factory automation, consumer products,instrumentation and automobiles.
The COM20051 contains many features that arebeneficial for embedded control applications.
The microcontroller is a fully-functional 16MHz80C32 that is comparable to the Intel 80C32 with2 timers. In contrast to other embeddedcontroller/networking solutions, the COM20051adds a fully-featured, robust, powerful, andsimple network interface while retaining all of thebasic 8051 peripherals, such as the serial portand counter/timers.
In addition, the COM20051 supports anEmulation Mode that permits the use of astandard 80C32 emulator in conjunction with theCOM20051 to develop software drivers for thenetwork core. ARCNET core is mapped to a256-byte page of the External Data MemorySpace of the 80C32. This
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TABLE OF CONTENTS FEATURES........................................................................................................................................................................1 GENERAL DESCRIPTION................................................................................................................................................1 PIN CONFIGURATION......................................................................................................................................................3 OVERVIEW........................................................................................................................................................................4 DESCRIPTION OF PIN FUNCTIONS...............................................................................................................................4 BASIC ARCHITECTURE...................................................................................................................................................7 PROTOCOL DESCRIPTION...........................................................................................................................................12NETWORK PROTOCOL ..................................................................................................................................................12DATA RATES....................................................................................................................................................................12NETWORK RECONFIGURATION...................................................................................................................................12BROADCAST MESSAGES ..............................................................................................................................................14EXTENDED TIMEOUT FUNCTION.................................................................................................................................14LINE PROTOCOL.............................................................................................................................................................15SYSTEM DESCRIPTION .................................................................................................................................................18MICROCONTROLLER INTERFACE ...............................................................................................................................18TRANSMISSION MEDIA INTERFACE............................................................................................................................18ARCNET CORE FUNCTIONAL DESCRIPTION.............................................................................................................24MICROSEQUENCER .......................................................................................................................................................24INTERNAL REGISTERS ..................................................................................................................................................24INTERNAL RAM ...............................................................................................................................................................38SOFTWARE INTERFACE................................................................................................................................................38COMMAND CHAINING ....................................................................................................................................................42RESET DETAILS ..............................................................................................................................................................45INITIALIZATION SEQUENCE..........................................................................................................................................45IMPROVED DIAGNOSTICS.............................................................................................................................................46COM20051 APPLICATIONS INFORMATION .................................................................................................................48USING ARCNET DIAGNOSTICS TO OPTIMIZE YOUR SYSTEM................................................................................66CABLING THE COM20051 ..............................................................................................................................................70USING THE COM20051'S EMULATION MODE.............................................................................................................71OPERATIONAL DESCRIPTION ......................................................................................................................................72MAXIMUM GUARANTEED RATINGS.............................................................................................................................72DC ELECTRICAL CHARACTERISTICS..........................................................................................................................72TIMING DIAGRAMS .........................................................................................................................................................74PACKAGE DIMENSIONS.................................................................................................................................................80
80 Arkay DriveHauppauge, NY 11788(516) 435-6000FAX (516) 273-3123
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provides for an easy interface between the CPUand the ARCNET core. The networking coreis based around an ARCNET Token Busprotocol engine that provides highly-reliable andfault tolerant message delivery at data ratesranging from 5Mbps down to 156 Kbps withmessage sizes varying from 1 to 508 bytes.The ARCNET protocol offers a simple,standardized, and easily-understood networkingsolution for any application. The networkinterface supports several media interfaces,
including RS-485, coaxial, and twisted pair ineither bus or star topologies. The networkinterface incorporates powerful diagnosticfeatures for network management and faultisolation. These include duplicate node IDdetection, reconfiguration detection, receive all(monitor) mode, receiver activity, and tokendetection.
ARCNET is a registered trademark of Datapoint Corporation
PIN CONFIGURATION
P3.
6/nW
R
P3.
7/nR
D
XTA
L2
XTA
L1
VS
S
nPU
LSE
2
P2.
0/A
8
P2.
1/A
9
P2.
2/A
10
P2.
3/A
11
P2.
4/A
12
P1.
4
P1.
3
P1.
2
P1.
1
P1.
0
RX
IN
VC
C
P0.
0/A
D0
P0.
1/A
D1
P0.
2/A
D2
P0.
3/A
D3
P1.5P1.6P1.7RST
P3.0/RXDnPULSE1P3.1/TXDP3.2/INT0P3.3/INT1
P3.4/T0P3.5/T1
P0.4/AD4P0.5/AD5P0.6/AD6P0.7/AD7nEA/EMULTXENALEnPSENP2.7/A15P2.6/A14P2.5/A13
COM20051
6 5 4 3 2 1 44 43 42 41 40
18 19 20 21 22 23 24 25 26 27 28
3938373635343332313029
7891011121314151617
44
OVERVIEW
The COM20051 is essentially a network board-in-a-chip. It takes an 80C32 microcontroller coreand an ARCNET controller and integrates theminto a single device. ARCNET is a tokenpassing-based protocol that combines powerfulflow control, error detection, and diagnosticcapabilities to deliver fast and reliable messages.The COM20051 supports a variety of data rates(5 Mbps to 156 Kbps), topologies (bus, star,tree), and media types (RS-485, coax, twistedpair, fiber optic, and powerline) to suit any type ofapplication.
The ARCNET network core of the COM20051contains many features that make networkdevelopment simple and easy to comprehend.Diagnostic features, such as Receive All,Duplicate ID Detection, ReconfigurationDetection, Token, and Receiver Detection, allcombine to make the COM20051 simple to useand to implement in any environment. TheARCNET protocol itself is relatively simple tounderstand and very flexible. A wide variety ofsupport products are available to assist innetwork development, such as software drivers,line drivers, boards, and development kits. The
COM20051 implements a full-featured 16MHz,Intel-compatible 80C32 microcontroller with all ofthe standard peripheral functions, including a fullduplex serial port, two timer/counters, one 8-bitgeneral purpose digital I/O port, and interruptcontroller. The 8051 architecture has long beena standard in the embedded control industry forlow-level data acquisition and control. ARCNETand the 8051 form a simple solution for many oftoday's and tomorrow's low-level networkingsolutions.
In addition to the 80C32 and the ARCNETnetwork core, the COM20051 contains all theaddress decoding and interrupt routing logic tointerface the network core to the 80C32 core.The integrated 8051/ARCNET combinationprovides an extremely cost-effective and space-efficient solution for industrial networkingapplications. The COM20051 can be used in astand-alone embedded application, executingcontrol algorithms or performing data acquisitionand communicating data in a master/slave orpeer-to-peer configuration, or used as a slaveprocessor handling communication tasks in amulti-processing system.
DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL DESCRIPTION
1 Receive In RXIN Input. Network receiver input.
2-9 P1.0-1.7 P1.0-1.7 Input/Output. Port 1 of the 8051. General purposedigital I/O port.
10 Reset RESET Input. Active high reset.
11 P3.0 P3.0 Input/Output. Port 3 bit 0 of the 8051. RX input ofserial port.
12 nPulse 1 nPULSE1 Output. Network output. Open-drain whenbackplane mode is invoked, otherwise it is a push-pull output.
13-19 P3.1-3.7 P3.1-3.7 Input/Output. Port 3 bits 1-7 of the 8051.
20, 21 Crystal Oscillator XTAL1,XTAL2
Input. Oscillator inputs 1 and 2.
22 Ground VSS Ground pin.
55
DESCRIPTION OF PIN FUNCTIONSPIN NO. NAME SYMBOL DESCRIPTION
23 nPulse 2 nPULSE2 Output. Network output. Outputs a synchronousclock at 2x the data rate when backplane mode isinvoked.
24-31 P2.0-2.7 P2.0-2.7 Input/Output. Port 2 of the 8051. High order addressbus.
32 nProgram StoreEnable
nPSEN Output.
33 Address LatchEnable
ALE Output.
34 Transmit Enable TXEN Output. This signal is used to enable the drivers fortransmitting. The polarity of this signal isprogrammable by grounding the nPULSE2 pin priorto the POWER-UP.nPULSE2 floating prior to the power-up = TXENactive highnPULSE2 grounded prior to the power-up = TXENactive low. (This option is available only in theBackplane mode).
35 nEnable nEA Input. When high, causes the 8051's outputs to tri-state. When low, allows the 8051 to address externalmemory. Must be low to execute code from theembedded 8051.
36-43 P0.7-0.0 P0.7-0.0 Input/Output. Port 0 of the 8051. Multiplexed loworder address/data bus.
44 Power Supply VCC +5V power supply.
RESET CIRCUIT FOR THE COM20051The power on reset circuit for the COM20051 should be designed to provide a clean, fast transition timeTTL input to the COM20051. Sufficient signal high time on RST (pin 10) should be provided after Vccreaches +5V DC. The following circuit, which provides an 8ms power-on reset pulse, is recommended:
Vcc (+5V)
22uF/10V RST (PIN 10)
22074LS14
66
FIGURE 1 – INTERNAL ARCHITECTURE OF THE COM20051
INTERRUPT ROUTER
ADDRESS DECODER
ARCNET CORE (COM20010)
INT0 INT1
A8-A15
AD0-AD7
INTnCSRD/WR
ALE nPULSE1nPULSE2TXENRXIN
PORT0
PORT3
PORT2
INT0 INT1
PORT1
TXRXT0T1
EMUL ALE
ALE
CONTROL BUS
nPSEN
80C32
77
BASIC ARCHITECTURE
The COM20051 consists of four functionalblocks: the 80C32 microcontroller core,ARCNET network cell (includes 1K of bufferRAM), programmable address decoder, andprogrammable interrupt router. The internalarchitecture of the COM20051 is shown in Figure1.
The 80C32 microcontroller is a full ROMlessimplementation of the popular Intel 8051 series.The ARCNET network core is similar inarchitecture to SMSC's popular COM20020family of ARCNET controllers and retains thesame command and status flags of previousARCNET controllers. The programmableaddress decoder maps the ARCNET registersinto a 256-byte page anywhere within theExternal Data Memory space of the 80C32. TheARCNET core was mapped to the External DataMemory space to simplify software andapplication development and for production testpurposes. ARCNET core is available to thedeveloper when working with the 8051 emulator.When the COM20051 is put into Emulate mode,the internal microcontroller is put into a highimpedance state, thus allowing an external In-Circuit Emulator (ICE) to program the ARCNETcore. The advantage of this approach versusmapping the ARCNET registers into the internalmemory (Special Function) area of the 80C32 isthat dedicated software development tools willnot be necessary to debug application software.Since a majority of 8051 applications use only asmall portion of the Data Memory space, there isno penalty paid for used address space. Therewill also be no penalty in execution time, sincecycle times for external data memory accessesand internal direct memory moves are identical.The network interrupt can be routed to either ofthe two external interrupt ports or can beassigned to one of the general purpose I/O ports.The ARCNET interrupt is internally wire ORedwith the external interrupt pin to allow greatersystem flexibility.
80C32 ARCHITECTURE AND INSTRUCTIONSET
The 80C32 microcontroller core is identical to the16MHz Intel 80C32 in all respects except for theabsence of Timer 2. Please refer to the IntelEmbedded Microcontrollers and ProcessorsDatabook, Volume 1, for details regarding the8051 architecture, peripherals, instruction set,and programming guide. Note that any accessto the internal ARCNET core or any externalmemorry access is visible on the pins of theCOM20051.
The following differences apply to theCOM20051:
1. Oscillator frequency is 40MHz instead of16MHz. This is necessary to derive a20MHz clock for the ARCNET core. Theprocessor still operates at 16MHz.
2. nEA pin - This pin must be tied to groundfor normal internal processor operation.When tied to VCC, the COM20051 will enterthe Emulate mode.
3. Unused pins - The COM20051 is packagedin a 44-pin PLCC. Network I/O is generatedon the four unused pins of the standard80C32 PLCC package. No DIP package isavailable.
4. Power Down operation - The Power Downmode can only be used in conjunction whenthe internal oscillator is being used. If anexternal oscillator is used and the PowerDown mode is invoked, damage may resultto the oscillator and to the COM20051.
Clock Speed
The COM20051 processor operates at 16MHzand the network controller at a maximum 40MHzclock rate. A single crystal oscillator is used tosupply the two clocks: a 16MHz processor clockand a 20MHz network clock for the nominal 2.5Mbps data rate. Pins 20 and 21 are designatedas crystal inputs. When clocking with an external
88
oscillator, pin 21 (XTAL1) functions as the clockinput.
Emulate Mode
The COM20051 contains a unique feature calledthe Emulate mode that most 8051-basedperipheral devices do not accommodate.TheEmulate mode permits developers to access
and program the internal ARCNET core using astandard low-cost 8032 emulator. This featureeliminates the need for expensive dedicateddevelopment equipment needed for other typesof 8051-based peripheral devices. The Emulatemode is invoked by connecting the nEA pin toVCC. This causes the internal 80C32 processorto enter a HI-Z state and changes the state of theCOM20051 pins according to the following table:
Table 1 - Emulate ModeSIGNAL NAME EMUL = 0 EMUL = 1
PORT 0 Bidirectional Bidirectional
PORT 1 Bidirectional HI-Z (except for pinsdesignated as interruptdestinations)
PORT 2 Output Input
INT0,1(P3.2, P3.3)
Input Output
RD/WR(P3.6, P3.7)
Output Input
ALE Output Input
TX,T0, T1(P3.1,3.4,3.5)
nPSEN
Output HI-Z
Address Decoding
The COM20051, as described previously, mapsthe ARCNET registers into the 80C32's ExternalData Memory space. This provides systemflexibility because the location of the ARCNETregisters can be located anywhere within the 64KExternal Data Memory space. The preciselocation can be resolved with a 256-byte page.The location of that page in the External DataMemory space is pointed to by the read/writeAddress Decode Register, as shown in Figure 2.The Address Decode Register is located at
FFFFh of the External Data Memory space. Itholds the upper 8 bits of the 16-bit address atwhich the 256 page boundary will start. Thisregister must be programmed prior to any accessto the ARCNET core. The default value is0000h.
The ARCNET core register page must bemapped away from the external RAM prior to anyaccess to the external RAM by the software.Failure to do this may result in incorrect datawrite and read operations to the external RAM aswell as the core registers.
99
FIGURE 2 – COM20051 EXTERNAL DATA ADDRESS SPACE
ADDRESS DECODE REGISTERNAME BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
ADR DEC A15 A14 A13 A12 A11 A10 A9 A8
LOCATION: FFFFh of the External Data Memory space. Default: 00h
EXAMPLE: Address Decode Register = 80hARCNET core registers will be located at 8000h + Register offset (e.g. ARCNETConfiguration Register offset = 06h, physical address = 8006h).
ARCNET CORE256 BYTES
FFFFh
64K BYTES
ADDRESS DECODE REGISTER(FIXED LOCATION)
PAGE LOCATION CAN VARY
VALUE x 100h
0000h
1010
COM20051 MEMORY MAPPING
The COM20051 maps the Arcnet core into a256 byte page of data memory space. Thismemory is physically located internally to thedevice and itrquote s default base address onpower up is 0000h. This 256 byte page can belogically located anywhere within the 64Kexternal data memory space while physicallyremaining on board. The location of this 256 bytepage is pointed to by the Address DecodeRegister in the device. This Address DecodeRegister holds the upper 8 bits of the 16 bitaddress at which the 256 byte page boundarywill start. The address of this Address DecodeRegister is FFFFh. This register is also logicallylocated in external data memory space butphysically located on the device. This registermust be written to on power-up to properly locatethe Arcnet core. .
The user must ensure that the Arcnet corerquotes 256 byte page does not conflict with externalmemory, otherwise data bus contention willresult. As an example, if the user has 32K ofexternal data memory located from 0000h to7FFFh then the Arcnet core should be mappedabove this area, 8000H is suggested. The userwill write 80h to address FFFFh on power up toproperly map the core to this location.
ARCNET Network Core - Overview andArchitecture
ARCNET is a baseband token passing networkprotocol (ANSI 878.1). ARCNET featuresdeterministic behavior, hardware-based networkconfiguration, flexible topologies, several datarates, and multiple media support. Data ratesvarying from 5 Mbps to 156 Kbps and messagesizes from 1 to 508 bytes are supported.Supported media includes RS-485, twisted pair,coax, fiber optic, and powerline in bus, star ortree topologies. ARCNET has enjoyedwidespread use in the industrial community,finding a home in such applications as I/Ocontrol/acquisition, multi-processorcommunications, point-of-sale terminals, in-vehicle navigation systems, data acquisitionsystems, remote sensing, avionics, machinecontrol, embedded computing, buildingautomation, robotics, consumer products, andsecurity systems.
The ARCNET core used in the COM20051 issimilar in architecture to SMSC's 200XX series ofIndustrial ARCNET Controllers. The ARCNETcore of the COM20051 contains a 1K x 8 internalRAM for packet buffering, Duplicate IDDetection, Receive All Mode, New Next IDIndicator, Excessive NACK Interrupt,Programmable Data Rates, Backplane Mode,Programmable Transmitter Enable, PolarityReceive Activity, Reconfiguration, Token SeenIndicators, and Network Mapping hooks. TheARCNET core of the COM20051 uses asoftware-programmable node ID, enabling theuser to program the Node ID according to theapplication needs. The Node ID can be stored inan electronic medium or changed with theswitch.
1111
FIGURE 3 - DETAILED ARCNET CORE OPERATION
Invitationto Transmit to
this ID?
Y N
Free BufferEnquiry to
this ID?SOH?
Y N
Y N
RI?
Write SIDto Buffer
DID=0?
DID=ID?
Write Bufferwith Packet
CRCOK?
LENGTHOK?
DID=0?
DID=ID?
SEND ACK
N
Y
N
Y
N
Y N
BroadcastEnabled?
N
Y
N
No Activityfor 82
uS?
Y
N
Set NID=ID
Start Timer:T=(255-ID)
ActivityOn Line?
Y
N
T=0?
Set RI
RI?TransmitNAK
TransmitACK
Set NID=ID
Write ID toRAM Buffer
SendReconfigure
Burst
Power On
ReconfigureTimer hasTimed Out
Start ReconfigurationTimer (840 mS)
TA?
Broadcast?Transmit
Free BufferEnquiry
No Activity
Pass theToken
Set TA
Y
N
ACK?
NAK?
1
NoActivity NYIncrement
NID
SendPacket
Was PacketBroadcast?
NoActivity
N
ACK? Set TMA
Set TA
x 146 us
for 74.7us?
for 74.7us?
for 74.7us?
YN
NY
Y N
NY
N
N
N
N
1
YY
Y
Y Y
Y
Y
N
Y
Read Node ID
ID refers to the identification number of the ID assigned to this node.
NID refers to the next identification number that receives the token afterafter this ID passes it.
-
-
-
-
SID refers to the source identification.DID refers to the destination identification.SOH refers to the start of header character; preceeds all data packets.
-
Y N
Note*: Time values pertain to the default 2.5 Mbps operation
1212
PROTOCOL DESCRIPTION
NETWORK PROTOCOL
Communication on the network is based on atoken passing protocol. Establishment of thenetwork configuration and management of thenetwork protocol are handled entirely by theCOM20051's internal microcoded sequencercalled ARCNET network core. The 80C32controller core transmits data by simply loadinga data packet and its destination ID into thenetwork core's RAM buffer, and issuing acommand to enable the transmitter. When theARCNET core next receives the token, it verifiesthat the receiving node is ready by firsttransmitting a FREE BUFFER ENQUIRYmessage. If the receiving node transmits anACKnowledge message, the data packet istransmitted followed by a 16-bit CRC. If thereceiving node cannot accept the packet(typically its receiver is inhibited), it transmits aNegative AcKnowledge message and thetransmitter passes the token. Once it has beenestablished that the receiving node can acceptthe packet and transmission is complete, thereceiving node verifies the packet. If the packetis received successfully, the receiving nodetransmits an ACKnowledge message (or nothingif it is not received successfully) allowing thetransmitter to set the appropriate status bits toindicate successful or unsuccessful delivery ofthe packet. An interrupt mask permits theARCNET core to generate an interrupt to theprocessor when selected status bits becometrue. Figure 4 is a flow chart illustrating theinternal operation of the ARCNET core. Alltiming details in the discussion of ARCNETprotocol are based on the 2.5 Mbps data rate.
DATA RATES
The ARCNET core is capable of supporting datarates from 156.25 Kbps to 5 Mbps. For slower or
faster data rates, an internal Programmableclock divider scales down the clockfrequency. Thus all timeout values are scaledup as shown in the following table:
DATARATE
TIMEOUT SCALINGFACTOR
(MULTIPLY BY)CLOCKPRE-
SCALER
40 MHzCLOCK DIV.TO 20 MHz
40 MHz UN-DIVIDED
40 MHzCLOCK DIV.TO 20 MHz
40 MHzUN-
DIVIDED÷8
÷16÷32÷64
÷128
25Mbps1.25Mbps625Kbps
3125Kbps156.25Kbps
5Mbps25Mbps
1.25Mbps625Kbps
3125Kbbps
1248
16
.51248
NETWORK RECONFIGURATION
A significant advantage of the ARCNET is itsability to adapt to changes on the network.Whenever a new node is activated ordeactivated, a NETWORK RECONFIGURATIONis performed. When a new ARCNET node isturned on (creating a new active node on thenetwork), or if the COM20051 has not receivedan INVITATION TO TRANSMIT for 840ms, or ifa software reset occurs, the ARCNET nodecauses a NETWORK RECONFIGURATION bysending a RECONFIGURE BURST consisting ofeight marks and one space repeated 765 times.The purpose of this burst is to terminate allactivity on the network. Since this burst is longerthan any other type of transmission, the burst willinterfere with the next INVITATION TOTRANSMIT, destroy the token and keep anyother node from assuming control of the line.
When any ARCNET node senses an idle line forgreater than 82 S, which occurs only when thetoken is lost, it starts an internal timeout equal to146 s times the quantity 255 minus its own ID.The COM20051 starts network reconfigurationby sending an invitation to transmit (TOKEN)first to itself and then to
1313
FIGURE 4 - ARCNET RECONFIGURATION PROCESS
HARDWARE OR SOFTWARE RESET OR NO TOKEN FOR
840 MS
SEND RECON BURST
(765 times 111111110)
TIMEOUT FOR146µs x
(255 - NODE ID)
TRANSMIT TOKEN TO NODE = OWN ID
LINE ACTIVITY DETECTED
WITHIN 74.7µs
INCREMENT TOKEN VALUE AND TRANSMIT
840msTIMER
EXPIRED?
END NODE RECONFIGURATION
SET RECON BIT IN THE STATUS
REGISTER & NEW NEXT ID
BIT IN THE DIAGNOSTIC
STATUS REGISTER
NODE DROPS OFF THE
NETWORK
NO ACTIVITY WITHIN 82µs?
N
Y
Y
NN
Y
1414
all other nodes by incrementing the destinationNode ID value. If the timeout expires with noline activity, the ARCNET core starts sendingINVITATION TO TRANSMIT with the DestinationID (DID) equal to the currently stored NID.Within a given network, only one node willtimeout (the one with the highest ID number).After sending the INVITATION TO TRANSMIT,the COM20051 waits for activity on the line. Ifthere is no activity for 74.7 S, the COM20051increments the NID value and transmits anotherINVITATION TO TRANSMIT using the NID equalto the DID. If activity appears before the 74.7 Stimeout expires, the COM20051 releases controlof the line. During NETWORKRECONFIGURATION, INVITATIONS TOTRANSMIT are sent to all NIDs (1-255).
Each COM20051 on the network will finally havesaved a NID value equal to the ID of theARCNET node that it released control to. This iscalled the Next ID Value. At this point, control ispassed directly from one node to the next with nowasted INVITATIONS TO TRANSMIT being sentto ID's not on the network, until the nextNETWORK RECONFIGURATION occurs.When a node is powered off, the previous nodeattempts to pass the token to it by issuing anINVITATION TO TRANSMIT. Since this nodedoes not respond, the previous node times outand transmits another INVITATION TOTRANSMIT to an incremented ID and eventuallya response will be received.
The NETWORK RECONFIGURATION timedepends on the number of nodes in the network,the propagation delay between nodes, and thehighest ID number on the network, but is typicallywithin the range of 24 to 61 ms for 2.5 Mbpsoperation.
BROADCAST MESSAGES
Broadcasting gives a particular node the ability totransmit a data packet to all nodes on thenetwork simultaneously. NID=0 is reserved forthis feature and no node on the network can beassigned NID=0. To broadcast a message, thetransmitting node's processor simply loads theRAM buffer with the data packet and sets theDID (Destination ID) equal to zero. Figure 12
illustrates the position of each byte in the packetwith the DID residing at address 1Hex of thecurrent page selected in the "Enable Transmitfrom Page fnn" command. Each individual nodehas the ability to ignore broadcast messages bysetting the most significant bit of the "EnableReceive to Page fnn" command (see Table 8) toa logic "0".
EXTENDED TIMEOUT FUNCTION
There are three timeouts associated with theCOM20051 operation. The values of thesetimeouts are controlled by bits 3 and 4 of theConfiguration Register and bit 5 of the SetupRegister (see register description for details).
Response Time (ET1, ET2, ET3)
The Response Time determines the maximumpropagation delay allowed between any twonodes, and should be chosen to be larger thanthe round trip propagation delay between the twofurthest nodes on the network plus the maximumturn around time (the time it takes a particularARCNET node to start sending a message inresponse to a received message) which isapproximately 12.7 S. The round trippropagation delay is a function of thetransmission media and network topology. For atypical system using RG62 coax in a basebandsystem, a one way cable propagation delay of 31S translates to a distance of about 4 miles. Theflow chart in Figure 3 uses a value of 74.7 S (31+ 31 + 12.7) to determine if any node willrespond.
Idle Time (ET1, ET2, ET3)
The Idle Time is associated with the NETWORKRECONFIGURATION. Figure 3 and Figure 4illustrate that during a NETWORKRECONFIGURATION one node will continuallytransmit INVITATIONS TO TRANSMIT until itencounters an active node. All other nodes onthe network must distinguish between thisoperation and an entirely idle line. DuringNETWORK RECONFIGURATION, activity willappear on the line every 82 S. This 82 S isequal to the Response Time of 74.7 S plus thetime it takes the COM20051 to start
1515
retransmitting another message (usually anotherINVITATION TO TRANSMIT).
Reconfiguration Time (ET1, ET2)
If any node does not receive the token within theReconfiguration Time, it will initiate aNETWORK RECONFIGURATION. The ET2 andET1 bits of the Configuration Register allow thenetwork to operate over longer distances thanthe 4 miles stated earlier. The logic levels onthese bits control the maximum distances overwhich the COM20051 can operate by controllingthe three timeout values described above. Forproper network operation, all nodes connected tothe same network must have the sameResponse Time, Idle Time, and ReconfigurationTime.
LINE PROTOCOL
The ARCNET line protocol is consideredisochronous because each byte is preceded by astart interval and ended with a stop interval.Unlike asynchronous protocols, there is aconstant amount of time separating each databyte. Each byte takes exactly 11 clock intervalsthat are defined by nPULSE1 and nPULSE2signals (at 2.5 Mbps one byte takes 4.4 ms). Asa result a time to transmit a message can beprecisely determined. The line idles in aspacing (logic "0") condition. A logic "0" isdefined as no line activity and a logic "1" isdefined as a negative pulse of 200nSduration. A transmission starts with an
ALERT BURST consisting of 6 unit intervals ofmark (logic "1"). Eight bit data characters arethen sent, with each character preceded by 2unit intervals of mark and one unit interval ofspace. Five types of transmission can beperformed as described below:
Invitations To Transmit (ITT)
An Invitation To Transmit is used to pass thetoken from one node to another and is sent bythe following sequence:
• An ALERT BURST• An ITT (Invitation To Transmit: ASCII code
04H)• Two (repeated) DID (Destination ID)
characters
ALERTBURST
ITT DID DID
Free Buffer Enquiries (FBE)
A Free Buffer Enquiry is used to ask anothernode if it is able to accept a packet of data. It issent by the following sequence:
• An ALERT BURST• An FBE - Free Buffer Enquiry: ASCII code
85H)• Two (repeated) DID (Destination ID)
characters
ALERTBURST
FBE DID DID
1616
Data Packets (PAC)
A Data Packet consists of the actual data beingsent to another node. It is sent by the followingsequence:
• An ALERT BURST• An PAC (Data Packet--ASCII code 01H)• An SID (Source ID) character• Two (repeated) DID (Destination ID)
characters
• A single COUNT character which is the2's complement of the number of databytes to follow if a short packet is sent,or 00Hex followed by a COUNTcharacter if a long packet is sent
• N data bytes where COUNT = 256-N (or512-N for a long packet)
• Two CRC (Cyclic Redundancy Check)characters. The CRC polynomial used is:X16 + X15 + X2 + 1.
Acknowledgements (ACK)
An Acknowledgement is used to acknowledgereception of a packet or as an affirmativeresponse to FREE BUFFER ENQUIRIES and issent by the following sequence:
• An ALERT BURST• An ACK (ACKnowledgement--ASCII code
86H) character
ALERTBURST
ACK
Negative Acknowledgements (NAK)
A Negative Acknowledgement is used as anegative response to FREE BUFFERENQUIRIES and is sent by the followingsequence:
• An ALERT BURST• A NAK (Negative Acknowledgement--ASCII
code 15H) character
ALERTBURST
NAK
Figure 5 illustrates the flow of events on a 5-node network where a node with the NID=1 transmits adata packet to a node with the NID=5, and a node with the NID=3 tries to transmit a data to a nodewith the NID=4 but node 4 cannot accept it. All other nodes are just passing the tokens.
ALERT
BURSTPAC SID DID DID COUNT data data CRC CRC
1717
FIGURE 5 – AVERAGE SEQUENCE OF LINE EVENTS FOR A FIVE-NODE NETWORK
#5 ITT to #1 #1 FBE to #5 #5 ACK to #1 #1 PAC to #5 #5 ACK to #1
#1 ITT to #2#2 ITT to #3#3 FBE to #4#4 NAK to #3#3 ITT to #4
#4 ITT to #5
SEQUENCE OF LINE EVENTS
1) NODE 1 RECEIVES TOKEN FROM NODE 52) NODE 1 TRANSMITS TO NODE 5
A) ISSUES FBE TO NODE 5B) NODE 5 IS READY TO RECEIVE SO IT ISSUES AN ACK C) NODE 1 NOW TRANSMITS THE DATAD) NODE 5 RECEIVES THE DATA ERROR FREE AND ISSUES AN ACK
3) NODE 1 PASSES TOKEN TO NODE 24) NODE 2 DOES NOT NEED TO TRANSMIT AND PASSES THE TOKEN TO NODE 35) NODE 3 NEEDS TO TRANSMIT TO NODE 4
A) ISSUES AN FBE TO NODE 4B) NODE 4 IS NOT READY TO RECEIVE AND IT ISSUES A NAK
6) NODE 3 PASSES THE TOKEN TO NODE 47) NODE 4 PASSES THE TOKEN TO NODE 58) GO TO STEP 1
1818
SYSTEM DESCRIPTION
MICROCONTROLLER INTERFACE
COM20051 ARCNET network core contains 1Kbyte of RAM and 11 registers. The internal RAMis accessed via a pointer-based scheme (refer tothe Sequential Access Memory section), and theinternal registers are accessed via directaddressing. The ARCNET core bus interface isdesigned to be flexible so that it is independentof the 80C32 speed.
The COM20051 provides for no wait statearbitration via direct addressing to its internalregisters and a pointer based addressingscheme to access its internal RAM. Note that at5 Mbps data rate, the internal arbiter must beslowed down using the SLOWARB bit of theSetup Register. The pointer may be used in theauto-increment mode for typical sequentialbuffer emptying or loading, or it can be taken outof the auto-increment mode to perform out ofsequence accesses to the RAM. The data withinthe RAM is accessed through the Data Register.Data being read is prefetched from memory andplaced into the Data Register for themicrocontroller to read. During a write operation,the data is stored in the Data Register and thenwritten into memory. Whenever the pointer isloaded for reads with a new value, data isimmediately prefetched to prepare for the firstread operation.
TRANSMISSION MEDIA INTERFACE
Figure 6 illustrates the COM20051 interface tothe transmission media used to connect the nodeto the network. Table 2 lists different types ofcable which are suitable for ARCNET
applications.1 The user may interface to thecable of choice in one of three ways:1 Please refer to TN7-5 - Cabling Guidelines for theCOM20020 ULANC, available from SMSC, forrecommended cabling distance, termination, and nodecount for ARCNET nodes.
Traditional Hybrid Interface
The Traditional Hybrid Interface is that which isused with previous ARCNET devices. TheHybrid Interface is recommended if the node is tobe placed in a network with other Hybrid-Interfaced nodes. The Traditional HybridInterface is for use with nodes operating at 2.5Mbps only. The transformer coupling of theHybrid offers isolation for the safety of thesystem and offers high Common ModeRejection. The Traditional Hybrid Interface usescircuits like SMSC's HYC9068 or HYC9088 totransfer the pulse-encoded data between thecable and the COM20051. The COM20051transmits a logic "1" by generating two 100nSnon-overlapping negative pulses, nPULSE1 andnPULSE2. Lack of pulses indicates a logic "0".The nPULSE1 and nPULSE2 signals are sent tothe Hybrid, which creates a 200nS dipulse signalon the medium. During reception, the 200nSdipulse appearing on the media is coupledthrough the transformer of the LAN Driver, whichproduces a positive pulse at the RXIN pin of theCOM20051. The pulse on the RXIN pinrepresents a logic "1". Lack of pulse representsa logic "0". Typically, RXIN pulses occur atmultiples of 400nS. The COM20051 can toleratedistortion (bit jitter) of plus or minus 100nS andstill correctly capture and convert the RXINpulses to NRZ format. Figure 8 illustrates theevents which occur in transmission or receptionof data consisting of 1, 1, 0.
Backplane Configuration
The Backplane Configuration is recommendedfor cost-sensitive, short-distance applications likebackplanes and instrumentation. This mode isadvantageous because it saves components,cost, and power.
1919
FIGURE 6 – DIPULSE HYBRID CONFIGURATION
FIGURE 7 – COM20051 NETWORK USING RS-485 DIFFERENTIAL TRANSCEIVERS
R X IN
n P U L S E 1
n P U L S E 2
n T X E N
G N D
Tra d i t iona l H y b r i dC o n f i g u r a t i o n
R X IN
n P U L S E 1
n P U L S E 2
1 7 , 1 9 ,4 , 1 3 , 1 4
5 . 6 K1 / 2 W5 . 6 K1 / 2 W
0 . 0 1 u F1 K V
1 2
1 1
- 5 V0 . 4 7
u F1 0
u F+
3
0 . 4 7 u F+
+ 5 V
u F1 0
6
H Y C 9 0 8 8H Y C 9 0 6 8 o r
N /C
C O M 2 0 0 5 1
COM20051 COM20051 COM20051
+VCC
RBIAS+VCC +VCC
RBIASRBIAS
RT RT
75176B or Equiv.
2020
FIGURE 8 – DIPULSE WAVEFORM FOR BIT DATA OF 1-1-0
20MHZ
CLOCK
(FOR REF.ONLY)
nPULSE1
nPULSE2
DIPULSE
RXIN
1 0
100ns
100ns
200ns
400ns
1
2121
Since the Backplane Configuration encodes datadifferently than the traditional HybridConfiguration, nodes utilizing the BackplaneConfiguration cannot communicate directly withnodes utilizing the Traditional HybridConfiguration.
The Backplane Configuration does not isolatethe node from the media nor protect it fromCommon Mode noise, but Common Mode Noiseis less of a problem in short distances.
The COM20051 supplies a programmable outputdriver for Backplane Mode operation. Apush/pull or open drain driver can be selected byprogramming the P1MODE bit of the SetupRegister (see register descriptions for details.)The COM20051 defaults to an open drain output.
The Backplane Configuration provides for directconnection between the COM20051 and thephysical medium in open drain configuration ofthe output driver. Only one pull-up resistor (foropen drain only) is required somewhere on themedia (not on each individual node). ThenPULSE1 signal, in this mode, is an open drainor push/pull driver and is used to directly drivethe media. It issues a 200nS negative pulse totransmit a logic "1". Note that when used in theopen-drain mode, the COM20051 does not havea fail/safe input on the RXIN pin.
The nPULSE1 signal actually contains a weakpull-up resistor. This pull-up should not take theplace of the resistor required on the media foropen drain mode. In typical applications, theserial backplane is terminated at both ends and abias is provided by the external pull-up resistor.
The RXIN signal is directly connected to thecable via an internal Schmitt trigger. A negativepulse on this input indicates a logic "1". Lack ofpulse indicates a logic "0". For typical single-ended backplane applications, RXIN is
connected to nPULSE1 to make the serialbackplane data line. A ground line (from thecoax or twisted pair) should run in parallel withthe signal. For applications requiring differenttreatment of the receive signal (like filtering orsquelching), nPULSE1 and RXIN remain asindependent pins. External differentialdrivers/receivers for increased range andcommon mode noise rejection, for example,would require the signals to be independent ofone another. When the device is in BackplaneMode, the clock provided by the nPULSE2 signalmay be used for encoding the data into adifferent encoding scheme or other synchronousoperations needed on the serial data stream.
Differential Driver Configuration
The Differential Driver Configuration is a specialcase of the Backplane Mode. It is a DC coupledconfiguration recommended for applications likecar-area networks (CAN) or other cost-sensitiveapplications which do not require directcompatibility with existing ARCNET nodes anddo not require isolation. Figure 7 illustrates thisconfiguration.
The Differential Driver Configuration cannotcommunicate directly with nodes utilizing theTraditional Hybrid Configuration. Like theBackplane Configuration, the Differential DriverConfiguration does not isolate the node from thephysical medium.
The Differential Driver interface includes aRS485 Driver/Receiver to transfer the databetween the cable and the COM20051. ThenPULSE1 signal transmits the data, provided thenTXEN signal is active. The nPULSE1 signalissues a 200nS negative pulse to transmit a logic"1". The RXIN pin receives the data. Anegative pulse on this input indicates a logic "1".Lack of pulse indicates a logic "0". Thetransmitter portion of the COM20051 is disabledduring reset and the nPULSE1, nPULSE2 andnTXEN pins are inactive.
2222
Table 2 - Typical Media
CABLE TYPENOMINAL
IMPEDANCE
ATTENUATIONPER 1000 FT.
AT 5MHZ
RG-62 Belden #86262 93 5.5dB
RG-59/U Belden#89108
75 7.0dB
RG-11/U Belden#89108
75 5.5dB
IBM Type 1* Belden#89688
150 7.0dB
IBM Type 3* TelephoneTwisted Pair Belden#1155A
100 17.9dB
COMCODE 26 AWGTwisted Pair Part #105-064-703
105 16.0dB
*Non-plenum-rated cables of this type are also available.
Note: For more detailed information on Cabling options including RS-485, transformer-coupled RS-485and Fiber Optic interfaces, please refer to TN7-5 - Cabling Guidelines for the COM20020 ULANC,available from Standard Microsystems Corporation.
2323
FIGURE 9 – ARCNET CORE BLOCK DIAGRAM
MICRO-SEQUENCER
ANDWORKING
REGISTERS
STATUS/COMMANDREGISTER
RESETLOGIC
RECONFIGURATIONTIMER
NODE IDLOGIC
TX/RXLOGIC
ADDITIONALREGISTERS
ADDRESSDECODINGCIRCUITRY 1K x 8
AD0-AD7
BUSARBITRATIONCIRCUITRY
nPULSE1nPULSE2nTXEN
nINTR
nRESET IN
RAM
ALE
nRD
nWR
nCS
RXIN
20 MHz or 40 MHz CORE CLOCK
2424
ARCNET CORE FUNCTIONAL DESCRIPTION
MICROSEQUENCER
The ARCNET core contains an internalmicrosequencer which performs all of the controloperations necessary to carry out the ARCNETprotocol. It consists of a clock generator, a 544 x8 ROM, a program counter, two instructionregisters, an instruction decoder, a no-opgenerator, jump logic, and reconfiguration logic.
The ARCNET core derives The Program CounterClock and Instruction Execution Clock from theSYSTEM CLOCK. If the system clock is 40 MHzthe Program Counter Clock runs at 10 MHz andthe Instruction Execution Clock runs at 5 MHz. Ifthe System Clock is 20 MHz the above clocksrun at 5 MHz and 2.5 MHz respectively. Themicroprogram is stored in the ROM and theinstructions are fetched and then placed into theinstruction registers. One register holds the opcode, while the other holds the immediate data.Once the instruction is fetched, it is decoded bythe internal instruction decoder, at which pointthe ARCNET core proceeds to execute theinstruction. When a no-op instruction isencountered, the microsequencer enters a timedloop and the program counter is temporarilystopped until the loop is complete. When a jumpinstruction is encountered, the program counteris loaded with the jump address from the ROM.The ARCNET core contains an internalreconfiguration timer which interrupts themicrosequencer if it has timed out. At this pointthe program counter is cleared and theMYRECON bit of the Diagnostic Status Registeris set.
INTERNAL REGISTERS
The ARCNET core contains eight internalregisters. Tables 4 and 5 illustrate the ARCNETcore register map. Reserved locations shouldnot be accessed. All undefined bits are read asundefined and must be written as logic "0".
Interrupt Mask Register (IMR) (Location+00Hex)
The ARCNET core is capable of generating aninterrupt signal when certain status bits becometrue. A write to the IMR specifies which statusbits will be enabled to generate an interrupt. Thebit positions in the IMR are in the same positionas their corresponding status bits in the StatusRegister and Diagnostic Status Register. A logic"1" in a particular position enables thecorresponding interrupt. The Status bits capableof generating an interrupt include the ReceiverInhibited bit, New Next ID bit, Excessive NAK bit,Reconfiguration Timer bit, and TransmitterAvailable bit. No other Status or DiagnosticStatus bits can generate an interrupt.
The five maskable status bits are ANDed withtheir respective mask bits, and the results areORed to produce the interrupt signal. An RIor TA interrupt is masked when thecorresponding mask bit is reset to logic "0", butwill reappear when the corresponding mask bit isset to logic "1" again, unless the interrupt statuscondition has been cleared by this time. ARECON interrupt is cleared when the "ClearFlags" command is issued. An EXCNAKinterrupt is cleared when the "POR Clear Flags"command is issued. A New Next ID interrupt iscleared by reading the New Next ID Register.The Interrupt Mask Register defaults to the value0000 0000 upon hardware reset only. Refer toTable 3 on the following page.
2525
Table 3 - Cleaning Interrupt BitInterrupt Type Cleaning Interrupt Bit
RI Issue "Enable Receive to Page Fnn" commandEXCNAK Issue "Clean Flags" Command with "p" bit setRECON Issue "Clear Flags" Command with "r" bit set
New Next ID Read New Next ID RegisterTA Issue "Enable Transmit From Page Fnn"
Command
Table 4 – Read Register Summary
R E G I S T E RO F F S E T
A D D R E S SR E A D
M S B L S B
S TATUS
DIAG.S TATUS
A D D R E S SP T R H I G HA D D R E S SP T R L O W
DATA
R E S E R V E D
C O N F I G -U R A T I O N
T E N T I D
N O D E I D
S E T U P
N E X T I D
00
01
02
03
04
05
06
07
RI
M Y-R E C O N
RDDATA
A7
D7
X
R E S E T
TID7
NID7
P 1 M O D E
NXTID7
F O U RN A K S
NXTID6
X
D U P I D
AUTO-INC
A6
D6
X
C C H E N
TID6
NID6
X
RCVACT
X
A5
D5
X
T X E N
TID5
NID5
ET3
NXTID5
P O R
T O K E N
X
A4
D4
X
ET1
TID4
NID4
R C V _ALL
NXTID4
TEST
E X C N A K
X
A3
D3
X
ET2
TID3
NID3
C K P 3
NXTID3
R E C O N
TENTID
X
A2
D2
X
BACK-P L A N E
TID2
NID2
C K P 2
NXTID2
T M A
N E WNEXTID
A9
A1
D1
X
SUB-AD1
TID1
NID1
C K P 1
NXTID1
TA
X
A8
A0
D0
X
SUB-AD0
TID0
NID0
S L O WA R B
NXTID0
IRR X 095 M B S D E C 3 D E C 2 D E C 1 EXT INT1 INT0
NOTE: The SLOWARB b i t must be set fo r 5 Mbps operat ion.
R E S E R V E D X X X X X X X X 08
2626
Table 5 – Write Register Summary
REGISTEROFFSET
ADDRESSWRITE
MSB LSB
INTERRUPT
COMMAND
ADDRESSPTR HIGH
ADDRESSPTR LOW
DATA
RESERVED
CONFIG-URATION
TENTID
NODEID
SETUP
NEXT ID
00
01
02
03
04
05
06
07
RI
RDDATA
A7
D7
0
RESET
TID7
NID7
0 0
0
D6
AUTO-INC
A6
D6
0
CCHEN
TID6
NID6
0
D5
0
A5
D5
0
TXEN
TID5
NID5
0
0
D4
0
A4
D4
0
ET1
TID4
NID4
0
EXCNAK
D3
0
A3
D3
0
ET2
TID3
NID3
0
RECON
D2
0
A2
D2
0
BACK-PLANE
TID2
NID2
0
NEW
D1
A9
A1
D1
0
SUB-AD1
TID1
NID1
0
TA
D0
A8
A0
D0
0
SUB-AD0
TID0
NID0
0
MASK
D7
P1MODEFOURNAKS
ET3RCV_ALL
CKP3 CKP2 CKP1SLOWARB
NEXTID
IRRX DEC35MBS EXTDEC2 DEC1 INT1 INT009
NOTE: The SLOWARB bit must be set for 5 Mbps operation.
RESERVED08 X X X X X X X X
2727
Interrupt Routing Register (Location +09HEX)
The Interrupt Routing Register (IRR) routes theinterrupt generated by the ARCNET core to theappropriate 80C32 interrupt input (INT0 or INT1)or to one of the eight general purpose digital I/Oports (P1.0-1.7) of the 80C32. The interruptrouting operates on a priority driven schemewhere if two bits are enabled the highest priorityalways wins. INT0 has highest priority followedby INT1 then EXT. The nINT0 and nINT1 bitsroute the interrupt signal to either the nINT0 ornINT1 pin of the 80C32. The 80C32 nINT1 andnINT0 inputs are wire ANDed with the routedinterrupt. This allows the 80C32's interrupts to beused for more than one source. If manyinterrupts are being used in the system, the
COM20051 supports the use of an externalinterrupt controller to arbitrate simultaneousinterrupts. External interrupt controllers aresupported by programming the EXT bit of theIRR. This will cause the interrupt signal to bepresent on one of the Port 1 pins as programmedby Bits 3 - 5.
The 5 Mbps bit programs the ARCNET core tooperate at a 5 Mbps data rate. The 5 Mbps bitcauses the clock to the ARCNET core to doubleits frequency from 20MHz to 40MHz. 5 Mbpsoperation requires the SLOWARB bit of theSETUP register to be set. Failure to set theSLOWARB bit may result in errors whenaccessing the ARCNET buffer RAM.
Table 6 - Interrupt Routing RegisterBIT BIT NAME SYMBOL DESCRIPTION
6 5 Mbps Enable 5MBPS Causes the ARCNET core to operate at a 5 Mbpsdata rate. Defaults to 0.
3-5 Port 1 BitAssignment
DEC1 - 3 Selects one of the eight Port 1 bits to output theinterrupt on. 000 - P1.0001 - P1.1010 - P1.2011 - P1.3100 - P1.4101 - P1.5110 - P1.6111 - P1.7Defaults to 000 (P1.0).
2 External InterruptEnable
EXT Enables routing of the ARCNET interrupt onto onthe Port 1 pins. Defaults to 0.
1 Interrupt 1Enable.
INT1 Enables wire Oring of the ARCNET interrupt withthe INT1 pin. Defaults to 0.
0 Interrupt 0Enable.
INT0 Enables wire ORing if the ARCNET interrupt withthe INT0 pin. Defaults to 0.
2828
Data Register (Location +04Hex)
This read/write 8-bit register is used as thechannel through which the data to and from theRAM passes. The data is placed in or retrievedfrom the address location presently specified bythe address pointer. The contents of the DataRegister are undefined upon hardware reset. Inthe case of READ operation, the Data Register isloaded with the contents of ARCNET CoreInternal RAM upon writing Address Pointer Low-only once.
Tentative ID Register (Location +07Hex)
The Tentative ID Register is a read/write 8-bitregister accessed when the Sub Address Bitsare set up accordingly (please refer to theConfiguration Register description). TheTentative ID Register can be used while thenode is on-line to build a network map of thosenodes existing on the network. It minimizes theneed for operator interaction with the network.The node determines the existence of othernodes by placing a Node ID value in theTentative ID Register and waiting to see if theTentative ID bit of the Diagnostic Status Registergets set. The network maps developed by thismethod has only historical value, since nodesmay join or depart from the network at any time.When using the Tentative ID feature, a nodecannot detect the existence of the next logicalnode to which it passes the token. The Next IDRegister will hold the ID value of that node. TheTentative ID Register defaults to the value 00000000 upon hardware reset only.
Node ID Register (Location +07Hex)
The Node ID Register is a read/write 8-bitregister accessed when the Sub Address Bitsare set up accordingly (please refer to theConfiguration Register). The Node ID Registercontains the unique value which identifies thisparticular node. Each node on the network mustoccupy a unique Node ID value at all times. TheDuplicate ID bit of the Diagnostic Status Registerhelps the user find a unique Node ID. Refer tothe Initialization Sequence section for furtherdetail on the use of the DUPID bit. The
microsequencer of the ARCNET core does notwake up until a Node ID other than zero iswritten into the Node ID Register. During thistime, no microcode is executed, no tokens arepassed by this node, and no reconfigurations arecaused by this node. Once a non-zero Node IDis placed into the Node ID Register, the corewakes up but will not join the network until theTXEN bit of the Configuration Register is set.While the Transmitter is disabled, the Receiverportion of the device is still functional and willprovide the user with useful information aboutthe network. The Node ID Register defaults tothe value 0000 0000 upon hardware reset only.
Next ID Register (Location +07Hex)
The Next ID Register is an 8-bit, read-onlyregister, accessed when the sub-address bits areset up accordingly (please refer to theConfiguration Register). The Next ID Registerholds the value of the Node ID to which theCOM20051 will pass the token. When used inconjunction with the Tentative ID Register, theNext ID Register can provide a complete networkmap. The Next ID Register is updated each timea node enters/leaves the network or when anetwork reconfiguration occurs. Each time themicrosequencer updates the Next ID Register, aNew Next ID interrupt is generated. This bit iscleared by reading the Next ID Register. Defaultvalue is 0000 0000 upon hardware or softwarereset.
Status Register (Location +00Hex)
The ARCNET Status Register is an 8-bit read-only register. All of the bits, except for bits 5 and6, are software compatible with previous SMSCARCNET devices. In previous SMSC ARCNETdevices the Extended Timeout status wasprovided in bits 5 and 6 of the Status Register.In the COM20020, the COM20020-5,COM20010, COM90C66, and the COM90C165,these bits exist in and are controlled by theConfiguration Register. The Status Registercontents are defined as in Table 6, but aredefined differently during the CommandChaining operation. Please refer to theCommand Chaining section for the definition of
2929
the Status Register during Command Chainingoperation. The Status Register defaults to thevalue 1XX1 0001 upon either hardware orsoftware reset.
Diagnostic Status Register (Location +01Hex)
The Diagnostic Status Register contains sevenread-only bits which help the user troubleshootthe network or node operation. Variouscombinations of these bits and the TXEN bit ofthe Configuration Register represent differentsituations. All of these bits, except the ExcessiveNAK bit and the New Next ID bit, are reset tologic "0" upon reading the Diagnostic StatusRegister or upon software or hardware reset.The EXCNAK bit is reset by the "POR ClearFlags" command upon software or hardwarereset. The Diagnostic Status Register defaults tothe value 0000 000X upon either hardware orsoftware reset.
Command Register (Location +01Hex)
Execution of commands are initiated byperforming write operations to this register. Anycombinations of written data other than thoselisted in Table 8 are not permitted and may resultin incorrect chip and/or network operation.
Address Pointer Registers (Location +02Hex,+03Hex)
These read/write registers are each 8-bits wideand are used for addressing the internalARCNET RAM. New pointer addresses shouldbe written by first writing to the High Register andthen writing to the Low Register because writingto the Low Register loads the address. Thecontents of the Address Pointer High and LowRegisters are undefined upon hardware reset.
Configuration Register (Location +06Hex)
The Configuration Register is a read/writeregister which is used to configure the differentmodes of the ARCNET core. The ConfigurationRegister defaults to the value 0001 1000 uponhardware reset only.
Setup Register (Location +07Hex)
The Setup Register is a read/write 8-bit registeraccessed when the Sub Address Bits are set upaccordingly (see the bit definitions of theConfiguration Register). The Setup Registerallows the user to change the network speed(data rate) or the arbitration speedindependently, invoke the Receive All feature,change the nPULSE1 driver type, and reduceprotocol timeouts by a factor of 3. The data ratemay be slowed to 156.25 Kbps and/or thearbitration speed may be slowed by a factor oftwo. The SLOWARB must be set to a 1 for the 5Mbps operation. The Setup Register defaults tothe value 0000 0000 upon hardware reset only.
3030
Table 7 - Status RegisterBIT BIT NAME SYMBOL DESCRIPTION7 Receiver
InhibitedRI This bit, if high, indicates that the receiver is not enabled
because either an "Enable Receive to Page fnn" commandwas never issued, or a packet has been deposited into theRAM buffer page fnn as specified by the last "Enable Receiveto Page fnn" command. No messages will be received untilthis command is issued, and once the message has beenreceived, the RI bit is set, thereby inhibiting the receiver. TheRI bit is cleared by issuing an "Enable Receive to Page fnn"command. This bit, when set, will cause an interrupt if thecorresponding bit of the Interrupt Mask Register (IMR) is alsoset. When this bit is set and another station attempts to senda packet to this station, this station will send a NAK.
6,5 (Reserved) These bits are undefined.
4 Power On Reset POR This bit, if high, indicates that the ARCNET core has beenreset by either a software reset, a hardware reset, or writing00H to the Node ID Register. The POR bit is cleared by the"Clear Flags" command.
3 Test TEST This bit is intended for test and diagnostic purposes. It is alogic "0" under normal operating conditions.
2 Reconfiguration RECON This bit, if high, indicates that the Line Idle Timer has timedout because the RXIN pin was idle for 82 S. The RECON bitis cleared during a "Clear Flags" command. This bit, whenset, will cause an interrupt if the corresponding bit in the IMRis also set. The interrupt service routine should consist ofexaming the MYRECON bit of the Diagnostic Status Registerto determine whether there are consecutive reconfigurationscaused by this node.
1 TransmitterMessageAcknowledged
TMA This bit, if high, indicates that the packet transmitted as aresult of an "Enable Transmit from Page fnn" command hasbeen acknowledged. This bit should only be considered validafter the TA bit (bit 0) is set. Broadcast messages are neveracknowledged. The TMA bit is cleared by issuing the "EnableTransmit from Page fnn" command.
0 TransmitterAvailable
TA This bit, if high, indicates that the transmitter is available fortransmitting. This bit is set when the last byte of scheduledpacket has been transmitted out, or upon execution of a"Disable Transmitter" command. The TA bit is cleared byissuing the "Enable Transmit from Page fnn" command afterthe node next receives the token. This bit, when set, willcause an interrupt if the corresponding bit in the IMR is alsoset.
3131
Table 8 - Diagnostic Status Register
BIT BIT NAME SYMBOL DESCRIPTION
7 MyReconfiguration
MY-RECON
This bit, if high, indicates that a past reconfiguration wascaused by this node. It is set when the Lost Token Timertimes out, and is typically read following an interrupt caused byRECON. Refer to the Improved Diagnostics section for furtherdetail.
6 Duplicate ID DUPID This bit, if high, indicates that the value in the Node IDRegister matches both Destination ID characters of the tokenand a response to this token has occurred. The EOTcharacter and the trailing zero's are also verified. A logic "1"on this bit indicates a duplicate Node ID, thus the user shouldwrite a new value into the Node ID Register. This bit is onlyuseful for duplicate ID detection when the device is offline, that is, when the transmitter is off. When the device ison line it will be set every time the device gets the token. Thisbit is reset automatically upon reading the Diagnostic StatusRegister. Refer to the Improved Diagnostics section for furtherdetail.
5 ReceiveActivity
RCVACT This bit, if high, indicates that data activity (logic "1") wasdetected on the RXIN pin of the device. Refer to the ImprovedDiagnostics section for further detail.
4 Token Seen TOKEN This bit, if high, indicates that a token has been seen on thenetwork, sent by a node other than this one. Refer to theImproved Diagnostic section for further detail.
3 Excessive NAK EXCNAK This bit, if high, indicates that either 128 or 4 NegativeAcknowledgements have occurred in response to the FreeBuffer Enquiry. This bit is cleared upon the "POR Clear Flags"command. Reading the Diagnostic Status Register does notclear this bit. This bit, when set, will cause an interrupt if thecorresponding bit in the IMR is also set. Refer to the ImprovedDiagnostics section for further detail.
2 Tentative ID TENTID This bit, if high, indicates that a response to a token whoseDID matches the value in the Tentative ID Register hasoccurred. In addition, the EOT character is checked. Thesecond DID and the trailing zero's are not checked. Sinceeach node sees every token passed around the network, thisfeature can be used with the device on-line in order to buildand update a network map. Refer to the ImprovedDiagnostics section for further detail.
1 New Next ID NEWNXTID
This bit, if high, indicates that the Next ID Register has beenupdated and that a node has either joined or left the network.Reading the Diagnostic Status Register does not clear this bit.This bit, when set, will cause an interrupt if the correspondingbit in the IMR is also set. The bit is cleared by reading theNext ID Register.
1,0 (Reserved) These bits are undefined.
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Table 9 - Command RegisterDATA COMMAND DESCRIPTION
0000 0000 ClearTransmitInterrupt
This command is used only in the Command Chaining operation.Please refer to the Command Chaining section for definition of thiscommand.
0000 0001 DisableTransmitter
This command will cancel any pending transmit command (transmissionthat has not yet started) and will set the TA (Transmitter Available)status bit to logic "1" when the ARCNET core next receives the token.
0000 0010 DisableReceiver
This command will cancel any pending receive command. If theCOM20051 is not yet receiving a packet, the RI (Receiver Inhibited) bitwill be set to logic "1" the next time the token is received. If packetreception is already underway, reception will run to its normalconclusion.
b0fn n100 EnableReceive toPage fnn
This command allows the ARCNET core to receive data packets intoRAM buffer page fnn and resets the RI status bit to logic "0". Thevalues placed in the "nn" bits indicate the page that the data will bereceived into (page 00 or 01). If the value of "f" is a logic "1", an offsetof 256 bytes will be added to that page specified in "nn", allowing a finerresolution of the buffer. Refer to the Selecting RAM Page Size sectionfor further detail. If the value of "b" is logic "1", the device will alsoreceive broadcasts (transmissions to ID zero). The RI status bit is set tologic "1" upon successful reception of a message.
00fn n011 EnableTransmit fromPage fnn
This command prepares the ARCNET core to begin a transmitsequence from RAM buffer page fnn the next time it receives the token.The values of the "nn" bits indicate which page to transmit from (0 or 1).If "f" is logic "1", an offset of 256 bytes is added to that page specified in"nn", allowing a finer resolution of the buffer. Refer to the SelectingRAM Page Size section for further detail. When this command isloaded, the TA and TMA bits are reset to logic "0". The TA bit is set tologic "1" upon completion of the transmit sequence. The TMA bit willhave been set by this time if the device has received an ACK from thedestination node. The ACK is strictly hardware level, sent by thereceiving node before its microcontroller is even aware of messagereception. Refer to Figure 3 for details of the transmit sequence and itsrelation to the TA and TMA status bits.
0000 c101 DefineConfiguration
This command defines the maximum length of packets that may behandled by the device. If "c" is a logic "1", the device handles both longand short packets. If "c" is a logic "0", the device handles only shortpackets.
000r p110 Clear Flags This command resets certain status bits of the COM20051. A logic "1"on "p" resets the POR status bit and the EXCNAK Diagnostic status bit.A logic "1" on "r" resets the RECON status bit.
0000 1000 ClearReceiveInterrupt
This command is used only in the Command Chaining operation.Please refer to the Command Chaining section for definition of thiscommand.
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Table 10 - Address Pointer High Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Read Data RDDATA This bit tells the ARCNET core whether the followingaccess will be a read or write. A logic "1" prepares thedevice for a read, a logic "0" prepares it for a write.
6 Auto Increment AUTOINC This bit controls whether the address pointer willincrement automatically. A logic "1" on this bit allowsautomatic increment of the pointer after each access,while a logic "0" disables this function. Please refer tothe Sequential Access Memory section for further detail.
5-2 (reserved) These bits are undefined.
1-0 Address 9-8 A9-A8 These bits hold the upper two address bits which provideaddresses to RAM.
Table 11 - Address Pointer Low Register
BIT BIT NAME SYMBOL DESCRIPTION
7-0 Address 7-0 A7-A0 These bits hold the lower 8 address bits which providethe addresses to RAM.
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Table 12 - Configuration Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Reset RESET A software reset of the ARCNET core is executed bywriting a logic "1" to this bit. A software reset does notreset the microcontroller interface mode, nor does itaffect the Configuration Register. The only registers thatthe software reset affect are the Status Register, theNext ID Register, and the Diagnostic Status Register.This bit must be brought back to logic "0" to release thereset. The Software Reset applies only to the ARCNETcore. It does not apply to the 8051 microcontroller of theCOM20051.
6 CommandChainingEnable
CCHEN This bit, if high, enables the Command Chainingoperation of the device. Please refer to the CommandChaining section for further details. A low level on thisbit ensures software compatibility with previous SMSCARCNET devices.
5 TransmitEnable
TXEN When low, this bit disables transmissions by keepingnPULSE1, nPULSE2 if in non-Backplane Mode, andnTXENABLE inactive. When high, it enables the abovesignals to be activated during transmissions. This bitdefaults low upon reset. This bit is typically enabledonce the Node ID is determined, and never disabledduring normal operation. Please refer to the ImprovedDiagnostics section for details on evaluating networkactivity.
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Table 12 - Configuration Register
BIT BIT NAME SYMBOL DESCRIPTION
4,3 ExtendedTimeout 1,2
ET1, ET2 These bits allow the network to operate over longerdistances than the default maximum 4 miles bycontrolling the Response, Idle, and ReconfigurationTimes. All nodes should be configured with the sametimeout values for proper network operation. The bitcombinations follow.
2.5 Mbpsoperation Response Idle Time Reconfig ET2 ET1 Time (µS) (µS) Time (mS) 0 0 1193.6 1312 1680 0 1 596.8 656 1680 1 0 298.4 328 1680 1 1 74.7 82 840
5 Mbpsoperation Response Idle Time Reconfig ET2 ET1 Time (µS) (µS) Time (mS) 0 0 596.8 656 840 0 1 298.4 328 840 1 0 74.7 82 840 1 1 37.35 41 420
2 Backplane BACK-PLANE
A logic "1" on this bit puts the device into BackplaneMode signalling which is used for Open Drain andDifferential Driver interfaces.
1,0 SubAddress 1,0
SUBAD 1,0 These bits determine which register at address 07 maybe accessed. The combinations are as follows:
SUBAD1 SUBAD0 Register
0 0 Tentative ID 0 1 Node ID 1 0 Setup 1 1 Next ID
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Table 13 - Setup Register
BIT BIT NAME SYMBOL DESCRIPTION
7 Pulse1 Mode P1MODE This bit determines the type of PULSE1 output driver used inBackplane Mode. When high, a push/pull output is used.When low, an open drain output is used. The default is opendrain.
6 Four NACKS FOUR NACKS This bit, when set, will cause the EXNACK bit in the DiagnosticStatus Register to set after four NACKs to Free Buffer Enquiryare detected by the ARCNET core. This bit, when reset, will setthe EXNACK bit after 128 NACKs to Free Buffer Enquiry. Thedefault is 128.
5 ET3 ET3 This bit, when set, scales down protocol timeout values ofResponse Time and Idle Time but not Reconfiguration Time tooptimize network performance in short topologies. Provides ascaling factor of ÷ 3. Defaults to a zero. Must be reset to beARCNET compliant.
4 Receive All RCVALL This bit, when set, allows the COM20051 to receive all validdata packets on the network, regardless of their destination ID.This mode can be used to implement a network monitor with thetransmitter on- or off-line. Note that ACKs are only sent forpackets received with a destination ID equal to theCOM20051's programmed node ID. This feature can be usedto put the COM20051 in a 'listen-only' mode, where thetransmitter is disabled and the COM20051 is not passingtokens. Defaults low.
3,2,1 ClockPrescaler Bits3,2,1
CKP2,1,0 These bits are used to determine the data rate of theCOM20051. The following table is for a 40MHz crystal:ResponseCKP3 CKP2 CKP1 DIVISOR CLOCK 0 0 0 8 2.5 Mbps 0 0 1 16 1.25 Mbps 0 1 0 32 625 Kbps 0 1 1 64 312.5 Kbps 1 0 0 128 156.25 Kbps 1 0 1 256 Reserved 1 1 0 Reserved 1 1 1 Reserved
NOTE: The lowest data rate achievable by the COM20051 is156.25 Kbps. A divide by 256 is provided for those systemsthat use faster clock speeds. Defaults to 000 or 2.5 Mbps.
0 SlowArbitrationSelect
SLW-ARB This bit, when set, will divide the arbitration clock by 2. Memorycycle times will increase when slow arbitration is selected.
NOTE: For 5 Mbps operation, SLOWARB must be set.Defaults to low.
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FIGURE 10 – SEQUENTIAL ACCESS OPERATION
Address Pointer Register
Low
1K x 8
RAM
10
Data Register
8
I/O Address 04H
I/O Address 03H
10-Bit Counter
MemoryAddress Bus
MemoryData Bus
D0-D7
High
I/O Address 02H
INTERNAL
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INTERNAL RAM
The integration of the 1K x 8 RAM in theARCNET core represents significant real estatesavings. The PC board is now free of thecumbersome external RAM, external latch, andmultiplexed address/data bus and controlfunctions which were necessary to interface tothe RAM.
The integration of RAM represents significantcost savings because it isolates the systemdesigner from the changing costs of externalRAM and it minimizes reliability problems,assembly time and costs, and layout complexity.
Sequential Access Memory
The internal RAM is accessed via a pointer-based scheme. Rather than interfering withsystem memory, the internal RAM is indirectlyaccessed through the Address High and LowPointer Registers. The data is channeled to andfrom the microcontroller via the 8-bit DataRegister. For example: a packet in the internalRAM buffer is read by the microcontroller bywriting the corresponding address into theAddress Pointer High and Low Registers (offsets02H and 03H). Note that the High Registershould be written first, followed by the LowRegister, because writing to the Low Registerloads the address. At this point the deviceaccesses that location and places thecorresponding data into the Data Register. Themicrocontroller then reads the Data Register(offset 04H) to obtain the data at the specifiedlocation. If the Auto Increment bit is set to logic"1", the device will automatically increment theaddress and place the next byte of data intothe Data Register, again to be read by themicrocontroller. This process is continued untilthe entire packet is read out of RAM. Refer toFigure 10 for an illustration of the SequentialAccess operation.
When switching between reads and writes, thepointer must first be written with the startingaddress. At least one cycle time should separatethe pointer being loaded and the first read (seetiming parameters).
Access Speed
The ARCNET core is able to accommodate veryfast access cycles to its registers and buffers.Arbitration to the buffer does not slow down thecycle because the pointer based access methodallows data to be prefetched from memory andstored in a temporary register. Likewise, datato be written is stored in the temporary registerand then written to memory.
A Slow Arbitration Bit is provided in the SetupRegister to slow down the arbitration clock forbuffer accesses at 5 Mbps. The SLOWARB bitmust be set to a "1" for 5 Mbps operation.
SOFTWARE INTERFACE
The 80C32 core interfaces to the ARCNET corevia software by accessing the various registers.These actions are described in the InternalRegisters section. The software flow foraccessing the data buffer is based on theSequential Access scheme. The basic sequenceis as follows:
• Disable Interrupts• Write to Pointer Register High (specifying
Auto-Increment mode.)• Write to Pointer Register Low (this loads the
address.)• Enable Interrupts• Read or write the Data Register (repeat as
many times as necessary to empty or fill thebuffer.)
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• The pointer may now be read to determinehow many transfers were completed.
The software flow for controlling theConfiguration, Node ID, Tentative ID, and NextID registers is generally limited to theinitialization sequence and the maintenance ofthe network map.
Additionally, it is necessary to understand thedetails of how the other Internal Registers areused in the transmit and receive sequences andto know how the internal RAM buffer is properlyset up. The sequence of events that tie theseactions together is discussed as follows.
Selecting RAM Page Size
During normal operation, the 1K x 8 of RAM isdivided into two pages of 512 bytes each. Thepage to be used is specified in the "EnableTransmit (Receive) from (to) Page fnn"command, where "nn" specifies page 0 or 1.This allows the user to have constant controlover the allocation of RAM.
When the Offset bit "f" (bit 5 of the "EnableTransmit (Receive) from (to) Page fnn"command word) is set to logic "1", an offset of256 bytes is added to the page specified. Forexample: to transmit from the second half ofpage 0, the command "Enable Transmit fromPage fnn" (fnn=100 in this case) is issued bywriting 0010 0011 to the Command Register.This allows a finer resolution of the buffer pageswithout affecting software compatibility. Thisscheme is useful for applications whichfrequently use packet sizes of 256 bytes or less,especially for microcontroller systems withlimited memory capacity. The remaining portionsof the buffer pages which are not allocated forcurrent transmit or receive packets may be usedas temporary storage for previous network data,packets to be sent later, or as extra memory forthe system, which may be indirectly accessed.
If the device is configured to handle both longand short packets (see "Define Configuration"command), then the receive page should alwaysbe 512 bytes long because the user never knowswhat the length of the receive packet will be. Inthis case, the transmit page may be made 256bytes long, leaving at least 256 bytes free at anygiven time. Please note that it is theresponsibility of software to reserve 512 bytes forthe receive page if the device is configured tohandle long packets. The ARCNET core doesnot check page boundaries during reception.
If the device is configured to handle only shortpackets, then both transmit and receive pagesmay be allocated as 256 bytes long, allowing tworeceive and two transmit packets.
The general rule which may be applied todetermine where in RAM a page begins is asfollows:
Address = (nn x 512) + (f x 256).
Transmit Sequence
During a transmit sequence, the microcontrollerselects a 256 or 512 byte segment of the RAMbuffer and writes into it. The appropriate buffersize is specified in the "Define Configuration"command. When long packets are enabled, theARCNET core interprets the packet as either along or short packet, depending on whether thebuffer address 2 contains a zero or non-zerovalue. The format of the buffer is shown inFigure 11. Address 0 contains the SourceIdentifier (SID); Address 1 contains theDestination Identifier (DID); Address 2 (COUNT)contains, for short packets, the value 256-N,where N represents the number of informationbytes in the message, or for long packets, thevalue 0, indicating that it is indeed a long packet.In the latter case, Address 3 (COUNT) wouldcontain the value 512-N, where N represents thenumber of information bytes in the message.The SID in Address 0 is used by
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FIGURE 11 – RAM BUFFER PACKET CONFIGURATION
SID
DID
COUNT = 256-N
NOT USED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
NOT USED
SID
DID
0
COUNT = 512-N
NOT USED
DATA BYTE 1
DATA BYTE 2
DATA BYTE N-1
DATA BYTE N
SHORT PACKETFORMAT
LONG PACKETFORMAT
ADDRESS ADDRESS0
1
2
COUNT
255
511
N = DATA PACKET LENGTHSID = SOURCE IDDID = DESTINATION ID(DID = 0 FOR BROADCASTS)
0
1
2
COUNT
511
3
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the receiving node to reply to the transmittingnode. The ARCNET core puts the local ID in thislocation, therefore it is not necessary to write intothis location.
Please note that a short packet may containbetween 1 and 253 data bytes, while a longpacket may contain between 257 and 508 databytes. A minimum value of 257 exists on a longpacket so that the COUNT is expressable ineight bits. This leaves three exception packetlengths which do not fit into either a short or longpacket; packet lengths of 254, 255, or 256 bytes.If packets of these lengths must be sent, the usermust add dummy bytes to the packet in order tomake the packet fit into a long packet. Note thatonly the number of bytes specified in the bytecount plus the three-byte header are transmitted.For example, if the byte count is equal to 253,only three bytes of data will be transmitted plusthe header (SID, DID, Byte Count) for a total ofsix bytes.
Once the packet is written into the buffer, themicrocontroller awaits a logic "1" on the TA bit,indicating that a previous transmit command hasconcluded and another may be issued. Eachtime the message is loaded and a transmitcommand issued, it will take a variable amount oftime before the message is transmitted,depending on the traffic on the network and thelocation of the token at the time the transmitcommand was issued. The conclusion of theTransmit command will generate an interrupt ifthe Interrupt Mask allows it. If the device isconfigured for the Command Chaining operation,please see the Command Chaining section forfurther detail on the transmit sequence. Oncethe TA bit becomes a logic "1", themicrocontroller may issue the "Enable Transmitfrom Page fnn" command, which resets the TAand TMA bits to logic "0". If the message is not aBROADCAST, the ARCNET core automaticallysends a FREE BUFFER ENQUIRY to thedestination node in order to send the message.At this point, one of four possibilities may occur.The first possibility is if a free buffer is availableat the destination node, in which case itresponds with an ACKnowledgement. At thispoint, the ARCNET core fetches the data fromthe Transmit Buffer and performs the transmit
sequence. If a successful transmit sequence iscompleted, the TMA bit and the TA bit are set tologic "1". If the packet was not transmittedsuccessfully, TMA will not be set. A successfultransmission occurs when the receiving noderesponds to the packet with an ACK. Anunsuccessful transmission occurs when thereceiving node does not respond to the packet.
The second possibility is if the destination noderesponds to the Free Buffer Enquiry with aNegative AcKnowledgement. A NAK occurswhen the RI bit of the destination node is a logic"1". In this case, the token is passed on from thetransmitting node to the next node. The nexttime the transmitter receives the token, it willagain transmit a FREE BUFFER ENQUIRY. If aNAK is again received, the token is again passedonto the next node. The Excessive NAK bit ofthe Diagnostic Status Register is used to preventan endless sending of FBE's and NAK's. If nolimit of FBE-NAK sequences existed, thetransmitting node would continue issuing a FreeBuffer Enquiry, even though it wouldcontinuously receive a NAK as a response. TheEXCNAK bit generates an interrupt (if enabled)in order to tell the microcontroller to disable thetransmitter via the "Disable Transmitter"command. This causes the transmission to beabandoned and the TA bit to be set to a logic "1"when the node next receives the token, while theTMA bit remains at a logic "0". Please refer tothe Improved Diagnostics section for furtherdetail on the EXCNAK bit.
The third possibility which may occur after aFREE BUFFER ENQUIRY is issued is if thedestination node does not respond at all. In thiscase, the TA bit is set to a logic "1", while theTMA bit remains at a logic "0". The user shoulddetermine whether the node should try to reissuethe transmit command.The fourth possibility is if a non-traditionalresponse is received (some pattern other thanACK or NAK, such as noise). In this case, thetoken is not passed onto the next node, whichcauses the Lost Token Timer of the next node totime out, thus generating a networkreconfiguration.
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The "Disable Transmitter" command may beused to cancel any pending transmit commandwhen the ARCNET core next receives the token.Normally, in an active network, this command willset the TA status bit to a logic "1" when the tokenis received. If the "Disable Transmitter"command does not cause the TA bit to be set inthe time it takes the token to make a round tripthrough the network, one of three situationsexists. Either the node is disconnected from thenetwork, or there are no other nodes on thenetwork, or the external receive circuitry hasfailed. These situations can be determined byeither using the improved diagnostic features ofthe ARCNET core or using another softwaretimeout which is greater than the worst case timefor a round trip token pass, which occurs whenall nodes transmit a maximum length message.
Receive Sequence
A receive sequence begins with the RI status bitbecoming a logic "1", which indicates that aprevious reception has concluded. Themicrocontroller will be interrupted if thecorresponding bit in the Interrupt Mask Registeris set to logic "1". Otherwise, the microcontrollermust periodically check the Status Register.Once the microcontroller is alerted to the factthat the previous reception has concluded, it mayissue the "Enable Receive to Page fnn"command, which resets the RI bit to logic "0" andselects a new page in the RAM buffer. Again,the appropriate buffer size is specified in the"Define Configuration" command. Typically, thepage which just received the data packet will beread by the microcontroller at this point.
Once the "Enable Receive to Page fnn"command is issued, the microcontroller attendsto other duties. There is no way of knowing howlong the new reception will take, since anothernode may transmit a packet at any time. Whenanother node does transmit a packet to thisnode, and if the "Define Configuration" commandhas enabled the reception of long packets, theARCNET core interprets the packet as either along or short packet, depending on whether thecontent of the buffer location 2 is zero or non-zero. The format of the buffer is shown in Figure12. Address 0 contains the Source Identifier
(SID), Address 1 contains the DestinationIdentifier (DID), and Address 2 contains, for shortpackets, the value 256-N, where N representsthe message length, or for long packets, thevalue 0, indicating that it is indeed a long packet.In the latter case, Address 3 contains the value512-N, where N represents the message length.Note that on reception, the ARCNET coredeposits packets into the RAM buffer in the sameformat that the transmitting node arranges them,which allows for a message to be received andthen retransmitted without rearranging any bytesin the RAM buffer other than the SID and DID.Once the packet is received and stored correctlyin the selected buffer, the ARCNET core sets theRI bit to logic "1" to signal the microcontroller thatthe reception is complete.
COMMAND CHAINING
The Command Chaining operation allowsconsecutive transmissions and receptions tooccur without on-chip 80C32 intervention.Through the use of a dual two-level FIFO,commands to be transmitted and received, aswell as the status bits, are pipelined.
In order for the COM20051 to be compatible withprevious SMSC ARCNET device drivers, thedevice defaults to the non-chaining mode. Inorder to take advantage of the CommandChaining operation, the Command ChainingMode must be enabled via a logic "1" on bit 6 ofthe Configuration Register.
In Command Chaining, the Status Registerappears as in Figure 12.
The following is a list of Command Chainingguidelines for the software programmer. Furtherdetail can be found in the Transmit CommandChaining and Receive Command Chainingsections.
• The device is designed such that theinterrupt service routine latency does notaffect performance.
• Up to two outstanding transmissions andtwo outstanding receptions can be pending
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at any given time. The commands may begiven in any order.
• Up to two outstanding transmit interruptsand two outstanding receive interrupts arestored by the device, along with theirrespective status bits.
• The Interrupt Mask bits act on TTA (RisingTransition on Transmitter Available) fortransmit operations and TRI (RisingTransition of Receiver Inhibited) for receiveoperations. TTA is set upon completion of apacket transmission only. TRI is set uponcompletion of a packet reception only.Typically there is no need to mask the TTAand TRI bits after clearing the interrupt.
• The traditional TA and RI bits are stillavailable to reflect the present status of thedevice.
Transmit Command Chaining
When the microcontroller issues the first "EnableTransmit to Page fnn" command, the ARCNETcore responds in the usual manner by resettingthe TA and TMA bits to prepare for thetransmission from the specified page. The TA bitcan be used to see if there is currently atransmission pending, but the TA bit is reallymeant to be used in the non-chaining mode only.The TTA bits provide the relevant information forthe device in the Command Chaining mode.
In the Command Chaining Mode, at any timeafter the first command is issued, the processorcan issue a second "Enable Transmit from Pagefnn" command. The ARCNET core stores thefact that the second transmit command wasissued, along with the page number.
After the first transmission is completed, theARCNET core updates the Status Register bysetting the TTA bit, which generates an interrupt.The interrupt service routine should read theStatus Register. At this point, the TTA bit will befound to be a logic "1" and the TMA (TransmitMessage Acknowledge) bit will tell the processorwhether the transmission was successful. Afterreading the Status Register, the "Clear TransmitInterrupt"
FIGURE 12 – COMMAND CHAINING STATUS REGISTER QUEUE
TRI RI TA POR TEST RECON
TMA TTA
TMA TTA
TRI
MSB LSB
4444
command is issued, thus resetting the TTA bitand clearing the interrupt. Note that onlythe "Clear Transmit Interrupt" command willclear the TTA bit and the interrupt. It is notnecessary, however, to clear the bit or theinterrupt right away because the status of thetransmit operation is double buffered in order toretain the results of the first transmission foranalysis by the processor. This information willremain in the Status Register until the "ClearTransmit Interrupt" command is issued. Notethat the interrupt will remain active until thecommand is issued, and the second interrupt willnot occur until the first interrupt is acknowledged.The ARCNET core guarantees a minimum of200nS interrupt inactive time interval betweeninterrupts. The TMA bit is also double bufferedto reflect whether the appropriate transmissionwas a success. The TMA bit should only beconsidered valid after the corresponding TTA bithas been set to a logic "1". The TMA bit nevercauses an interrupt.
When the token is received again, the secondtransmission will be automatically initiated afterthe first is completed by using the stored "EnableTransmit from Page fnn" command. Theoperation is as if a new "Enable Transmit fromPage fnn" command has just been issued. Afterthe first Transmit status bits are cleared, theStatus Register will again be updated with theresults of the second transmission and a secondinterrupt resulting from the second transmissionwill occur. The ARCNET core guarantees aminimum of 200ns interrupt inactive time intervalbefore the following edge.
The Transmitter Available (TA) bit of the InterruptMask Register now masks only the TTA bit of theStatus Register, not the TA bit as in the non-chaining mode. Since the TTA bit is only setupon transmission of a packet (not by RESET),
and since the TTA bit may easily be reset byissuing a "Clear Transmit Interrupt" command,there is no need to use the TA bit of the InterruptMask Register to mask interrupts generated bythe TTA bit of the Status Register. In CommandChaining mode, the "Disable Transmitter"command will cancel the oldest transmission.This permits canceling a packet destined for anode not ready to receive. If both packetsshould be canceled, two "Disable Transmitter"commands should be issued.
Receive Command Chaining
Like the Transmit Command Chaining operation,the processor can issue two consecutive "EnableReceive from Page fnn" commands.
After the first packet is received into the firstspecified page, the TRI bit of the Status Registerwill be set to logic "1", causing an interrupt.Again, the interrupt need not be servicedimmediately. Typically, the interrupt serviceroutine will read the Status Register. At thispoint, the RI bit will be found to be a logic "1".After reading the Status Register, the "ClearReceive Interrupt" command should be issued,thus resetting the TRI bit and clearing theinterrupt. Note that only the "Clear ReceiveInterrupt" command will clear the TRI bit and theinterrupt. It is not necessary, however, to clearthe bit or the interrupt right away because thestatus of the receive operation is double bufferedin order to retain the results of the first receptionfor analysis by the processor, therefore theinformation will remain in the Status Registeruntil the "Clear Receive Interrupt" command isissued. Note that the interrupt will remain activeuntil the "Clear Receive Interrupt" command isissued, and the second interrupt will be storeduntil the first interrupt is acknowledged. Aminimum of 200nS interrupt inactive time intervalbetween interrupts is guaranteed.
4545
The second reception will occur as soon as asecond packet is sent to the node, as long as thesecond "Enable Receive to Page fnn" commandwas issued. The operation is as if a new "EnableReceive to Page fnn" command has just beenissued. After the first Receive status bits arecleared, the Status Register will again beupdated with the results of the second receptionand a second interrupt resulting from the secondreception will occur.
In the ARCNET core, the Receive Inhibit (RI) bitof the Interrupt Mask Register now masks onlythe TRI bit of the Status Register, not the RI bitas in the non-chaining mode. Since the TRI bit isonly set upon reception of a packet (not byRESET), and since the TRI bit may easily bereset by issuing a "Clear Receive Interrupt"command, there is no need to use the RI bit ofthe Interrupt Mask Register to mask interruptsgenerated by the TRI bit of the Status Register.
In Command Chaining mode, the "DisableReceiver" command will cancel the oldestreception, unless the reception has alreadybegun. If both receptions should be canceled,two "Disable Receiver" commands should beissued.
RESET DETAILS
Internal Reset Logic
The ARCNET core supports two reset options;software and hardware reset. A software reset isgenerated when a logic "1" is written to bit 7 ofthe Configuration Register. The device remainsin reset as long as this bit is set. The softwarereset does not affect the contents of the AddressPointer Registers, the Configuration Register, theIMR, or the Setup Register. A hardware resetoccurs when a high signal is asserted on thenRESET input. The minimum reset pulse widthis 3.2 s (for 20 MHz core clock, 1.6 s for 40 MHzcore clock) . This pulse width is used by theinternal digital filter, which filters short glitches toallow only valid resets to occur.
Upon reset, the transmitter portion of the deviceis disabled and the internal registers assume
those states outlined in the Internal Registerssection.
After the nRESET signal is removed the usermay write to the internal registers. Since writinga non-zero value to the Node ID Register wakesup the ARCNET core, the Setup Registershould be written before the Node ID Register.Once the Node ID Register is written to, theARCNET core reads the value and executes twowrite cycles to the RAM buffer. Address 0 iswritten with the data D1H and address 1 iswritten with the Node ID. The data pattern D1Hwas chosen arbitrarily, and is meant to provideassurance of proper microsequencer operation.
INITIALIZATION SEQUENCE
When the ARCNET core is powered on theinternal registers may be written to. Since writinga non-zero value to the Node ID Register wakesup the core, the Setup Register should be writtento before the Node ID Register. Until a non-zerovalue is placed into the NID Register, nomicrocode is executed, no tokens are passed bythis node, and no reconfigurations are generatedby this node. Once a non-zero value is placed inthe register, the core wakes up, but the node willnot attempt to join the network until the TXEnable bit of the Configuration Register is set.
Before setting the TX Enable bit, the softwaremay make some determinations. The softwaremay first observe the Receive Activity and theToken Seen bits of the Diagnostic StatusRegister to verify the health of the receiver andthe network.
Next, the uniqueness of the Node ID valueplaced in the Node ID Register is determined.The TX Enable bit should still be a logic "0" untilit is ensured that the Node ID is unique. If thisnode ID already exists, the Duplicate ID bit ofthe Diagnostic Status Register is set after amaximum of 840mS (or 1680mS if the ET1 andET2 bits are other than 1,1). To determine ifanother node on the network already has this ID,the ARCNET core compares the value in theNode ID Register with the DID's of the token,and determines whether there is a response to it.Once the Diagnostic Status Register is read, the
4646
DUPID bit is cleared. The user may then attempta new ID value, wait 840mS before checking theDuplicate ID bit, and repeat the process until aunique Node ID is found. At this point, the TXEnable bit may be set to allow the node to jointhe network. Once the node joins the network, areconfiguration occurs, as usual, thus setting theMYRECON bit of the Diagnostic Status Register.
The Tentative ID Register may be used to build anetwork map of all the nodes on the network,even once the COM20051 has joined thenetwork. Once a value is placed in the TentativeID Register, the ARCNET core looks for aresponse to a token whose DID matches theTentative ID Register. The software can recordthis information and continue placing TentativeID values into the register to continue buildingthe network map. A complete network map isonly valid until nodes are added to or deletedfrom the network. Note that a node cannotdetect the existence of the next logical node onthe network when using the Tentative ID. Todetermine the next logical node, the softwareshould read the Next ID Register.
IMPROVED DIAGNOSTICS
The COM20051 allows the user to bettermanage the operation of the network through theuse of the internal Diagnostic Status Register.
A high level on the My Reconfiguration(MYRECON) bit indicates that the TokenReception Timer of this node expired, causing areconfiguration by this node. After theReconfiguration (RECON) bit of the StatusRegister interrupts the microcontroller, theinterrupt service routine will typically read theMYRECON bit of the Diagnostic Status Register.Reading the Diagnostic Status Register resetsthe MYRECON bit. Successive occurrences of alogic "1" on the MYRECON bit indicates that a
problem exists with this node. At that point, thetransmitter should be disabled so that the entirenetwork is not held down while the node is beingevaluated.
The Duplicate ID (DUPID) bit is used before thenode joins the network to ensure that anothernode with the same ID does not exist on thenetwork. Once it is determined that the ID in theNode ID Register is unique, the software shouldwrite a logic "1" to bit 5 of the ConfigurationRegister to enable the basic transmit function.This allows the node to join the network.
The Receive Activity (RCVACT) bit of theDiagnostic Status Register will be set to a logic"1" whenever activity (logic "1") is detected onthe RXIN pin.
The Token Seen (TOKEN) bit is set to a logic "1"whenever any token has been seen on thenetwork (except those tokens transmitted by thisnode).
The RCVACT and TOKEN bits may help theuser to troubleshoot the network or the node. Ifunusual events are occurring on the network, theuser may find it valuable to use the TXEN bit ofthe Configuration Register to qualify events.Different combinations of the RCVACT, TOKEN,and TXEN bits, as shown indicate differentsituations:
Normal Results:
RCVACT=1, TOKEN=1, TXEN=0: The node isnot part of the network. The network is operatingproperly without this node.
RCVACT=1, TOKEN=1, TXEN=1: The nodesees receive activity and sees the token. Thebasic transmit function is enabled. Network andnode are operating properly.MYRECON=0, DUPID=0, RCVACT=1, TXEN=0,TOKEN=1: Single node network.
4747
Abnormal Results:
RCVACT=1, TOKEN=0, TXEN=X: The nodesees receive activity, but does not see the token.Either no other nodes exist on the network, sometype of data corruption exists, the media driver ismalfunctioning, the topology is set up incorrectly,there is noise on the network, or areconfiguration is occurring.
RCVACT=0, TOKEN=0, TXEN=1: No receiveactivity is seen and the basic transmit function isenabled. The transmitter and/or receiver are notfunctioning properly.
RCVACT=0, TOKEN=0, TXEN=0: No receiveactivity and basic transmit function disabled.This node is not connected to the network.
The Excessive NAK (EXCNAK) bit is used toreplace a timeout function traditionallyimplemented in software. This function isnecessary to limit the number of times a senderissues a FBE to a node with no available buffer.When the destination node replies to 128 FBEswith 128 NAKs or 4 FBEs with 4 NAKs, theEXCNAK bit of the sender is set, generating aninterrupt. At this point the software may abandonthe transmission via the "Disable Transmitter"command. This sets the TA bit to logic "1" whenthe node next receives the token, to allow a
different transmission to occur. The timeoutvalue for the EXNACK bit (128 or 4) isdetermined by the FOUR-NAKS bit on the SetupRegister.
The user may choose to wait for more NAK'sbefore disabling the transmitter by takingadvantage of the wraparound counter of theEXCNAK bit. When the EXCNAK bit goes high,indicating 128 or 4 NAKs, the "POR Clear Flags"command may be issued to reset the bit so that itwill go high again after another count of 128 or 4.The software may count the number of times theEXCNAK bit goes high, and once the final countis reached, the "Disable Transmitter" commandmay be issued.
The New Next ID bit permits the software todetect the withdrawal or addition of nodes to thenetwork.
The Tentative ID bit allows the user to build anetwork map of those nodes existing on thenetwork. This feature is useful because itminimizes the need for human intervention.When a value placed in the Tentative ID Registermatches the Node ID of another node on thenetwork, the TENTID bit is set, telling thesoftware that this NODE ID already exists on thenetwork. The software should periodically placevalues in the Tentative ID Register and monitorthe New Next ID bit to maintain an updatednetwork map.
4848
COM20051 APPLICATIONS INFORMATION
PROGRAMMING THE COM20051 NETWORKCORE
The COM20051 ARCNET core is relativelysimple to program. The ARCNET core wasdesigned to allow the processor to remain incontrol of the node and to perform network flowcontrol with a minimum of processor intervention.There are two methods of operating theARCNET core: in Command Chaining and Non-Command Chaining mode. Command chainingmode permits the processor to pipeline up to twotransmit and two receive commands. In normalNon-Command Chaining mode, themicrocontroller must access the ARCNET corefor each individual transmission and receptionsince the ARCNET core can only handle onetransmit and one receive command at any giventime. The Command Chaining mode permits theARCNET core to handle up to two transmit andtwo receive commands at any given time.Receive and Transmit status bits are buffered foreach command in Command Chaining mode.
The basic software approach can be divided intothree parts: ARCNET initialization, TransmitInterrupt servicing, and Receive Interruptservicing. Both Command and Non-CommandChaining examples will be illustrated. It isstrongly suggested that an interrupt drivenapproach be used since polling methods canresult in lost transmit opportunities and in lostreceptions.
ARCNET Initialization
Basic COM20051 ARCNET core initializationconsists of the following:
1) Programming of the Address DecodeRegister
2) Configuring the Operating Mode (Commandor Non-Command Chaining, Backplane orDipulse operation)
3) Programming the Interrupt Routing Register(IRR)
4) Programming the Data Rate (optional)5) Enabling the Receive All mode (optional)6) Obtaining a Node ID and programming in its
value7) Entering the Network8) Issuing initial Receive commands
Figure 14 is a flowchart of a typical initializationprocedure. Steps 1 through 5 arestraightforward and do not require muchexplanation. Step 6, Selection of a Node ID canbe somewhat more involved depending on theapplication. There are many methods ofobtaining a unique node id for a particular noderanging from simply reading a switch tosophisticated software algorithms. Severalmethods will be discussed but the best methoddepends on the particular application.
Node ID Selection
The ARCNET Protocol is a token passingprotocol that relies on each station to have aunique Node ID in order to permit proper networkoperation. Many methods will be discussed but itis up to the user to choose the right method forhis application.
Method 1 - Hardware Switch Read
This is the simplest and the most common formof obtaining a Node ID for an individual node. Itconsists of adding an eight bit DIP switch andaddress decoder as shown in Figure 15. Asimple read from the microcontroller will obtainthe ID value.
4949
FIGURE 13 – TYPICAL INITIALIZATION PROCEDURE
S T A R T
W R IT E A R C N E T C O R E B A S E A D D R E S S T O D E C O D E R E G I S T E R
A D D R E S S F F F F h
W R I T E T O C O N F I G U R A T IO N
R E G IS T E R . P R O G R A M C H A IN IN G M O D E A N D E N C O D I N G M E T H O D .
P R O G R A M I R R
P R O G R A M D A T A R A T E T H R O U G H
S E T U P R E G IS T E R
E N A B L E R E C E IV E A L L M O D E
T H R O U G H S E T U P R E G IS T E R
O B T A IN A N D P R O G R A M U N I Q U E
ID
C H E C K S T A T U S A N D J O IN N E T W O R K
S E T IM R A N D E N A B L E R E C E IV E R
E N D
5050
FIGURE 14 – NODE ID SELECTION USING A HARDWARE SWITCH READ
Method 2 - Non-Volatile Memory Storage
This method involves the storage of the Node IDin either a PROM, EPROM, or EEPROM. Themicrocontroller simply reads the proper locationand programs the ID value. This method is wellsuited for closed networks that are not expectedto expand or are maintained solely by the OEM.Such examples might include machine controland automobiles.
Method 3 - Hardwire Daisy Chain
The Daisy Chain method uses an additional wirerunning from node to node in a daisy chainedfashion. This type of setup relies on a masternode that uses a fixed ID value that is stored inthe master node's non-volatile memory or byreading a switch. Once the master programs itsID value it brings the additional line low. Thenext node that is in line physically detects the lowlevel on the line and uses a duplicate ID searchalgorithm to detect the first available ID on the
COM20051
ADDRESSDECODER
A15-A0
D7-D0 'LS244DIP
SWITCH
NID DECODE
EN
5151
network. Once this node finds an ID and joinsthe network, it brings its ID line low to allow thenext node to join. This process continues until allnodes have joined the network. Figure 16 showsan example of how this is accomplished.
Method 4 - Duplicate ID Software Search
The Duplicate ID software search is a softwareonly method of locating available node ID valueson a given network. The basic algorithminvolves a sequential search of ID values andchecking their availability by using a combinationof diagnostic bits located within the ARCNETcore of the COM20051. This method is not wellsuited for the initial power-up sequence of anetwork since there are instances in which thealgorithm will assign the same ID to two nodeswhen they power-up simultaneously. Thisoccurs due to basic constraints imposed by theARCNET protocol itself. The Duplicate IDalgorthim is very useful for adding nodes toalready existing networks that use a mix of nodeID selection methods. Please refer to the sectionon Duplicate ID Detection for details regardingthe algorithm.
Entering the Network
After establishing a unique Node ID, theCOM20051 can join the network. Prior toactually joining the network, several diagnosticbits should be checked to ensure that the node isproperly functioning and that the network isfunctioning properly. The DUPID, RCVACT, and
TOKEN bits should all be checked to ensure thatthe network is operating properly. A read of theDiagnostic Status register should be done toclear previous data prior to checking the statusbits. This will ensure that the Diagnostic Statusbits are reflecting the latest status of the network.A period of time lasting 840ms should elapseprior to checking the status bits. The 840msperiod is a worst case situation based on a full255 node network with every node transmitting a512 byte packet. The actual wait time will beless for most systems and should be calculatedbased on the number of nodes and maximumpacket size. Once the wait period is over, theDiagnostic Status bits should read as follows:DUPID = 0, RCVACT = 1, and TOKEN = 1. Anyother combination indicates that a problem existson the network. Once a valid status condition isestablished, the TXEN bit of the ConfigurationRegsiter should be programmed to a '1' to allowthe transmitter output to drive the network. Thenode is now a member of the network.
Initializing Receptions and Interrupt Masking
Normally the receiver is enabled immediatelyafter joining the network. Since a node never willknow when a packet will be transmitted to it, it isadvisable to have the receiver enabled at theearliest time possible. Generally, Enable toReceive commands are given at the end of theinitialization. For systems using the CommandChaining feature, two receive commands shouldbe given. For Non-Command Chaining systems,
5252
FIGURE 15 – DAISY CHAIN METHOD OF NODE ID SELECTION
T TNETWORK CABLE
OUT IN OUT IN OUT IN
COM20051 COM20051 COM20051 COM20051
MASTER SLAVE #1 SLAVE #2 SLAVE #3
LINE 1 LINE 2 LINE 3
TIME
LINE 1
LINE 2
LINE 3
OUT
SLAVE #3 OUT
0
5353
a single Enable to Receive command should beissued.
Interrupt Masking is a critical function in Non-Command Chaining systems. The interrupt maskis critical because it provides the only method ofreleasing interrupts in Non-Command Chainingsystems. For Non-Command Chaining systems,the RI interrupt should be unmasked right afterthe Enable to Receive commands to ensure thatan interrupt will be generated. Note that theinterrupt must be masked to release the interruptonce the packet has been received. ForCommand Chaining systems, the ReceiveInterrupt mask should be enabled and leftenabled prior to the first Enable to ReceiveCommands. The Command Chaining modeutilizes a software Clear Receive Interruptcommand to release the interrupt thus theinterrupt can be left unmasked.
DUPLICATE ID DETECTION (AUTO NODE IDSELECTION)
The Duplicate ID algorithm was introducedpreviously as a software only method ofobtaining unique ID values to join the network.The algorithm uses many of the diagnosticfeatures found in the COM20051 including theRECON, RCVACT, TOKEN, DUPID, andMYRECON diagnostic bits to locate a unique IDvalue. Caution should be used when using thisalgorithm in that it cannot isolate a unique valuewhen two nodes power-on simulatneously orwithin close proximity of each other. Two nodesusing the same ID value will cause the networkto fail.
The basic algorithm operates as follows: TheCOM20051's Node ID is temporaily initialized toFEh. A 52us waiting period is then entered toallow the core to read the new node ID value.This is necessary to allow time for the ARCNETmicrosequencer to read the value from theARCNET Node register. A one second timingloop is then entered in which
several diagnostic bits are sampled in order todetermine if the selected node ID is being usedor not. The first determination made is if theRCVACT (RECEIVER ACTIVITY) and theTOKEN bits are set. If both are reset, this nodeis most likely to be the first node to join thenetwork. If one of these bits is reset, then atiming loop is entered and the bits are sampledagain. Once both bits are found to be set thenthe DUPID bit is sampled. If this bit is set thenthe current node ID is decremented and thetiming loop is restarted. If the DUPID bit is resetthen the program continues in the timing loopand the RECON bit tested after the loop is exitedto determine if a RECON had occurred duringthe sampling of the diagnostic status bits. If theRECON bit is reset then another loop is enteredto synchronize the COM20051 with its TokenRotation timer in order to prevent multiple nodesfrom using the same Node ID. This loopsamples the MYRECON bit which only gets setwhen the node has not seen a token to itself for840ms. While the program is sampling theMYRECON bit, the DUPID bit is checked toprevent two nodes which have reconfiguredclose together from using the same ID. If theDUPID bit is set before the MYRECON bit is setthen another node ID must be found. Once theMYRECON bit is found to be set then theTOKEN bit is checked again to make sure thatanother node has not RECONed just prior to thisnode. If all these conditions are satisfied thenthe TXEN bit of the Configuration Register is setand a transmission is sent out to the same NodeID. The TA and TMA bits are polled for 840ms. Ifthe TMA bit is sampled as set within 840ms thenthe node ID is not valid and the selection processstarts again. In the event that the MYRECON bitis not found to be set, an 840ms timer has beenincorporated into the polling loop to account forthis. The only time the MYRECON bit will not getset is when there is a single node network.Once a valid node ID has been located then thetransmitter is enabled and the initializationprocess is completed.
5454
FIGURE 16 – DUPLICATE ID DETECTION ALGORITHM
Y
A
Y
Y
Y
N
Y
N
READ DIAGNOSTIC STATUS REGISTER
IS RCVACT & TOKEN RESET?
INC. RECON COUNT
IS RECON COUNT = 3?
IS DUPID SET?
IS MYRECON
SET?
DID THE 840mS TIMER EXPIRE?
Y
N
N
Y
N
Y
Y
N
N
B
N
C
Y
N
INIT NODE ID TO FEh
SET RECON COUNT TO ZERO
WAIT 52µS FOR THE CORE TO USE NEW ID
ISSUE CLEAR FLAGS COMMAND
WAIT 82.2µS MIN. FOR RCVACT
IS RCVACT & TOKEN SET?
IS DUPID SET?
DID THE 840mS TIMER EXPIRE?
IS THE RECON BIT SET?
CLEAR THE DIAGNOSTIC STATUS
REGISTER
INITIALIZE THE 840 mS TIMER
HAS A TOKEN BEEN SEEN?
DEC NODE ID
START
D
5555
FIGURE 16 - DUPLICATE ID DETECTION ALGORITHM (continued)
A B
N
Y
N
N
Y
Y
N
Y
N
N
Y
C
D
Y
SET NODE ID = FFh
INITIALIZE THE 840mS TIMER
WAIT 82.2µS FOR RCV ACTIVITY
READ THE DIAGNOSTIC
STATUS REGISTER
IS RCVACT SET?
IS MYRECON SET?
DID THE 840mS TIMER EXPIRE?
SET THE NODE ID TO FEh
SET TXEN BIT
ISSUE A ENABLE TO TX CMD TO YOUR OWN ID
VALUE
INIT. THE 840mS TIMER
IS TA SET?
IS TMA SET?
DID THE 840mS TIMER EXPIRE?
GOOD ID VALUE
5656
DUPID Algorithm Exception Handling
There are two cases that require specialprocessing that the normal Duplicate IDalgorithm does not handle. The first case iswhen the node is the first node to join thenetwork. The second case is when the node isthe second node to join the network.
When a node is the first to join a network it willdetect no receive activity and detect no tokens(i.e. RCVACT = 0 and TOKEN = 0). If this is thecase, a special routine is entered that monitorsthe MYRECON bits and constantly polls theRCVACT, TOKEN, and DUPID bits. If any of theRCVACT, TOKEN, or DUPID bits gets set priorto the MYRECON bit, then another node hasentered the network just prior to this one. If theMYRECON bit sets and the RCVACT, TOKEN,and DUPID bits remain reset then the node takesthe ID value of FFh. Node ID FFh is reserved forthe first node to join the network.
The second case involves a node that is thesecond node to join the network. In this case thenode will detect the presence of tokens andreceive activity (RCVACT & TOKEN = 1), and noduplicate IDs (DUPID = 0). The algorithm willdetect that RECON bit has set. This is becausethe only existing node on the network isundergoing constant reconfigurations because itcannot pass tokens to another node. In order toprevent an endless loop from occurring due tothe RECON test failure, a count of RECON bittests is kept. If three consecutive polls of theRECON bit are positive it can be safely assumedthat this node is the second node to join thenetwork and takes the ID value of FEh.
Basic Transmit and Receive Service Routines
Transmit and Receive Service routines are oftenfound together as part of an single interruptservice routine used to service the ARCNETinterrupt. The COM20051 provides a 1Kx8 RAMfor buffering of both transmit and receive packetsand accommodates two types of packet formats:
A short format which takes a maximum of 253bytes of data and a long format which takes amaximum of 508 bytes of data. Mostindustrial/embedded applications use the short(256 byte) format, thus allowing the RAM tobuffer four packets. The following examples willuse a two packet buffer for receptions and a twopacket buffer for transmissions. Examples areshown for both Command and Non-CommandChaining systems. Figure 18 shows how atypical program will run.
Upon entry into the service routine all relevant8051 registers are pushed onto the stackincluding the PSW and DPTR. The state of theCOM20051 address registers is also saved sothat any procedures that were interrupted in theprocess of accessing the COM20051 RAM arenot corrupted. The COM20051 status register isthen read and stored in a variable. A series ofcase statements then check the bit settings andbranch to the appropriate service routine.
Service Priority
The ARCNET core of the COM20051 cangenerate a single interrupt from multiple sourcesincluding reception of packets, transmission ofpackets, EXcessive NACK counts,RECONfigurations, and New Next ID generation.When testing status bits to determine the sourceof the interrupt it is best to use the followingpriority:
1) RI - Receiver Inhibited (packet received)2) TA - Transmitter Available (packet
transmitted)3) EXNACK - Excessive Number of NACK's to
FBE's4) RECON - either a full or mini RECON was
detected5) New Next ID - the node to which this node is
passing the token to has not responded tothe token pass and this node has found anew id to pass the token to.
5757
FIGURE 17 – TYPICAL PROGRAM EXECUTION
S T A R T
I N I T I A L I Z E 8 0 5 1 P E R I P H E R A L S
E X T E R N A L R A M T E S T
P R O G R A M A R C N E T D E C O D E
A R C N E T R A M T E S T
I N I T I A L I Z E A R C N E T
C O R E
F I N D N O D E I D
E X E C U T E M A I N T A S K
E N D
T X I S R
R X I S R
5858
Receive Interrupt
A basic Receive service routine is shown in theflowchart of Figure 19. The basic concept of theservice routine is not to process the packet databut to remove the packet from the ARCNETbuffer and free the buffer for another reception.This method will minimize the number of missedpackets due to unavailable buffers.
The Receiver Interrupt Service Routine(RX_ISR) will handle one reception at a time andenable another receive command upon exitingthe service routine. Received data is stored inone of four buffers in external RAM. Severalvariables are kept in order to facilitateprocessing. RAM_BUF_REG is a byte wide, bitmapped software register which shows whichexternal buffers are empty so that new data canbe copied. RX_PAGE_REG is a byte wideregister in which the lower nibble contains theARCNET buffer RAM page address in which thelatest reception can be found. The upper nibblecontains the page address in which the nextreceived is to be stored. This register allows theservice routine to track from which page the mostcurrent data can be found when back to backEnable to Receive commands are issued. MI-N_RX_PAGE and MAX_RX_PAGE are twoconstants that contain the page addressboundaries for the ARCNET memory. If it isdesired to allow more RAM for receptions andless RAM for transmissions then these constantsmust be changed accordingly.
Upon entering the RX_ISR the RX_PAGE_REGis read. The lower three bits are masked off andstored as the page address. RAM_BUF_REG isthen read and the first free buffer found is usedto store the packet. Once the data has beencopied, the RAM_BUF_REG is checked to makesure that at least one buffer is empty beforeissuing another receive command. If no buffersare available, the interrupt is cleared and a newcommand is issued, thus discarding the received
packet. This is done so that all receptions arehandled. If it is found that receptions are beingmissed then more buffering on the CPU side isnecessary. If a free buffer exists, the secondreceive command page is then checked to see ifthe maximum page address has been reached. Ifthe page address is at its maximum value, thenthe page address is set to the minimum pageaddress, otherwise the page address isincremented to next page. The Enable toReceive command string is then generated fromthe page address. RX_PAGE_REG is updatedto make the second receive command the firstcommand and the new command will be thesecond command. The actual command is thenissued. The Clear Receive Interrupt command isthen issued and the routine is exited.
Transmit Interrupt Servicing
The Transmit ISR (TX_ISR) services interruptscaused by the TA bit being set. The routine willfirst check the TMA bit to see if the lasttransmission has been received error free. IfTMA is good then another transmission occurs. IfTMA is bad then the last transmission is sentagain and the ISR is exited. Limits can beimposed on the number of re-tries beforeaborting.
Several variables are kept in order to simplifyservicing of the Transmit interrupt.TX_PEND_REG is a byte wide, bit mappedregister that conveys information about whethera packet needs to be transmitted and where it islocated in the ARCNET RAM. The lower nibbleof the register tells the ISR from which externalRAM page the transmit data is to come. Bits 5and 6 are status bits telling the ISR how manytransmit commands are in the CommandChaining pipeline. To identify from whichARCNET buffer page the last transmissionoriginated, a variable called LAST_TX is usedthat contains the page number used in the lastEnable to Transmit command. LAST_TX is usedto re-transmit data when a bad TMA bit is found.
5959
Upon entering the ISR, the status register is readand the TMA bit is checked. If the TMA bit is notset, then the action as described above is taken.If TMA is good then the interrupt is cleared andeither bit 6 or bit 5 of the TX_PEND_REG iscleared depending on the number oftransmissions pending. The configurationregister is then read and the Command Chainingenable bit is checked. If Command Chaining isenabled, then bit 4 of TX_PEND is set, otherwiseit is cleared. A series of case statements arethen executed which read the TX_PEND_REGand look for a set bit. If a bit is set in the lowernibble, it signifies that the ARCNET RAM hasbeen loaded with data and that page is ready tobe transmitted. Software should be written sothat an external routine will copy transmit datainto the ARCNET RAM. This will speed up theISR. Bits 5 and 6 are checked to see that thepipeline is not completely filled. If they are bothset, then the routine is exited. If either one of thebits is reset, then the
pending bit in TX_PEND_REG is reset, bit 5 or6 is set, and an Enable to Transmit command isgiven to the page corresponding to the bitposition in TX_PEND_REG.
Up to two transmit commands can be givenwithin the ISR at any given time. If notransmissions are pending, then the routine isexited without any new transmissions.
Initiating Transmissions
The Transmit Service routine can only executeafter a transmission occurs. Therefore, initialtransmit commands must originate from routinesexternal to the Transmit Interrupt serviceroutine. The Transmit ISR can only transmitpackets if and only if packets are pendingtransmission upon entry into the routine.Normally this is not the case, thus theprogrammer must take care to monitor andupdate the TX_PEND_REG for eachtransmission.
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
TX_PEND_REG
RAM_BUF_REG
RX_PAGE_REG
NOTUSED
TX CMD #2 ISSUED
TX CMD #1 ISSUED
TX PEND. IN
BUFFER 4
NOTUSED
TX PEND. IN
BUFFER 3
TX PEND. IN
BUFFER 2
TX PEND. IN
BUFFER 1
NOTUSED
NOTUSED
NOTUSED
NOTUSED
NOTUSED
NOTUSED
RX BUF2
RX BUF1
RECEIVE COMMAND PAGE #2 RECEIVE COMMAND PAGE #1
6060
FIGURE 18 – RECEIVE INTERRUPT SERVICE ROUTINE
RX_ISR
READ
RX_PAGE REG
PUSH DPTR, PSWSAVE A, HI_ADDR
& LO_ADDRDISABLE INTRPTS
READ STATUSREGISTER;
SAVE ASSTAT_REG
MASK OUT ALLBITS EXCEPT 3 LSB'S TO GETADDR OFFSET
SWAP LOWER &UPPER NIBBLES
TO MAKE 2NDRX_CMD THE IST
READ
RAM_BUF_REG
A
6161
FIGURE 18 – RECEIVE INTERRUPT SERVICE ROUTINE (continued)
N
N
N
Y
Y
Y
R A M B U F F E R1 FREE?
R A M B U F F E R2 FREE?
R A M B U F F E R3 FREE?
SET B IT 0
I N R A M _ B U F
SET B IT 1
I N R A M _ B U F
S E T B I T 2
I N R A M _ B U F
SET B IT 3
I N R A M _ B U F
S E T D P T R
TO START OF
BUF_4
MAX RX_PAGEREACHED?
SET RX_PAGE =
C U R R E N TRX_PAGE
Y NSET RX_PAGE =
MIN_RX_PAGE
ALLE X T E R N A L B U F F E R S
FULL?
Y NI S S U E E N A B L E
TO RECEIVEC O M M A N D
C L E A RINT
EXIT
S E T D P T R T OSTART OF
BUF_1
S E T D P T R T OSTART OF
BUF_2
S E T D P T R T OSTART OF
BUF_3
C O P Y PACKETT O E X T E R N A L R A M
EXT.
EXT.
EXT.
A
6262
FIGURE 19 – TRANSMIT INTERRUPT SERVICE ROUTINE
R E A D A R C N E TS T A T U S R E G .
T M A S E T ?C L E A R T X I N T
( M A S K O F F F O RN O N - C H A I N I N G )
R E A D T X _ P E N D _ R E G
B I T 6 S E T ?C L E A R B I T 5
C L E A R B I T 6
S T O R E T X _ P E N D
C L E A R I N T . ( M A S K O F F F O R
N O N - C H A I N I N G )
3
S E T L A S T _ T X = T X _ O F F S E T
B I T 5 O F T X _ P E N D
S E T ?
S E T B I T 6 A N D S T O R E T X _ P E N D
S E N D E N A B L E T O T R A N S M I I T C M D .
E X I T
C M D C H A I N E N A B L E D ?
U N M A S K I N T E R R U P T
S TA R T
Y N
N
Y
Y
N
N
6363
FIGURE 19 – TRANSMIT INTERRUPT SERVICE ROUTINE (continued)
Y
3
BIT 0 OF TX_PEND
SET?
BIT 4 OF TX_PEND
SET?
BITS 5&6 SET?
SET OFFSET = #013H
CALL SEND_TX_CMD
CLEAR BIT 0 OF TX_PEND
N
N
Y
Y
BIT 4 OF TX_PEND
SET?
Y N
BIT 1 OF TX_PEND
SET?
Y
N
SAME PROCEDURE AS FOR BIT 0 BUT WITH
OFFSET = 33H
BIT 2 OF TX_PEND
SET?
Y
N
SAME PROCEDURE AS FOR BIT 0 BUT WITH
OFFSET = 1BH
BIT 3 OF TX_PEND
SET?
Y
N
SAME PROCEDURE AS FOR BIT 0 BUT WITH
OFFSET = 3BH
EXIT
N
*CCHEN CHECK TO BE IMPLEMENTED
EXIT
EXIT
6464
FIGURE 20 – EXTERNAL TRANSMIT ROUTINE
TRANSMIT
READ STATUS REGISTER
SET?CHK TTA BIT
(FOR CMD. CHAINONLY)
YN
BIT 0 SET?
BIT 2 SET?
SET OFFSET OF TX PAGE
SET OFFSET OF TX PAGE
SET OFFSET OF TX PAGE
ENABLE TOTX COMMAND
RET
READ TX_PEND_REG
BIT6 & BIT 5 SET?
SET BIT 6 OF TX_PEND_REG
AND STORE
N
Y
CMD. CHAINSET?
N
TA BIT
SET OFFSET OF TX PAGE
BIT 1 SET?UNMASK TA
INTERRUPT
SET BIT 6 OF TX_PEND
AND STORE
BIT 5 SET?
6565
FIGURE 20 – EXTERNAL TRANSMIT ROUTINE (continued)
SET DPTR = STARTOF TX BUFFER
RET
PACKET COPY
SET HI_ADDR FORWRITE AT TX PAGEWITH AUTOINC SET& LO_ADDR = 00H
READ DATA, INCREMENT
DPTR & SAVE DPTR
WRITE DATA TOARCNET RAM
READ LO_ADDR_REG
LO_ADDR = 00H
N
6666
USING ARCNET DIAGNOSTICS TO OPTIMIZE YOUR SYSTEM
EXcessive Negative ACKnowledgement(EXNACK) Loops
Under certain conditions (node failure forexample), a particular node's receiver may notbecome available. This will result in a NACK toFBE response each time the transmitter attemptsto transmit a message. This can continueendlessly without CPU intervention and degradenetwork performance. In order to handle suchfailures, the COM20051 incorporates anEXNACK interrupt that will signal the CPU that ithas made a specified number of Free Bufferrequests which have not been acknowledged.The limit is specified by the 4NACKS bit of theSetup register of the ARCNET core. The defaultvalue is 128 re-tries but can be reduced to fourby setting the 4NACKS bit. Once the limit isreached, an interrupt is generated by theARCNET core. Note that FBEs will be issueduntil the CPU takes appropriate action by eitheraborting the transmission or continuing to retry.
The EXNACK (EXcessive NegativeACKnowledge) Interrupt handler is a simpleprocedure. For most applications, the Interrupthandler will abort the transmission by issuing aDisable Transmitter command. A Clear Flagscommand must be issued to release the interruptand clear the EXNACK flag. Note thathousekeeping should be done to signify toexternal procedures that the transmission wasaborted and is still not pending. Figure 22 showsa typical flowchart of a EXNACK ISR.
Generating Network Maps
Most applications will require a table of existingnodes to be stored somewhere in the system forsystem administration and maintainence (it isusually the master node). The DUPID, TENTID,and New Next ID features are used to generatethe Network Map. The map is generated by
synchronizing the node to the token rotation timeusing the DUPID feature. Whenever a node ispart of the network the DUPID bit will set whenthe node's receiver detects its own transmitactivity in response to receipt of the token.Reading the Diagnostic Status register resets theDUPID bit. Resetting the bit and polling until theDUPID is set will synchronize the node the tokenrotation time. At this time a node ID value isprogrammed into the TENTID register. Wait forthe Token or the Recon bits to be set and clearTent-ID bit. Then wait again for the Tent-ID bitto be set during one token rotation time. Thisprocess should continure until all node ID valueshave been accounted for. There is one case inwhich the TENTID does not function. TheTENTID detector cannot detect the node ID towhich the node is passing the token. This isbecause the ARCNET core operates in a half-duplex mode thus blocking the recevier while it istransmitting the token. After compiling a node IDtable using the TENTID feature, the Next IDregister can be read to find out the missing IDvalue.
In order to keep the map updated, the New NextID feature can be used to indicate changes in thenetwork. The New Next ID feature will interruptthe processor any time the Next ID register isupdated. This occurs whenever a node drops(causing a mini-recon) or when a node joins thenetwork (causing a full recon). Whenever theNext ID interrupt is generated, a message shouldbe sent to the Master node identifying a changein the network. The Master node can then updatethe network map accordingly.
Network Mapping While Off-Line
The previous mapping algorithm described a fastmethod of building a network map while on-line(being an active part of the network). Often it isdesirable to build a map while off-line. A similaralgorithm is used, but instead of using theTENTID feature the DUPID feature is used andthe new node IDs are programmed into the nodeID register. Since the node is not an active partof the network, there is no reliable method of
6767
initially timing the token rotation. In order to findan existing ID to time the rotation, an 840mstimer is used. At the end of the 840ms, theDUPID is checked. If it is set then the node IDvalue exists and can be used as a fake ID
(remember the node is not on the network). Thatfirst ID value remains in the node ID register andthe above algorithm is used to determine theremainder of the ID values.
FIGURE 21 – EXCESSIVE NACK INTERRUPT SERVICE ROUTINE
EXNACK ISR
ISSUE DISABLETRANSMITTER
COMMAND
ISSUE CLEARFLAGS CMD.
FREE UP PAGEIN TX_PEND REG
END
6868
FIGURE 22A – ONLINE NETWORK MAPPING ROUTINE
READ DIAG. STATUS REG.
TO CLEAR DUPID
POLL DUPID BIT
DUPID SET?
N
PROGRAMTENTID VALUE
POLL DUPID BIT
DUPID SET?
N
READ TENTIDBIT
TENTIDSET?
LOG VALUE INNODE ID TABLE
DECREMENT & PROG. TENT ID
END OFNODE IDS
END
Y
N
N
Y
STARTA
6969
FIGURE 22B – ADDITIONAL CODE - OFFLINE NETWORK MAPPING ROUTINE
POLL DUPID BIT
DUPID SET?
READ DIAG.STATUS REG.
TO CLEAR DUPID
WRITE ID FFH INTO NODE ID
REGISTER
DECREMENT840 MS TIMER
TIMEREXPIRE?
DECREMENT& PROGRAM
NODE ID
AY
N
START
70
CABLING THE COM20051
The COM20051 supports several types of cablesand cable interfaces in either bus or startopologies. The following is a list of
media transceivers, supported media, andsupported topologies:
TRANSCEIVERALLOWED
TOPOLOGIESMAX.DIST.
MAX.NODE
ISOLATIONVOLTAGE
SUPPORTEDMEDIA
HYC9068 Star only 2000ft. N/A <500V Coax
HYC9088 Bus or Star 1000ft.(Coax)400ft.(TP)
8
10
<500V Coax
TwistedPair (TP)
RS-485 Bus 900ft. 32 15VD.C.
Coupled
Twisted Pair
IsolatedRS-485
Bus 700ft. 12 2.5KV TwistedPair
Fiber-Optic Star 3Km N/A >2.5KV Fiber
Note: The above figures are for a 2.5 Mbps data rate. Changing the data rate can significantlyincrease or decrease the line length and node count.
For more information please refer to TN7-5 RS-485 Cabling Guidelines for the COM20020 UniversalLocal Area Network Controller (ULANC) and Experimental Procedure for Verifcation of RS-485 CablingGuidelines or Cabling Alternatives for the COM20020, COM90C66, and COM90C165.
Compatability Considerations
Compatability with existing ARCNET installationsis of importance to some designers. TheCOM20051 is compatible with older ARCNETinstallations when it is operated in dipulsemode at 2.5 Mbps using normal
timeout values. It is suggested that theHYC9068 or HYC9088 transceivers be used tomaintain compatability. The COM20051 is notcompatible with standard ARCNET systemswhen the device is used in backplane mode,when the reduced timeout features are enabled,or at data rates other than 2.5 Mbps.
71
USING THE COM20051'S EMULATION MODE
The COM20051 is unique among specialpurpose 8051 based devices in that it can beused in conjunction with a standard 16MHz80C32 ICE. The COM20051 incorporates anEmulate mode that puts the internalmicrocontroller in a high impedance state so
an external processor (like an ICE) can accessthe internal ARCNET core through theCOM20051's pins. The ICE should be connectedin parallel to the COM20051 as shown in Figure24. The ICE should operate off of its internaloscillator.
FIGURE 23 – CONNECTIONS FOR EMULATION MODE
72
OPERATIONAL DESCRIPTION
MAXIMUM GUARANTEED RATINGS*
Operating Temperature Range....................................................................................... 0oC to +70oC
Storage Temperature Range ..................................................................................... -55oC to +150oC
Lead Temperature (soldering, 10 seconds).............................................................................. +325 oCPositive Voltage on any pin, with respect to ground .............................................................. VCC+0.5V
Negative Voltage on any pin, with respect to ground ..................................................................... -0.5VMaximum VCC .............................................................................................................................. +7V
*Stresses above those listed may cause permanent damage to the device. This is a stress rating onlyand functional operation of the device at these or any other condition above those indicated in theoperational sections of this specification is not implied.
NOTE: When powering this device from laboratory or system power supplies, it is important that theAbsolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibitvoltage spikes or "glitches" on their outputs when the AC power is switched on or off. In addition,voltage transients on the AC power line may appear on the DC output. If this possibility exists it issuggested that a clamp circuit be used.
DC ELECTRICAL CHARACTERISTICS (TA = 0 C - 70 C, VCC = 5.0V ± 10%, VSS = 0V)
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
Low Output Voltage (Ports 1, 2 and 3, ALE, PSEN)
VOL
0.30.451.0
VVV
IOL
= 100 A
IOL
= 1.6 mA
IOL
= 3.5 mA
Low Output Voltage (Port 0)
VOL1
0.30.451.0
VVV
IOL
= 200 A
IOL
= 3.2 mA
IOL
= 7.0 mA
High Output Voltage (Ports 1, 2 and 3, ALE, PSEN)
VOH
VCC
-0.3
VCC
-0.7
VCC
-1.5
VVV
IOH
= -10 A
IOH
= -30 A
IOH
= -60 A
High Output Voltage (Port 0 in ExternalBus Mode)
VOH1
VCC
-0.3
VCC
-0.7
VCC
-1.5
VVV
IOH
= -200 A
IOH
= -3.2 mA
IOH
= -7.0 mA
Input Leakage Current ILI
.02 A ±10 µA V 0<VIN
<VCC
RST PulldownResistor
RRST 50K Ω
Pin Capacitance CIO 10 pF
Power Supply Current ICC
50 mA
Low Input Voltage (XTAL1)
VIL2
1.0 V
73
PARAMETER SYMBOL MIN TYP MAX UNIT COMMENT
High Input Voltage VIH2
4.0 V
Low to High Threshold Input Voltage(RESET, RXIN)
VILH
1.8 V Schmitt Trigger @ 5V
High to Low Threshold Input Voltage(RESET, RXIN)
VIHL
1.2 V Schmitt Trigger @ 5V
Low Output Voltage (PULSE1 in Normal Mode, PULSE2,TXEN)
VOL3
0.4 V ISINK
= 4mA
High Output Voltage (PULSE1 in Normal Mode, PULSE2,TXEN)
VOH3
2.4 V ISOURCE
= 2mA
Low Output Voltage (PULSE1 inBackplane Mode)
VOL4
0.5 V ISINK
= 48mA
Output Capacitance (PULSE1 inBackplane Mode)
COUT2
400 pF
74
TIMING DIAGRAMS
FIGURE 24 – EXTERNAL PROGRAM MEMORY READ CYCLE
A0 - A7 INSTR. IN
A8 - A15
ALE
nPSEN
PORT 0
PORT 2
t11
t10t2
t1
t6
t7
t3t8
t5t4
t9
Parameter min typ max units
t1t2t3t4t5t6t7t8t9t10t11
ALE Pulse WidthAddress Valid to ALE LowALE Low to nPSEN LownPSEN Low to Valid Instruction InputnPSEN Low to Address FloatAddress to Valid Instruction InputAddress Hold after ALEALE Low to Valid Instruction InputnPSEN Pulse WidthInput Instruction Hold after nPSENInput Instruction Float after nPSEN
857
22.6
27
142.50
82.510
207.5
150
37.5
nSnSnSnSnSnSnSnSnSnSnS
AC CHARACTERISTICS (0°C - 70°C, 5.0V ± 10%)100 pF Loading for ALE, PORT0, and nPSEN; 16 MHz Processor Clock
75
FIGURE 25 – EXTERNAL DATA MEMORY READ CYCLE
Parameter min typ max units
ALE
nPSEN
nRD
PORT 0
PORT 2
A0 - A7 DATA IN
A8 - A15 FROM DPH
t1 t2
t3t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t1t2t3t4t5t6t7t8t9
t10t11t12t13
ALE Pulse WidthALE Low to Valid Data InALE Low to nRD or nWR LownRD or nWR High to ALE HighnRD Pulse WidthAddress Valid to ALE LowAddress to Valid Data InnRD Low to Address FloatnRD Low to Valid Data InData Hold after nRDData Float after nRDAddress Valid to nRD or nWR LowAddress Hold after ALE Low
85
137.522.5275
7
0
12027
350238.5102.5
397.50
147.5
55
nSnSnSnSnSnSnSnSnSnSnSnSnS
76
FIGURE 26 – EXTERNAL DATA MEMORY WRITE CYCLE
Parameter m in typ max units
t1 t2
t3
t4
t5
t6
t7
t8
t9
t10
A0 - A7 DATA OUT
A8 - A15 FROM DPH
ALE
nPSEN
nWR
PORT 0
PORT 2
t1t2t3t4t5t6t7t8t9
t10
ALE Pulse WidthALE Low to nRD or nWR LownRD or nWR High to ALE HighWR Pulse WidthAddress Valid to ALE LowData Hold after nWRAddress Valid to nRD or nWR LowAddress Hold after ALE LowData Valid to nWR TransitionData Valid to nWR High
85137.522.5275
712.5120272
287.5
238.5102.5
nSnSnSnSnSnSnSnSnSnS
77
FIGURE 27 – NORMAL MODE TRANSMIT OR RECEIVE TIMING(These signals are to and from the Hybrid)
nPULSE2
Parameter min max units
nPULSE1
t1
* t1, t6 = .25 x ( 1 ) for data rates other than 2.5 Mpbs. data rate
t2
t1
t3
typ
* t2,t7 = 8 x (crystal period) for clock frequencies other than 20 MHz. This period applies to data of two consecutive one's.
RXIN
t6
t7
TXEN
t2
t4t5
LAST BIT(400 nS BIT TIME)
** t4: For clock frequencies other than 20 MHz, t4 = 18 x (crystal period) ± 50 nsec. ** t5: For clock frequencies other than 20 MHz, t5 = 6 x (crystal period) ± 50 nsec.
Note: Clock frequency for 5 Mbps is 40 MHz.
t1t2t3t4t5t6t7
PULSE1, PULSE2 Pulse WidthPULSE1, PULSE2 PeriodPULSE1, PULSE2 OverlapTXEN Low to PULSE1 Low**Beginning of Last Bit Time to TXEN High**RXIN Pulse WidthRXIN Period
-1085025010
100*400*
0
100*400*
+10950350
nSnSnSnSnSnSnS
78
FIGURE 28 – BACKPLANE MODE TRANSMIT OR RECEIVE TIMING(These signals are to and from the differential driver or the cable)
nPULSE1t2
t3
RXIN
t10
t11
nPULSE2 t5 t6
(Internal Clk)
t4
t1
t7
TXEN
t9t8
LAST BIT(400 nS BIT TIME)
* t2,t7,t10 = 4 x (crystal period) for clock frequencies other than 20 MHz.* t3,t11 = 8 x (crystal period) for clock frequencies other than 20 MHz.
This period applies to data of two consecutive one's.
* t5,t6 = 2 x (crystal period) for clock frequencies other than 20 MHz.
** t9: For clock frequencies other than 20 MHz, t9 = 14 x (clock period) ± 50 nsec.
Note: Clock frequency for 5 Mbps is 40 MHz.
Parameter min typ max units
t1t2t3t4t5t6t7t8t9
t10t11
nPULSE2 High to TXEN LownPULSE1 Pulse WidthnPULSE1 PeriodnPULSE2 Low to nPULSE1 LownPULSE2 High TimenPULSE2 Low TimenPULSE2 PeriodnPULSE2 High to TXEN High(first rising edge on nPULSE2 after Last Bit Time)TXEN Low to First nPULSE1 Low**RXIN Pulse WidthRXIN Period
0
0
0
65010
200*400*
100*100*200*
200*400*
50
50
50
750
nSnSnSnSnSnSnSnS
nSnSnS
79
FIGURE 29 – TTL INPUT TIMING ON XTAL1 PIN
FIGURE 30 – RESET AND INTERRUPT TIMING
t1
t3
Parameter
Input Clock High Time
Input Clock Period
min
10
25
max units
nS
nS
XTAL1
t1
t4 Input Clock Frequency125
t2 Input Clock Low Time nS
t3
10
typ
10
t2
40 MHz
t1
Parameter
nRESET IN Pulse Width
min
3.2
max units
µS
nRESET IN t1
t2 nINTR High to Next nINTR Low nS
typ
*200
t2
nINTR
Note: For 5 Mbps operation, t2 is 100 nS.
80
FIGURE 31 – 44 PIN PLCC PACKAGE DIMENSIONS
B
-E-E1E
INDEX CORNER
D1D
G x 45°
-D-
J x 45°, 3 places
SEE DETAIL A
B1
DETAIL A
SEATING PLANE
-C-B2
A .004-C-
SEATING PLANE
A1
C R
e
.007 E D
E3/D3 E2/D2
F x 45°
DIMA
A1B
B1B2C
D/ED1/E1D2/E2D3/E3
eFGJR
44 LEAD.160-.188.090-.120.013-.021.026-.032.025 MIN.020-.045.685-.695.650-.656.600-.630.500 REF.050 BSC.042-.060.042-.048.000-.028.025-.045
Notes:1. Dimensions are in inches.2. Coplanarity is .004" maximum.3. Tolerance on the position of the leads is .007" maximum.4. Package body dimensions D1 and E1 do not include the mold protrusion. Maximum mold protrusion is .010".
81
COM20051 ERRATA SHEET
PAGE SECTION/FIGURE/ENTRY CORRECTIONDATE
REVISED
1 Features/General Description See Italicized Text 3/12/96
4 Overview peer/peer changed topeer-to-peer
3/12/96
5 Description of Pin Functions/Pin No. 34 & 35 See Italicized Text 3/12/96
7 Basic Architecture See Italicized Text 3/12/96
8 Address Decoding See Italicized Text 3/12/96
9 Address Decode Register See Italicized Text 3/12/96
10 ARCNET Network Core See Italicized Text 3/12/96
11 Figure 3/See Note See Italicized Text 3/12/96
12 & 14 Network Protocol/Network Reconfiguration See Italicized Text 3/12/96
13 Figure 4 See Italicized Text 3/12/96
14 All Sections See Italicized Text 3/12/96
15 All Sections See Italicized Text 3/12/96
16 All Sections See Italicized Text 3/12/96
17 Figure 5 See Italicized Text 3/12/96
18 System Description/All Sections See Italicized Text 3/12/96
21 All Sections See Italicized Text 3/12/96
23 Figure 9 See Italicized Text 3/12/96
24 Arcnet Core Functional Description/AllSections
See Italicized Text 3/12/96
25 Table 3/New Table See Italicized Text 3/12/96
28 All Sections See Italicized Text 3/12/96
29 All Sections See Italicized Text 3/12/96
30 Table 7 See Italicized Text 3/12/96
34 Table 12 See Italicized Text 3/12/96
36 Table 13 See Italicized Text 3/12/96
39 Transmit Sequence See Italicized Text 3/12/96
41 Transmit Sequence See Italicized Text 3/12/96
42 Command Chaining See Italicized Text 3/12/96
45 Internal Reset Logic See Italicized Text 3/12/96
47 Last Paragraph See Italicized Text 3/12/96
66 Generating Network Maps See Italicized Text 3/12/96
1996© STANDARD MICROSYSTEMSCORP.
Circuit diagrams utilizing SMSC products are included as a means of illustratingtypical applications; consequently complete information sufficient for constructionpurposes is not necessarily given. The information has been carefully checked andis believed to be entirely reliable. However, no responsibility is assumed forinaccuracies. Furthermore, such information does not convey to the purchaser ofthe semiconductor devices described any licenses under the patent rights of SMSCor others. SMSC reserves the right to make changes at any time in order to improvedesign and supply the best product possible. SMSC products are not designed,intended, authorized or warranted for use in any life support or other applicationwhere product failure could cause or contribute to personal injury or severe propertydamage. Any and all such uses without prior written approval of an Officer of SMSCand further testing and/or modification will be fully at the risk of the customer.
COM20051 Rev. 3/12/96