Cognitive Radio KitTutorial

Khanh Le, Prasanthi Maddala and Ivan Seskar

WINLAB, Rutgers University

Date : June 20, 2012

Motivation

Challenges in Cognitive Radio (CR) and Dynamic Spectrum Access (DSA) techniques

No currently available wideband and real-time radio system for CR and DSA experimentation purpose

Complete Radio system design is a complicated and elaborated process

Solution to resolve this problem ? Yes, CRKIT Framework

With CRKIT Framework, we can abstract the lower level HW design complexities from users

Concentrate more on Creative side of the Wireless problems, less on Engineering Complexity

What is CRKIT Framework ?

Baseband Processor :

FPGA-based off-the-shelf board Multitude of high-speed IOs : GigE, USB, PCIe Control up to 4 full-duplex wideband radios FPGA-based System-on-Chip (FSoC) implementation

Wideband Radio (WDR) Module :

Wideband : tunable range 300MHz to 7.5GHz 25MHz bandwidth 50Msps 12-bit ADC, 200Msps 12-bit DAC 50us switch between frequencies

Actual CogRadio with enclosure, 2 WDRs

CRKIT baseband with 4 stacked radios

CRKIT

HWPlatform

SWPlatform

ORBITIntegration

WidebandRadio

FlexibleBaseband

PHYLayer Exp.

Exp.Scalability

Embedded HOST

FPGA-SoC

Comm.APPs

RadioAPIs

OMF

Baseband with 1 mounted radio

Why CRKIT Framework ?

Focus on APP Development

NOT complete Radio

Abstract lower level design complexities from Users

INNOVATION CYCLE

Live system runs

Focus on Creativity, not Engineering Complexity :

Split Baseband into Static and Dynamic domains : Static - Open-sourced System-on-Chip (complex engineering problem) Dynamic – Swappable Communication

APPs (creative problem)

CRKIT = make real-time and wideband radio a viable solution for large scale experiments.

Build Radio :

Non trivial effort Substantial barrier to entry Many engineering man-hours needed Requires cross-disciplinary expertise

CogRadio from RTS

FSoC Features

Access to lower level resources thru APIs VITA radio transport protocol for radio control Networking capable node Support up to four different dynamic APPs Library of Open-sourced Communication APPs Static Framework utilization level < 15% for V5SX95, even less for newer technologies, for ex. Virtex7 . Transparent to underlying FPGA technology. Can be ported to future HW platforms and newer FPGA technologies.

FSoC Overview FSoC currently consists of following major components :

1. Ethernet Port (static)• Gigabit Ethernet rate• frame synchronization• frame generation/formatting• Support Jumbo frames

2. Packet Processor (static) • Simple packet classification/forwarding

scheme based on IP/UDP• Control packets -> Processor Core• Data packets -> APP• Support a subset of VITA Radio

Transport protocol • Memory management for APP data• IP/VITA packet generation/formatting

3. Application (dynamic)• User specific designs e.g. simple

QPSK/QAM, OFDM, FHSS, DSSS…• Support up to 4 APPs simultaneously

(number of APPs is restricted by FPGA size)

• APPs can be swapped as needed by users. APPs can either reside in RAM or downloadable through Ethernet port.

• Will require partial reconfiguration

4. RF Port (static)• interfacing to DA/AD

5. RMAP Processor (static)• Sub-system interfacing and control• Address decoding• RF SPI Control

6. Processor Core (static)• 32-bit Softcore processor • interfacing to 32MB DRAM• interfacing to 16MB FLASH

Three distinct data flows through system:

1) APP/Processor Core to outbound ethernet port2) Inbound ethernet port to APP3) Inbound ethernet port to Processor Core

CRKIT Transport Layers

Framework domain (static)

Application domain (dynamic)

ETH Layer – Ethernet Physical layer only, no MAC. Only Ethernet frames with Broadcast MAC or matching destination MAC addresses are forwarded to IP layer.

IP Layer (Fast Path) – Hardware based implementation Only a subset of IP and UDP functions. Fast track is reserved for APP data related traffic Data IP packets are routed to the fast track based on specific UDP port number.

IP Layer (Slow Path) – Software based implementation Support TCP as this is done in SW e.g. processor core. Slow track is reserved mostly for control related traffic : CRKit hardware configuration (register map access) and RF control. Any IP packets with UDP port number not matching the fast track UDP port number will be routed to the slow track.

Note : for Address Resolution Protocol (ARP) the IP layer is bypassed, we parse the packets based on Ethernet frame Ethertype field.

VRT Layer – VITA Radio Transport layer, only a subset of VITA standard is supported. VRT layer is optional, bypass this layer if not used. VRT useful to mux multiple radio streams to a single pipe, and demux at the other end. Standardized radio packet types: 1) Data for signal data transmission, could be digitized I/Q samples. 2) Context for control information such as set frequency, power level, bandwidth and so forth.

Framework Domain :

User Specific Layer - since we are in the APP domain, users have their freedom to add any new layers they may wish.

Wireless PHY – again user specific implementation.

Application Domain :

Inbound Packet Processing FlowPCORE CMD FORMAT

If (V==1) then VITA context packetElse non-VITA packet use ethertype field for further parsingEndif;

Forward ethernet payload if :

incoming MAC = dMAC incoming MAC = Broadcast

Append Ethertype field (16-bit) to ethernet payload

if (ethertype == IPv4 & Incoming IP == dIP & UDP = 1000-1004) then forward UDP payload to VITA Receiver

else

forward packet to PCORE

Ethertype = 0x0800 - IPv4 0x0806 - ARP

Use CMD_CNT as ACK to MEM_CTL to indicate completion of PCORE data removal from MEM.

PortID LookupTable

Inbound Packet Processor RMAP

Registers visible to PCORE

For UDP Port 1000 Traffic(VITA)

StreamID lookup(direct-mapped)

APP Identifier

For non-VITA trafficUDP 1001 => P0UDP 1002 => P1UDP 1003 => P2UDP 1004 => P3

Outbound Packet Processing Flow

VRT Receiver

Lookup using PortID

dMAC/Ethertype from IPProcessor

if (IP == 1) then Enable IP processing (append dIP, sIP & UDP) Forward dMAC/Ethertype (Note, sMAC provided in RMAP)

else

Disable IP Processing Forward dMAC/Ethertype (Note, sMAC provided in RMAP)

endif

Lookup using PortID

if (V == 1) then Enable VITA formatting else

Disable VITA formatting endif

dMAC/Ethertype appended to IP/VITA data

Outbound Packet Processor RMAP

Lookup using PID

Data/Context

VITA header

VITA enable flag

StreamID Lookup Table MAC/IP Lookup Table

IP header

Lookup using PID

IP enable flag

CRKIT Register Address Map

Upper 4 MSBs :

0x0-0x1 : PCORE0x2 : CRKITOthers : Unused

0x0 : CMN0x1 : ETH0x2 : PKT0x4-0xB : APP0xC : DAC IF0xD : ADC IF

INTSPI, LEDDCM/CLOCKCE

CRKIT Programming Model

Network

HOST CRKIT

Applicationdevelopment

CRKITdevelopment

Comm.APP

EmbeddedSW

GUI Algorithm

SystemDebugging

SystemTest

HW Configuration

IP NetworkingMathworksSimulink

CR DSAHost

CMD ParsingVHDL/Verilog

DHCP/ARP ETH/VITALookup Tables/

RF

Java, C# C C

APP Development Flow

MATLAB Simulink Flow

Xilinx ISE Flow

CRKITFlow

Lookup TableConfiguration

RF Control

dynamicConfig.

(ETH/VITA)

1. Get IP address using DHCP2. Discover HOST3. Configure CRKIT hardware4. Parse HOST commands

initialconfig.

APP Simulink Development Environment

APP

PCORE DRIVER

BMUDRV

BMUMON

RFLPBK

CMD

.txt file

ETH

.txt files

.txt files

data

RegisterRead/Write

IOValidation

DataVerification

ChannelModel

Send X data packets

I/Q

I/Q

APP Simulink Testbench

CRKIT Example – Rendezvous APPs

CRKIT Example – QPSK Transmitter

CRKIT Example – QPSK Receiver

CRKIT Example – FPGA Utilization

ORBIT Integration

ORBIT SB6Actual SB6 with two CRKITs

OPEN TO ORBIT COMMUNITY !

Conclusion

CRKIT = Advanced Radio System enabling experimental research in CR and DSA techniques

Powerful combination of Wideband Radio and Flexible Baseband Processing

FSoC Static and Dynamic domain spaces

APP development for Creativity and Productivity => MATLAB/Simulink

Framework development for Engineering Complexity => Traditional Hardware design flow

ORBIT Integration => User Friendliness Experience + Experimentation Scalability

Future Work

Extend APP library : OFDM-based waveform APP

Upgrade Static framework to support live loadable APPs from Network :1. Clock Management2. Run-time Reconfiguration

Port Linux to PCORE

Integrate CRKIT fully into ORBIT Management Framework

Upgrade current baseband board to newer and higher performance FPGA technologies