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ARVLSI 99 March 22, 1999Nestoras Tzartzanis

Clock-Powered CMOS: A Hybrid Adiabatic LogicStyle for Energy-Efficient Computing

Nestoras Tzartzanis and Bill Athas

[email protected], [email protected]://www.isi.edu/acmos

Information Sciences Institute

University of Southern California




Outline• The problem

• Standard approaches

• The idea of energy recovery and adiabatic charging• Driver experiment

• Clock-powered logic

• Conclusions




The Problem

• Processors contain some registers, a little bit of logic, and lots of longwires• Problem: driving high-capacitance interconnects in an energy-

efficient way

RF Decoder Address

RF Word Lines

I-Bus / Instruction Register Bus

Control Signals

Din-Bus

Bypass from EXE Stage / A-Bus

Constant Return Address

Indexed Address

.Bypass from MEM Stage / Write Back

High-

Capacitance

Nets

Control

Unit

PC

Unit

RegisterFile

Read

Dec. 1

ReadDec. 0

Write

Dec.

Comp.Unit

ALU

Shifter

....

..

..

Dout-Bus

...

FU Res.

.Source Op.

PC-Bus.

.




A Basic Approach• The basic approach in CMOS:

Use reduced-voltage drivers and low-to-high voltage converters

• Approach is limited by threshold voltages

V ddLV dd

. Din

C

Voltage

Converter

V dd Dout

low-swing signal high-swing signal




Inverters as Low-Swing Drivers

• An inverter is used as a driver

• A dual-rail-input low-to-high voltage converter is used

• HSPICE simulations for HP 0.5 µm, 3.3 V process

..

V ddL

x p x p

V ddL

V ddL..

Din

D Din

150 fF150 fF

xl xl

D

. . Din Dout

8.6 µm

26.8 µm

Driver




Energy vs. Delay for the Inverter

• V dd is set to 3.3 V

• V ddL is varied from 3.3 to 1.1 V

• Record energy for driving the load and delay through the converter

• Voltage reduction is limited by the threshold voltage of the converter

• Delay rapidly increases as V ddL is scaled (3.6 ns for V ddL = 1.1 V)

0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2

10−1

100

Delay (ns)

E n e

r g y

( p J )

3.3 V

1.2 V




Simple Improvement

• A modified inverter is used as a driver

• Reduces delay for low voltages

• Minimum energy dissipation is still limited by the threshold voltageof the converter

0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2

10−1

10

0

Delay (ns)

E n e r g y

( p J )

InverterModified Inv.

3.3 V

1.2 V1.1 V. .. Din Dout

V ddL

8.6 µm

26.8 µm 8.6 µm Din

Modified Inverter




Standard CMOS

Standard CMOS:

• Possible ONLY to reduce voltage

... .

V

C ⇒V

C

R p

Rn

E CV

2

=




Adiabatic Charging

Adiabatic CMOS:

• Reduce dissipation by reducing voltage AND increasing the energytransport time

..~

C

R

T

V

0

~

C

⇒

E 2 RC

T --------CV

2=




An Adiabatic Driver: The Energy-Recovery Latch

• Output node is clock powered

• Energy is injected and recovered through the same path

• Based on bootstrapped clocked buffer [Glasser & Dobberpuhl 1985]

• Minimizes R for given boot-node capacitance• Operates with two non-overlapping clock phases

Adiabatic

path M 2

M 3

thebootnode(bn).

. T

Latch

V iso

DinL

ϕD

C

V out

ϕL

Din

M 1

I 1V ϕ

0

V ϕ

0V out

V bn

ϕDϕL

.




Model for On-Resistance of Bootstrapped Transistor

• Bootstrap nFET on-resistance was analytically modeled for the case

of linear-ramp charging

• Analytical model can be used for sizing bootstrap transistordepending on load capacitance and switching time

1.52

2.53

2

2.5

3

0

500

1000

R e s i s t a n c e ( Ω )

Supply Voltage V dd (V) Clock Voltage Swing V ϕ (V)

Model

HSPICE




Driver Experiment Set-Up

•Purpose: to experimentally determine when increasing the switching

time T is more energy efficient than reducing the clock voltage swing V ϕ

•Voltage converter is inherently a pulse-to-level converter

. . x p∧ϕD x p∧ϕD. .

Din

150 fF150 fF

xl

xl

V ϕ

0ϕD

CB

ϕD

T . .

.

.

.

V iso ϕD

Dout

Din8.6 µm

Dout

V iso

8.6 µm

2.2 µm

2.2 µm

0.7 µm

0.7 µm

ϕD




Energy vs. Delay for all Drivers

• Clock buffer: set V ϕ (3.3-1.1 V) & T (0.001 ns, 0.25 ns, 0.5 ns, 1 ns)

• Conventional drivers: set V ddL (3.3-1.1 V)

• Record energy for driving the load and delay through the converter

• Clock-powered approach has superior scalability because both clock voltage swing V ϕ and switching time T can be varied

0.6 0.8 1 1.2 1.4 1.6 1.8 2 2.2

10−1

100

Delay (ns)

E n e

r g y

( p J )

InverterModified Inv.CB (0.001ns)CB (0.25ns)CB (0.50ns)CB (1.00ns)

previous results V ϕ

0

T




Clock-Powered Logic Design

• General approach:

Use the clock rails to inject and recover the energy

Derive as much operating power as possible from the clock rails

• General guidelines:

Need an efficient clock driver

Innovate in the design of a clock-steering logic

Use conventional precharged, pass-transistor, static logic

Use the clock-steering logic for high-capacitance loads

clock

driver

clock-

steering

logic

clock-

steering

logic

clock-

steering

logic

…

CMOS Chip

dc

logic

…

Clock-Powered Nodes

dc

logic

dc

logic




Clock-Powered Logic for Optimized Energy vs. Delay

• Reduce dissipation where dissipation is a problem

Node-selective energy recovery

Energy is recovered only from high-capacitance nodes

• clock-powered nodes: adiabatically switched

“1”: pulsed to a clock-voltage swing V ϕ

“0”: clamped at 0 V

• dc-powered nodes: conventionally switched

“1”: pulled-up to a voltage V dd from a dc supply

“0”: pulled-down to 0 V




The Energy Optimization Problem for Clock- Powered Logic

• Both clock-powered and dc-powered nodes contribute to energy

dissipation

• The simplest expression that demonstrates the problem:

• C cp » C dc for better energy efficiency

• Asymptotically E dc dominates

E E cp E dc+ RC cp

T -------------C cpV

ϕ

2C dcV dd

2+∼=




Conclusions

• Clocked buffers offer better energy vs. delay scalability than reduced-

voltage drivers

Energy depends on clock voltage swing and transition time

• Clock-powered logic is energy-efficient for implementing large-scale

microsystems when:

the system can be partitioned into C cp and C dc with effectively

C cp » C dc

long transition time of clock-powered nodes can be tolerated

without changing overall system delay

clock powered

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