circuits and elektroniks

8/3/2019 Circuits and Elektroniks

http://slidepdf.com/reader/full/circuits-and-elektroniks 1/414

6.002 CIRCUITS ANDELECTRONICS

Introduction and Lumped Circuit Abstraction

6.002 Fall 2000 Lecture 1 1



ADMINISTRIVIA Lecturer: Prof. Anant Agarwal Textbook: Agarwal and Lang (A&L

Readings are important!

Handout no. 3 Assignments —

Homework exercisesLabs

QuizzesFinal exam




Two homework assignments canbe missed (except HW11).

Collaboration policyHomework

You may collaborate withothers, but do your ownwrite-up.

LabYou may work in a team oftwo, but do you own write-up.

Info handout

Reading for today —Chapter 1 of the book




What is engineering?

Purposeful use of science

What is 6.002 about?Gainful employment ofMaxwell’s equations

From electrons to digital gatesand op-amps




6 .

0 0 2

Simple amplifier abstraction

Instruction set abstraction

Pentium, MIPS

Software systemsOperating systems, Browsers

Filters

Operationalamplifier abstractionabstraction

-+

Digital abstraction

Programming languagesJava, C++, Matlab 6.001

Combinational logic f

Lumped circuit abstraction

R S

+ –

Nature as observed in experiments

…0.40.30.20.1 I

…12963V

Physics laws or “abstractions” Maxwell’s Ohm’s

V = R I

abstraction fortables of data

Clocked digital abstraction

Analog system

components:Modulators,oscillators,RF amps,power supplies 6.061

Mice, toasters, sonar, stereos, doom, space shuttle

6.1706.455

6.004

6.033

M LC V




Lumped Circuit Abstraction

Consider I

The Big Jumpfrom physics

to EECS

+

-

V

? Suppose we wish to answer this question:

What is the current through the bulb?




We could do it the Hard Way…

Apply Maxwell’s

Differential form Integral form

Faraday’s ∇ × E = −∂ B ∫ E ⋅ dl = − ∂φ B ∂t ∂t

Continuity ∇ ⋅ J = − ∂∂

ρ t

∫ J ⋅ dS = − ∂

∂ q

t Others ∇ ⋅ E = ρ ∫ E ⋅ dS = q

ε 0 ε 0




Instead, there is an Easy Way…First, let us build some insight:

Analogy

F a ?

I ask you: What is the acceleration?

You quickly ask me: What is the mass?

I tell you: m F

You respond: a = m

Done!!!




Instead, there is an Easy Way…First, let us build some insight:

F a ?

Analogy

In doing so, you ignored the object’s shape its temperature

its color point of force application

Point-mass discretization




The Easy Way…Consider the filament of the light bulb.

A

B

We do not care about how current flows inside the filament its temperature, shape, orientation, etc.Then, we can replace the bulb with a

discrete resistor for the purpose of calculating the current.

6.002 Fall 2000 Lecture 1 10



The Easy Way…

A

B

Replace the bulb with a

discrete resistor for the purpose of calculating the current.

+

–V A

I

R and I = V

R B

In EE, we do thingsthe easy way…

R represents the only property of interest

Like with point-mass: replace objects F

with their mass m to find a = m

6.002 Fall 2000 Lecture 1 11



The Easy Way…

+

–V

A I R and I = V

R B

In EE, we do thingsthe easy way…

R represents the only property of interest

R relates element v and iV

I = R

called element v-i relationship

6.002 Fall 2000 Lecture 1 12



R is a lumped element abstraction

for the bulb.

6.002 Fall 2000 Lecture 1 13



R is a lumped element abstractionfor the bulb.

Not so fast, though …

A

B

S B S

I

+

–

V black box

Although we will take the easy wayusing lumped abstractions for the restof this course, we must make sure (atleast the first time) that ourabstraction is reasonable. In this case,ensuring that V I

are definedfor the element

6.002 Fall 2000 Lecture 1 14



AV I must be defined

B

A S B S

I

+

–

V for the element

black box

6.002 Fall 2000 Lecture 1 15



l

I must be defined. True when

I into S A = I out of S B True only when ∂q

= 0 in the filament!∂t

∫ J ⋅ dS S A

∫ J ⋅ dS S B

∫ J ⋅ dS − ∫ J ⋅ dS = ∂q S A S B ∂t

I A I B

I A = I B only if 0 = ∂ ∂

t q

So let’s assume this

6.002 Fall 2000 Lecture 1 16

f r o m

M a x w e

l



V Must also be defined. s e e

A & L

So let’s assume this too

V AB So V AB = ∫ AB E ⋅ dl

defined when 0= ∂

∂

t B φ

outside elements

6.002 Fall 2000 Lecture 1 17



Lumped Matter Discipline (LMD)

0= ∂ ∂

t Bφ

outside

0= ∂ ∂

t q

inside elementsbulb, wire, battery

Or self imposed constraints:

More inChapter 1of A & L

Lumped circuit abstraction applies whenelements adhere to the lumped matterdiscipline.

6.002 Fall 2000 Lecture 1 18



Demo Lumped element exampleswhosecaptured by their V – I

relationship.

only for thesorts ofquestions we

as EEs wouldlike to ask!

is completelybehavior

Demo Exploding resistor demo

can’t predict that!Pickle demo

can’t predict light, smell

6.002 Fall 2000 Lecture 1 19



So, what does this buy us?Replace the differential equationswith simple algebra using lumped

circuit abstraction (LCA).

For example —a

+ –

1

2

3b d

R4

V R

5

cWhat can we say about voltages in a loopunder the lumped matter discipline?

6.002 Fall 2000 Lecture 1 20



What can we say about voltages in a loopunder LMD?

+ –

1

2

3

a

b d R

4V

R5

c

∫ E ⋅ dl = t B

∂∂− φ under DMD

0 ∫ E ⋅ dl + ∫ E ⋅ dl + ∫ E ⋅ dl = 0

ca ab bc + V ca + V ab + V bc = 0

Kirchhoff’s Voltage Law (KVL):

The sum of the voltages in a loop is 0.

6.002 Fall 2000 Lecture 1 21



What can we say about currents?Consider

S I ca I da

ba I a

6.002 Fall 2000 Lecture 1 22



What can we say about currents?ca da

ba I

a I S

I

S J ⋅ dS =

t q

∂

∂− under LMD

0 ∫ I ca +

I da + I ba = 0

Kirchhoff’s Current Law (KCL):

The sum of the currents into a node is 0.

simply conservation of charge

6.002 Fall 2000 Lecture 1 23



KVL and KCL SummaryKVL: ∑ jν j = 0

loop

KCL:

∑ j i j = 0 node

6.002 Fall 2000 Lecture 1 24



6.002 Fall 2000 Lecture 12

6.002 CIRCUITS AND

ELECTRONICS

Basic Circuit Analysis Method(KVL and KCL method)




0=∂

∂

t

Bφ

0=∂

∂

t

q

Outside elements

Inside elements

Allows us to create the lumped circuitabstraction

wires resistors sources

Review

Lumped Matter Discipline LMD:Constraints we impose on ourselves to simplifyour analysis




LMD allows us to create thelumped circuit abstraction

Lumped circuit element+

-

v

i

power consumed by element = vi

Review




KVL:

loop

KCL:

node

0=∑ j jν

0=∑ j ji

ReviewReview

Maxwell’s equations simplify toalgebraic KVL and KCL under LMD!




KVL0=++ bcabca vvv

0=++ badaca iii KCLDEMO

1

2

4

5

3

a

b

d

c

+

–

Review




Method 1: Basic KVL, KCL method ofCircuit analysis

Goal: Find all element v’s and i’s

write element v-i relationships(from lumped circuit abstraction)

write KCL for all nodeswrite KVL for all loops

1.

2.3.

lots of unknownslots of equationslots of funsolve




Method 1: Basic KVL, KCL method ofCircuit analysis

For R,

For voltage source,

For current source,

Element Relationships

IRV =

0V V =

0 I =

3 lumped circuit elements

0V

o I

+ –




KVL, KCL Example

The Demo Circuit

+ –

1

2

4

5

3

a

b d

c

00 V =ν +

–

1ν +–

5ν

+

–

3ν + –

2ν +

–

4ν +–




Associated variables discipline

ν

i +

-

Element e

Then power consumed

by element e

iν = is positive

Current is taken to be positive goinginto the positive voltage terminal




KVL, KCL Example

The Demo Circuit

+ –

1

2

4

5

3

a

b d

c

00 V =ν +

–

1ν +–

5ν

+

–

3ν + –

1 L

2 L

4 L

3 L2ν

+

–

4ν +–

2i

1i

0i

5i

3i

4i




Analyze12 unknowns

5050 , ι ι ν ν ……

1. Element relationships

3. KVL for loops

00 V v =111 iv =

222 iv =

333 iv =444 iv =

555 iv =

given

2. KCL at the nodes

redundant

0431 =−+ vvv

0210 =++− vvv

0253 =−+ vvv0540 =++− vvv redundant

0410 =++ iii0132 =−+ iii0435 =−− iii0520 =−−− iii

a:b:

d:

e:

6 equations

3 independentequations

3 independentequations

1 2 u n k n o w n

s

1 2 e q u a

t i o n s

u g h @ # !

( )iv,

L1:

L2:

L3:

L4:




Other Analysis MethodsMethod 2— Apply element combination rules

B

C

D

⇔+++ 21

⇔1G 2G N G GGG ++21

i

i R

G1

=

⇔+ – + – + –

1V 2V 21 V V +

⇔

1 2 21 +

A1 2 3 N

…

Surprisingly, these rules (along with superposition, which you will learn about later) can solve the circuit on page 8




Other Analysis MethodsMethod 2— Apply element combination rules

V

32

32

R R +

V

32

32

1 R R R R

++=

+ –

V

?=

1

32

+ –

+ –

Example

1

R

V I =




1.

2.

3.

4.

5.

Select reference node ( ground)from which voltages are measured.

Label voltages of remaining nodeswith respect to ground.These are the primary unknowns.

Write KCL for all but the ground

node, substituting device laws andKVL.

Solve for node voltages.

Back solve for branch voltages andcurrents (i.e., the secondary unknowns)

Particular application of KVL, KCL method

Method 3—Node analysis




Example: Old Faithfulplus current source

0V

1

2

4

5

3

1 I

0V

+ – 1e

2e

Step 1Step 2





0)()()( 21321101 =+−+− GeGeeGV eKCL at 1e

0)()()( 152402312=−+−+−I GeGV eGee

KCL at 2e

for

conveniencewrite

i

i R

G1

=

0V

1

2

4

5

3

1e

1

0V

+ –

2e

Step 3





0)()()( 21321101 =+−+− GeGeeGV e

KCL at 1e

0)()()( 152402312 =−+−+− I GeGV eGeeKCL at 2l

move constant terms to RHS & collect unknowns

)()()( 10323211 GV GeGGGe =−+++

140543231 )()()( GV GGGeGe +=+++−

i

i R

G 1=

2 equations, 2 unknowns Solve for e’s(compare units)

0V

1

2

4

5

3

1e

1

0V

+ –

2e

Step 4




In matrix form:

+=

++−

−++

104

01

2

1

5433

3321

I V G

V G

e

e

GGGG

GGGG

conductivitymatrix

unknownnode

voltages

sources

( )( ) 2

3543321

104

01

3213

3543

2

1

GGGGGGG

I V G

V G

GGGG

GGGG

e

e

−++++

+

++

++

=

Solve

5G3G4G3G2

3G5G2G4G2G3G2G5G1G4G1G3G1G

1 I 0V 4G3G

0V 1G5G4G3G

1e

++++++++

++++=

( )( ) ( )( )

5343

2

3524232514131

1043210132

GGGGGGGGGGGGGGGGG

I V GGGGV GGe

++++++++

++++=

(same denominator)

Notice: linear in , , no negativesin denominator

0V 1




Solve, given

K 2.8

1

G

G

5

1

=

K 9.3

1

G

G

4

2

=

K 5.1

1G3 =

01 = I

( ) ( ) 23G5G4G3G3G2G1G

1

I

0

V

4

G

3

G

2

G

1

G

0

V

1

G

3

G

2e −+++++

++++

=

15.1

1

9.3

1

2.8

1

3G2G1G =++=++

12.81

9.31

5.11GGG 543 =++=++

0

2

2 V

5.1

11

9.3

115.1

1

2.8

1

e

−

×+×=

02 6.0 V e =

If , thenV V 30 = 02 8.1 V e =

Check out the

DEMO




6.002 CIRCUITS AND

ELECTRONICS

Superposition, Thévenin and Norton




0=∑loop

iV

Review

Circuit Analysis Methods

Circuit composition rules

Node method – the workhorse of 6.002KCL at nodes using V ’s referencedfrom ground(KVL implicit in “ ”) ji ee − G

KVL: KCL:

0=∑node

i

VI




Consider

Linearity

Write node equations –

V I

1

2+ –

021

=−+−

I R

e

R

V e

Notice:linear in V e ,,

VI ,eV No

terms

e




Consider

Linearity

Write node equations --

Rearrange --

V I

1

2+ –

021

=−+−

I R

e

R

V e

I R

V e R R +=

+121

11

e S =

conductance

matrix

node

voltages

linear sum

of sources

linear in IV e ,,




Linearity

or I R RV R Re21

21

21

2

+++=

…… +++++= 22112211 bbV aV ae

Write node equations --

Rearrange --

021

=−+−

I R

e

R

V e

I RV e

R R+=

+

121

11

e S =

conductancematrix nodevoltages linear sumof sources

linear in IV e ,,

Linear!




LinearityHomogeneitySuperposition⇒




LinearityHomogeneitySuperposition

Homogeneity

1 x2

x y...

1 xα 2 xα yα ...

⇓

⇒





Superposition

a x1

a x2 a y... ...b x1

b x2 b y

⇒

ba x x 11+

ba x x22

+ba y y +

⇓

...





Specific superposition example:

1V 0 1 y 02

V 2 y

01

+V

20 V + 21 y +

⇓

⇒




Method 4: Superposition method

The output of a circuit is

determined by summing theresponses to each sourceacting alone.

i n d e p e n d e n

t s o u rc e s

o n l y




i

+ –0=V

+

-

v

i

short

+

-

v

i

0= I

+

-

v

i

open

+

-

v




Back to the exampleUse superposition method

V

1

2+ –

e




Back to the exampleUse superposition method

V

acting alone

V 0= I

2+ –

e

1

I acting alone

0=V

1

2

e

V R R

eV 21

2

+=

I R R

e I 21

21

+=

I R R

V R R

eee I V

21

21

21

2

++

+=+=

sum superposition

Voilà !




saltwater

output showssuperposition

Demo

constant

+ –

sinusoid

+ –

?




Consider Yet another method…

resistors

nounits

By setting

0

,0

=

=∀

i

nn

0

,0

=

=∀

i

V mm

All

0

,0=∀=∀

mm

nn

V

+ –

mV n

A r b i t r a r

y n e t w o r k N

By superpositioni I V v n

nnm

mm ++= ∑∑ β α

+

-v

i

i

resistanceunits

independent of externalexcitation and behaves like avoltage “ ”TH v

alsoindependentof externalexcitement &behaves likea resistor




Orivv TH TH +=

As far as the external world is concerned(for the purpose of I-V relation),

“Arbitrary network N” is indistinguishable

from:

i + –

TH

TH v

+

-

vThéveninequivalentnetwork

TH

TH v open circuit voltageat terminal pair (a.k.a. port)

resistance of network seenfrom port( ’s, ’s set to 0)

mV n

N




Method 4:

The Thévenin Method

Replace network N with its Thévenin

equivalent, then solve external network E.

E

Thévenin equivalent

+ –

TH

TH v

+

-

v

i

E

+ –

+ –

i

+

-v

N




Example:1

V +

–

1i

1

V

+

–

1i

TH

TH

R RV V i

+−=

1

1

2

TH

TH V + –




Example:

:TH

:TH V

2 IRV TH =

2TH =

+

-TH V 2

+

-TH 2




Graphically, ivv TH TH +=

i

Open circuit( )0≡i

TH vv = OC V

Short circuit( )0≡v TH

TH

R

vi

−=

SC I −

v

TH R

1

TH v

SC I −

OC V “ ”




Method 5:

The Norton Method

in recitation,see text

+ –

+ –

i

+

-v

Nortonequivalent

TH

TH N

R

V I =

N TH = N




Summary

… 101100 …

Discretize matterLMD LCA

Physics EE

R, I, V Linear networks

Analysis methods (linear)KVL, KCL, I — VCombination rulesNode methodSuperpositionThéveninNorton

NextNonlinear analysis

Discretize voltage




6.002 CIRCUITS AND

ELECTRONICS

The Digital Abstraction




Review

Discretize matter by agreeing toobserve the lumped matter discipline

Analysis tool kit: KVL/KCL, node method,superposition, Thévenin, Norton

(remember superposition, Thévenin,Norton apply only for linear circuits)

Lumped Circuit Abstraction




Discretize value Digital abstraction

Interestingly, we will see shortly that thetools learned in the previous threelectures are sufficient to analyze simpledigital circuits

Reading: Chapter 5 of Agarwal & Lang

Today




Analog signal processing

But first, why digital?In the past …

By superposition,

The above is an “adder” circuit.

2

21

11

21

20

V R R

V R R

V +

+

+

=

If ,21

R R =

2

21

0

V V V

+=

1V

1

2+ –

2V +

–

0V

and

might represent the

outputs of two

sensors, for example.

1V 2V




Noise Problem

… noise hampers our ability to distinguish

between small differences in value —e.g. between 3.1V and 3.2V.

Receiver:

huh?

add noise onthis wire

t




Value Discretization

Why is this discretization useful?

Restrict values to be one of two

HIGH

5V

TRUE

1

LOW

0V

FALSE

0

…like two digits 0 and 1

(Remember, numbers larger than 1 can berepresented using multiple binary digits andcoding, much like using multiple decimal digits torepresent numbers greater than 9. E.g., thebinary number 101 has decimal value 5.)




Digital System

sender receiverS

V RV

noise

S V

“0” “0”“1”

0V

2.5V

5V HIGH

LOW

t

RV

“0” “0”“1”

0V

2.5V

5V

t

V V N

0=

N V

S V

“0” “0”“1”

2.5V t

With noiseV V

N 2.0=

S V

“0” “0”“1”

0V

2.5V

5V

t

0.2V

t




Digital System

Better noise immunityLots of “noise margin”

For “1”: noise margin 5V to 2.5V = 2.5V For “0”: noise margin 0V to 2.5V = 2.5V




Voltage Thresholdsand Logic Values

1

0

1

0

sender receiver

1

0

0V

2.5V

5V




forbidden

region

VH

V L

3V

2V

But, but, but …What about 2.5V?

Hmmm… create “no man’s land”or forbidden region

For example,

senderreceiver

0V

5V

1 1

0 0

“1” V 5V

“0” 0V V

H

L




sender receiver

But, but, but …Where’s the noise margin?

What if the sender sent 1: ?VHHold the sender to tougher standards!

5V

0V

11

00

V

0H

V0L

VIH

VIL




sender receiver

VH

But, but, but …Where’s the noise margin?

What if the sender sent 1: ?Hold the sender to tougher standards!

5V

0V

“1” noise margin:

“0” noise margin:

VIH

- V0H

VIL

- V0L

11

00

V

0H

V0L

VIH

VIL

Noise margins




Digital systems follow static discipline: ifinputs to the digital system meet valid inputthresholds, then the system guarantees itsoutputs will meet valid output thresholds.

sender

receiver

0 1 0 1

t

5VV

0H

V0L

0V

VIH

VIL

0 1 0 1

t

5VV

0H

V0L

0V

VIH

VIL




Processing digital signals

Recall, we have only two values —

Map naturally to logic: T, F

Can also represent numbers

1,0




Processing digital signalsBoolean Logic

If X is true and Y is trueThen Z is true else Z is false.

Z = X AND YX, Y, Z

are digital signals“0” , “1”

Z = X • YBoolean equation

Enumerate all input combinations

Truth table representation:

ZX Y

AND gateZX

Y

0 0 0

0 1 01 0 0

1 1 1




Adheres to static discipline Outputs are a function of

inputs alone.

Combinational gateabstraction

Digital logic designers do not

have to care about what is

inside a gate.




Demo

Noise

ZXY

Z = X • Y

Z

Y

X




Z = X • Y

Examples for recitation

X

t

Y

t

Z

t




In recitation…

Another example of a gateIf (A is true) OR (B is true)

then C is true

else C is false

C = A + B Boolean equation

OR

OR gate

CA

B

ZX

Y NAND

Z = X • Y

More gates

B B

Inverter




Boolean Identities

AB + AC = A • (B + C)

X • 1 = X

X • 0 = XX + 1 = 1X + 0 = X

1 = 0

0 = 1

output

BC B • C

A

Digital Circuits

Implement: output = A + B • C




6.002 CIRCUITS AND

ELECTRONICS

Inside the Digital Gate




Review

Discretize value 0, 1

Static disciplinemeet voltage thresholds

Specifies how gates must be designed

sender receiver

forbiddenregion

OLV

OH V

LV

IH V

The Digital Abstraction




Review

C A B

0 0 10 1 11 0 11 1 0

A

BC

NAND

Combinational gate abstractionoutputs function of input alonesatisfies static discipline




For example:a digital circuit

Demo

D

A

B

C

A Pentium III class microprocessoris a circuit with over 4 million gates !!

The RAW chipbeing built at theLab for Computer Science at MIT has about 3 million gates.

3 gates here

( )( ) B AC D ⋅⋅=

B A ⋅




How to build a digital gate

Analogy

A B

C

l i ke po wer

s u p p l y

( l i ke s w i tc he

s )

taps

if A=ON AND B=ON

C has H 0

else C has no H 0

2

2

Use this insight to build an AND gate.




How to build a digital gate

C

B

A

OR gate




Electrical Analogy

+ –

Bulb C is ON if A AND B are ON,else C is off

Key: “switch” device

V

BC




Electrical Analogy

Key: “switch” device

C

in

out

control

3-Terminal deviceif C = 0

short circuit between in and outelse

open circuit between in and out

For mechanical switch,control mechanical pressure

in

out

1=C

equivalent ck

0=C

in

out




Consider

=S

V “1”

+ – S

V

L

C

IN

OUT

OUT V

S V

0=C

OUT V

S V

1=C

OUT V

S V

L R

C

OUT V

Truth table for

C

0 1

1 0

OUT V




What about?Truth table for

OV 2

c

0 0 10 1 11 0 1

1 1 0

1c

Truth table for

OV 2

c

0 0 1

0 1 01 0 01 1 0

1c

S V

OUT V

1c

2c

S V

OUT V

1c

2c




What about?

can also build compound gates

S V

D

B

C ( ) C B A D +⋅=




The MOSFET Device

3 terminal lumped elementbehaves like a switch

Metal-OxideSemiconductorField-EffectTransistor

: control terminal: behave in a symmetricmanner (for our needs)

G

S D,

gate≡

source

D

S

G

drain




The MOSFET Device

Understand its operation by viewing it

as a two-port element —

“Switch” model (S model) of the MOSFET

D

S

Gi

G

GS v+

–

DS v

DS i +

–

Ch ec k o u t

th e t e x t b

o o k

f o r i t s i n

t e r n a l

s t r uc t u r

e.

T GS V v <

T GS V v ≥

V V T 1≈ typically

onG

D

S

DS i

G off

D

S




Check the MOS deviceon a scope.

Demo

GS v+

–

DS v

DS i

+

–

T GS V v ≥

DS i

DS v

T GS V v <

DS i

DS vvs




A MOSFET Inverter

S V

L

IN

B

B

V 5=

Note the power of abstraction.

The abstract inverter gate representationhides the internal details such as powersupply connections, , , etc.

(When we build digital circuits, theand are common across all gates!)

LGND

vOUT




The T1000 model laptop desires gates that satisfythe static discipline with voltage thresholds. Doesout inverter qualify?

IN v

OUT v

OUT v

IN v

5V

5V

0V=1VT

V

= 0.5VOL

V

= 4.5VOH

V

= 0.9V IL

V

= 4.1V IH

V

Our inverter satisfies this.

receiver

OLV

OH V

LV

IH V

54.5

0.5

0

sender

5

4.1

0.9

0

1:

0:

1

0

Example




E.g.:

Does our inverter satisfy the staticdiscipline for these thresholds:

= 0.2VOL

V

= 4.8VOH V

= 0.5V IL

V

= 4.5V IH V

= 0.5VOLV

= 4.5VOH

V

= 1.5V L

V

= 3.5V H

V

yes

no

x




Switch resistor (SR) modelof MOSFET

…more accurate MOS model

D

S

G

D

S T GS

V v <

G

T GS V v ≥

ON

D

S

G

e.g. Ω= K ON

5




SR Model of MOSFET

MOSFET S model

T GS V v ≥

T GS V v <

DS i

DS v

MOSFET SR model

T GS V v ≥

T GS V v <

DS i

DS v

ON R

1

D

S

G

D

S T GS

V v <

G

T GS V v ≥

ON

D

S

G




Using the SR model

=S

V “1”

+ – S

V

L

C

IN

OUT

OUT v

S V

0=C

OUT v

S V

1=C

OUT v

S V

L R

C

OUT v

Truth table for

C

0 11 0

OUT

V

T GS V v ≥

ON

ON OLV

L R

ON R

ON R

S V

OUT v ≤

+=

L

L Choose RL, RON, VS such that:




6.002 CIRCUITS AND

ELECTRONICS

Nonlinear Analysis




Discretize matter LCA

m1 KVL, KCL, i-v

m2 Composition rules

m3

Node methodm4 Superposition

m5 Thévenin, Norton

anycircuit

linearcircuits

Review




Discretize value

Digital abstraction Subcircuits for given “switch”

setting are linear! So, all 5methods (m1 – m5) can be

applied

1

1

=

=

B

B

S V

L

C

S V

L

C

ON ON

SR MOSFET Model

Review




Today

Nonlinear Analysis

Analytical methodbased on m1, m2, m3

Graphical method

Introduction to incremental analysis




How do we analyze nonlinearcircuits, for example:

Dv+ -

D

Di

Dv

Di

0,0

Dbv

D aei =

a

Dv+

-V +

–

Hypotheticanonlineardevice D

Di

(Expo Dweeb )

(Curiously, the device supplies power whenv D is negative)




Method 1: Analytical Method

Using the node method,(remember the node method applies for linear ornonlinear circuits)

Dbv

D aei = 2

0=+−

D D i

V v1

2 unknowns 2 equations

Solve the equation by trial and error numerical methods




Method 2: Graphical Method

Notice: the solution satisfies equations

and 21

Dv

Di

a

Dbv D aei =2

Dv

Di 1vV

i D D −=

V

V

slope1

−=




Combine the two constraints

1

4

1

1

1

=

=

=

=

b

a

R

V e.g.

Ai

V v

D

D

4.0

5.0

=

=

Dv

Di

5.0~

4.0~

V

V 1

1

a¼

called “loadline”for reasons youwill see later




Method 3: Incremental AnalysisMotivation: music over a light beam

Can we pull this off?

LED: LightEmittingexpoDweep

Dv+

-

)(t v + –

Di

LED

i

AMP

light intensity I Rin photoreceiver

Ri ∝

lightintensity

D D i I ∝

I v

t

music signal

)(t v I light sound)(t i R)(t i D

nonlinearlinear

problem! will result in distortion




Problem:The LED is nonlinear distortion

D vv=

Dv

Di

vD

t

t

Di v D

Di

t




If only it were linear …

vD

t

Di

Dv

Di

it would’ve been ok.What do we do?

Zen is the answer

… next lecture!




6.002 CIRCUITS AND

ELECTRONICS

Incremental Analysis




Nonlinear Analysis

Analytical method

Graphical method

Today

Incremental analysis

Reading: Section 4.5

Review




Method 3: Incremental AnalysisMotivation: music over a light beam

Can we pull this off?

LED: LightEmittingexpoDweep

Dv+

-

)(t v + –

Di

LED

i

AMP

light intensity I Rin photoreceiver

Ri ∝

lightintensity

D D i I ∝

I v

t

music signal

)(t v I light sound)(t i R)(t i D

nonlinearlinear

problem! will result in distortion




Problem:The LED is nonlinear distortion

D vv=

Dv

Di

vD

t

t

Di v D

Di

t




Insight:

D

v

Di

D I

DV

DC offsetor DC bias

Trick:

d D D ii +=

I V

Dv+

-

)(t vi+ –

LED+ –

v

d D D vV v +=

I V iv

small regionlooks linear(about V D , I D)




Result

v d very small

Di

Dv

d i

D

DV




Result

t

Dv DV

I D vv =

t

D

Di

~linear!

Demo

d v

d i Di




total

variable

DC

offset

small

superimposedsignal

The incremental method:(or small signal method)

1. Operate at some DC offsetor bias point V D, I D .

2. Superimpose small signal vd

(music) on top of V D .

3. Response id to small signal vd

is approximately linear.

Notation:

d D D i I i +=




( ) D D v f i =

What does this meanmathematically?

Or, why is the small signal responselinear?

We replaced

D D D vV v ∆+=

using Taylor’s Expansion to expand

f(v D ) near v D=V D :( ) D

V v D

D D D v

dv

vdf V f i

D D

∆⋅+=

=

)(

+∆⋅+

=

2

2

2 )(

!2

1 D

V v D

D

vdv

v f d

D D

large DC

incrementabout V D

nonlinear

d v

neglect higher order terms

because is small Dv∆




( ) D

V v D

D D D v

vd

v f d V f i

D D

∆⋅+≈

=

)(

equating DC and time-varying parts,

D

V v D

D D v

vd

v f d i

D D

∆⋅=∆

=

)(

constantw.r.t. ∆v D

constant w.r.t. ∆v D

slope at V D, I D

( ) D D V f = operating point

constant w.r.t. ∆v D

X :We can write

( ) D

V v D

D D D D v

vd

v f d V f i I

D D

∆⋅+≈∆+

=

)(

so, D D vi ∆∝∆ By notation,

d D ii =∆

d D vv =∆




Equate DC and incremental terms,

Dbv

D eai =

From X :

constant

In our example,

d

bV bV

d D vbeaeai I D D⋅⋅+≈+

DbV

D ea I =

d

bV

d vbeai D ⋅⋅=

operating point

d Dd vbi⋅⋅=

small signalbehaviorlinear!

aka bias pt.aka DC offset




DbV

D ea I = operating point

d Dd vb I i ⋅⋅=

Dv

Di

D I

DV

slope at

V D, I D

operating

point

we areapproximatingA with B

A

B

d v

d i

Graphical interpretation




We saw the small signal

D I

I V DV +

-

+ – LED DbV

D ea I =

Large signal circuit:

Small signal response: d Dd vbi =

graphically

mathematically

now, circuit

small signal circuit:

Linear!

d i

iv d v+

- b I D

1+ –

behaves like:d v+ -

d i

b I

1 R

D

=


http://slidepdf.com/reader/full/circuits-and-elektroniks 130/4146.002 – Fall 2002: Lecture 8 1

6.002 CIRCUITS AND

ELECTRONICS

Dependent Sources

and Amplifiers



Nonlinear circuits — can use thenode method

Small signal trick resulted in linearresponse

Today

Dependent sources

Reading: Chapter 7.1, 7.2

Review

Amplifiers



Dependent sources

+ –v

ivi =Resistor

2-terminal 1-port devices

+ –v

ii = I

IndependentCurrent source

Seen previously

controlport

outputport

i

I v

Oi

Ov

+

–

+

–

New type of device: Dependent source

2-port device

E.g., Voltage Controlled Current SourceCurrent at output port is a function of voltage

at the input port

)v( f I



Dependent Sources: Examples

independentcurrentsource

Example 1: Find V

0=

+

–V

V 0

=



voltagecontroledcurrent

source

Example 2: Find V

( ) V

K V f I ==

+

–V

i

I v

Oi

Ov

+

–

+

–

+

–V

( ) I

I v

K v f =




voltagecontroledcurrentsource

RV

K IRV ==

KRV =2

KRV =33

1010 ⋅=

−

Volt 1=

oror

Example 2: Find V

( ) V

K V f I ==

+

–V

e.g. K = 10-3 Amp·Volt

R = 1k Ω




Another dependent source example

v + –

( ) IN D v f i =

L

+ –S V

e.g. ( ) N D v f i =

( )2

IN 1v2

K −= for v IN ≥ 1

IN i

IN v

Di

Ov

+

–

+

–

otherwise0i D =

Find vO as a function of v I .




v + –

( ) IN D v f i =

L

S V

e.g. ( ) N D v f i =

( )2

IN 1v2

K −= for v IN ≥ 1

IN i

IN v

Di

Ov

+

–

+

–

otherwise0i D =






I v + –

I v

S V

Ov

L

( )2

IN D 1v2

K i −= for v IN ≥ 1

otherwise0i D =




0=++− O L DS viV

KVL

L DS O iV v −=

( ) L I S O Rv K

V v2

12

−−= for v I ≥ 1

S O V v = for v I < 1

I v + –

I v

S V

Ov

L

( )2

IN D 1v2


otherwise0i D =

Hold that thought



Next, Amplifiers



Why amplify?Signal amplification key to both analogand digital processing.

Analog:

Besides the obvious advantages of being

heard farther away, amplification is keyto noise tolerance during communication

AMP IN OUT

InputPort

OutputPort



Why amplify?

Amplification is key to noise toleranceduring communication

usefulsignal

huh?

1 mV n o i

s e10 mV

No amplification



AMP

Try amplification

not bad!

n o i s e



Why amplify?Digital:

IN OUT

Digital System

LV IH V

5V

0V OLV

OH V 5V

0V

t

5V

0V

ILV

IH V

IN OUT

t

5V

0V OL

V

OH V

Valid region



Why amplify?Digital:

Static discipline requires amplification!

Minimum amplification needed:

ILV IH V

OLV

OH V

L H

OLOH

V V

V V

−

−



An amplifier is a 3-ported device, actually

We often don’t show the power port.

Also, for convenience we commonly observe“the common ground discipline.”

In other words, all ports often share acommon reference point called “ground.”

How do we build one?

POWER

IN OUT

Amplifier

Power port

Inputport

Outputport

i

I v

Oi

Ov+

–

+

–



Remember?

0=++− O L DS viV

KVL

L DS O iV v −=

( ) L I S O Rv K

V v2

12

−−= for v I ≥ 1

S O V v = for v I < 1

Claim: This is an amplifier

I v + –

I v

S V

Ov

L

( )2

IN D 1v2


otherwise0i D =



So, where’s the amplification?

Let’s look at the vO versus v I curve.

amplification1>∆

∆ O

v

v

Ω===

k 5 R ,V

mA

2 K ,V 10V L2S e.g.

Ov∆

I v∆

( )2

12

−−= I LS O v R K

V v

( )2

1510 −−=O vv

( )233110510

2

210 −⋅⋅⋅−=

−

I v

1I v

S V

Ov



Plot vO versus v I

( )

2

O 1v510v−−=

10.001.0

~ 0.002.4

1.502.3

2.802.2

4.002.1

5.002.0

8.751.5

10.000.0

vOv I

0.1 changein v I

1V changein vO

Gain!

Measure vO .Demo



One nit …

1

v

Ov

Mathematically,

( )2

12

−−= I LS O v R K V v

Whathappenshere?

So is mathematically predicted behavior



One nit …

Di

S V

Ov L

VCCS

1

v

Ov

For vO>0, VCCS consumes power: vO i DFor vO<0, VCCS must supply power!

( )2

12


V v

( )2

12

−= I D v K

i for v I ≥ 1

However, from

Whathappenshere?



If VCCS is a device that can sourcepower, then the mathematicallypredicted behavior will be observed —

( )2

12


V vi.e.

where vO goes -ve

I v

Ov



If VCCS is a passive device,then it cannot source power,so vO cannot go -ve.So, something must give!

Turns out, our model breaks down.

( )2

12

−= I D v K

iCommonly

will no longer be valid when vO ≤ 0 .

e.g. i D saturates (stops increasing)

and we observe:

I v

Ov

1




6.002 CIRCUITS AND

ELECTRONICS

MOSFET Amplifier

Large Signal Analysis




Amp constructed using dependent source

Superposition with dependent sources:one way leave all dependent sources in;solve for one independent source at a

time [section 3.5.1 of the text] Next, quick review of amp …

Reading: Chapter 7.3–7.7

+ –+

–a′

a

v

b′

b

)(vi =

a′a

b′bcontrol

port DS outputport

Dependent source in a circuit

Review




Amp review

L DS O iV v −=

( )2

I 1v2

K −

forv I

≥ 1V

= 0 otherwise

S V

Ov

L

+ –

( )2

I D 1v2

K i −=

v

VCCS




Key device Needed:

Let’s look at our old friend, the MOSFET …

A

Bv

C

( )v f i =voltage controlled

current source




Key device Needed:

Our old friend, the MOSFET …

First, we sort of lied. The on-state behavior of theMOSFET is quite a bit more complex than either theideal switch or the resistor model would have you believe.

D

S

G

D

S

T GS V v <

G

T GS V v ≥?




Graphically

DS v

DS i

T GS V v ≥

T GS V v <

T GS

V v ≥

1GS v

Saturationregion

T r i o

d e

r e g

i o n

S MODEL

DS v

DS i

SR MODEL

Dv

DS i

Demo

T GS V v <

T GS V v <

2GS v

3GS v

+ – DS v

+

–

DS iGS v

.

.

.

GS DS Vvv −=

Cutoff

region




Graphically

DS v

DS i

T GS V v ≥

T GS V v <

T GS

V v ≥

1GS v

Saturationregion

T r i o

d e

r e g

i o n

S MODEL

DS v

DS i

SR MODEL

DSv

DS i

T GS V v <

T GS V v <

2GS v

3GS v

+ – DS v

+

–

DS iGS v

.

.

.

TGS DS V vv −=

Notice thatMOSFET behaves like a

current source

whenT GS DS V vv −≥




MOSFET SCS Model

D

S

G

D

S

T GS V v <

G

( )2

2T GS V v

K −=

whenT GS DS V vv −≥

( )GS DS v f i =

T GS V v ≥

D

S

G

When

the MOSFET is in its saturation region, and theswitch current source (SCS) model of the MOSFET ismore accurate than the S or SR model

T GS DS V vv −≥




Reconciling the models…

T GS DS V vv −≥

T GS DS V vv −<use SCS modeluse SR model

Note: alternatively (in more advanced courses)

or, use SU Model (Section 7.8 of A&L)

S MODEL SR MODEL SCS MODELfor fun!

for digitaldesigns

for analogdesigns

When to use each model in 6.002?

DS v

DS i

T GS V v ≥

T GS V v <

T GS V v ≥

1GS v

Saturationregion

T r i o

d e

r e g

i o n

DS v

DS i

Dv

DS i

T GS V v <

T GS V v <

2GS v

3GS v .

.

.

GS DS

Vvv −=




Back to Amplifier

in saturationregion

I

vO

vMP

S V

S V

L

I v

Ov

G D

S

( )2

2T I DS V v

K i −=

To ensure the MOSFET operates as a VCCS,

we must operate it in its saturation regiononly. To do so, we promise to adhere to the

“saturation discipline”




MOSFET Amplifier

in saturationregion

S V

L

I v

Ov

G D

S ( )2

2T I DS V v

K i −=

To ensure the MOSFET operates as a VCCS,

we must operate it in its saturation regiononly. We promise to adhere to the“saturation discipline.”

In other words, we will operate the amp

circuit such that

vGS

≥ V T

and v DS

≥ vGS

– V T

at all times.vO≥ v

I – v

T




Let’s analyze the circuitFirst, replace the MOSFET with its

SCS model.

forT I O V vv −≥GS vv =

G

I v+

–

+ –

S V

Ov

L

D

S

A( )2

2T I DS V v

K i −=




Let’s analyze the circuit

forT I O V vv −≥GS vv =

G

I v+

–

+ –

S V

Ov

L

D

S

A( )2

2

T I DS V v K

i −=

or ( ) LT I S O RV v K

V v2

2−−= for

T I V v ≥

T O V vv −≥

S O V v = for T V v <

(MOSFET turns off)

L DS S O iV v −= B1 Analytical method: I O vvsv

(vO = v DS DS in our examplein our example ) )




2 Graphical method

:B

From A ( ) ,

2

2

T I DS V v K

i −=:

2

O DS

DS O

T I O

v2

K i

K

i2v

V vv

≤

⇓

≥

⇓

−≥for

I O vvsv

L

0

L

S DS

R

v

R

V i −=




2 Graphical method

:B

Constraints and must be metA B

A ( ) ,

2

2

T I DS V v K

i −=:

S V

DS i

Ov

2

2O DS v

K i ≤

L

S

R

V

L o a d l i n e

B

for

GS v=

I v

A

2

2O DS v

K i ≤

L

O

L

S DS

R

v

R

V i −=

I O vvsv




2 Graphical method

Constraints and must be met.Then, given V I , we can find V O, I DS .A B

S V

DS i

Ov

L

S

R

V

B I v

A

2

2O DS v

K i ≤

I O vvsv

I V DS I

OV





1 vO versus v I

v

S V

( ) LT I S RV v K

V 2

2

−−Ov

T V

gets intotriode region

T O V vv −=




2 What are valid operating ranges

under the saturation discipline?

DS i

Ov

2

2O DS v K i ≤

S V

L

S

R

V

L

O

L

S DS

R

v

R

V i −=


T I O

T I

V vv

V v

−≥

≥2

2O DS v

K i ≤

OurConstraints

=T I

0=

DS i=

S O V v

V v

and

?

I v

( )2

2T I DS V v

K i −=




=T I

0= DS i= S O V v

V v

and

2 What are valid operating rangesunder the saturation discipline?

DS i

Ov

2

2O DS v

K i ≤

L

O

L

S DS

R

v

R

V i −=


I v

( )2

2T I DS V v

K i −=

L

S LT I

KR

V KRV v

211 ++−+=

L

S LO

KR

V KRv

211 ++−=

L

O

L

S DS

R

v

R

V i −=




Valid input range:

L

S L

T KR

V KR

V

211 ++−+

v I : V T to

corresponding output range:

L

S L

KR

V KR211 ++−

vO : V S to

2 Valid operating ranges under thesaturation discipline?

Large Signal AnalysisSummary

1 vO versus v I

( ) L

2

T I S O RV v2

K V v −−=




Amplifiers --

Small Signal Model

6.002 Fall 2000 Lecture 10 1



Review

MOSFET amp

S V

L

DS i

vO

v I

Saturation discipline — operateMOSFET only in saturation region

Large signal analysis1. Find vO vs v I under saturation discipline.

2. Validv I , v

O ranges under saturation discipline.

Reading: Small signal model -- Chapter 86.002 Fall 2000 Lecture 10 2



Large Signal Review

1 vO vs v I

vO = V S − K (v I −1)2 R L

2valid for v I ≥ V T

andvO ≥ v I – V T

(same as i DS ≤ K vO

2 )2

6.002 Fall 2000 Lecture 10 3



Large Signal Review2 Valid operating ranges

vV

5V corresponding v I −V T interesting v I

−V T

region for vOv I −V T

S

O

Ov = Ov >

Ov < 1V

v I V T 1V 2V “interesting” regionfor v I . Saturationdiscipline satisfied.

6.002 Fall 2000 Lecture 10 4



But…

S V

Ov

Ov = I v

5V

1V v I −V T

v I vO

Demo

V T 1V 2V

Amplifies alright,but distortsv I

vOt

Amp is nonlinear … / 6.002 Fall 2000 Lecture 10 5



Small Signal Model

~ 5V V S

~1V

Hmmm …

( ) L

T I

S O R

V v K

V v 2

2−

− = Amp all right, but nonlinear!

I v

Ov

T V

V 1 V 2~

Insight:

( ) O I V ,V

Focus on this line segment

So what about our linear amplifier ???

But, observe v I vs vO about somepoint (V I , V O) … looks quite linear !

6.002 Fall 2000 Lecture 10 6



Trickov

iv

I V

OV

( )OV V ,O

v∆ lookslinear

∆v I

Operate amp at V I

, V O

Æ DC “bias” (good choice: midpointof input operating range)

Superimpose small signal on top of V I Response to small signal seems to be

approximately linear

6.002 Fall 2000 Lecture 10 7



Trickov

iv

I V

OV

( )OV V ,O

v∆ lookslinear

∆v I

Operate amp at V I , V OÆ

DC “bias” (good choice: midpointof input operating range)

Superimpose small signal on top of V I

Response to small signal seems to beapproximately linear

Let’s look at this in more detail —I

III from a circuit viewpoint

graphically nextII mathematically week

6.002 Fall 2000 Lecture 10 8



I GraphicallyWe use a DC bias V I to “boost” interesting inputsignal above V T , and in fact, well above V T .

interestinginput signal

+ – + –

S V

L

vO

∆v I

V I Offset voltage or bias

6.002 Fall 2000 Lecture 10 9



Graphically

interesting

vO

∆v I

S V

L

+ – + –

input signal

V I

S V Ov

OV

operatingpoint

O I V V ,

I V

T V

O vv = 0

I −V T

v I

Good choice for operating point:midpoint of input operating range

6.002 Fall 2000 Lecture 10 10



Small Signal Modelaka incremental modelaka linearized model

Notation —Input:

total

v I = V I + vi

DC smallvariable bias signal (like ∆v I )

bias voltage aka operating point voltage

Output: vO = V O + vo

Graphically,v vvi

vo

V I V O

O

0 t 0 t 6.002 Fall 2000 Lecture 10 11



II Mathematically(… watch my fingers)

vO= V S

− R L K

(v I −V T )

2

V O = V S − R L

K

(V I −V T 2 2

substituting v I = V I + vi vi << V I

vO = V S − R L K ( [V I + vi ]− vT )

22

= V S − R L K ( [V I −V T ]+ vi )2

2= V S − R L K ([V I −V T ]

2+ 2[V I − vT ]vi

2

iv+ )2

OV + vo = ( 2

T I L

S V V 2

K RV −− ) − R L K (V I −V T )vi

rom ,vo = − R L K ( T I )V −V vi

g m related to V I

6.002 Fall 2000 Lecture 10 12



Mathematically

vo = − R L K ( T I )V −V vi g m related to V I

vo = − g m R L vi

For a given DC operating point voltage V I , V I – V T is constant. So,

vo = − A vi

constant w.r.t. vi

In other words, our circuit behaves like a linear amplifier

for small signals

6.002 Fall 2000 Lecture 10 13



Another way

vO

= V S

− R L K (v

I

−V T

)22

vo =

dv

d

I

V

S − R L

2

K (v I

−V T

)2

⋅ vi

I v = V

slope at V I vo = − R L K (V I −V T ) ⋅ vi

g m = K (V I −V T ) A = − g m R L amp gain

Also, see Figure 8.9 in the course notes

for a graphical interpretation of this result

6.002 Fall 2000 Lecture 10 14



More next lecture …

Demo DS i

I V

Ov

load line

operating pointinput signal response

V O

How to choose the bias point:

1. Gain component g m ∝ V I

2. vi gets big Æ distortion.

So bias carefully3. Input valid operating range.

Bias at midpoint of input operatingrange for maximum swing.

6.002 Fall 2000 Lecture 10 15




6.002 CIRCUITS AND

ELECTRONICS

Small Signal Circuits




Small signal notation

v A = V A + va

total operatingpoint

smallsignal

( ) i

V v

I

I

out

I OUT

vv f dv

d v

v f v

I I

⋅=

=

=

)(

S V

L

oOO vV v+=

I V

+ –

+ –

i I I vV v +=

iv

Review:




I Graphical view

(using transfer function)

behaves linear

for smallperturbations

I v

Ov

Review:




II Mathematical view

( ) L

T I S O R

V v K V v

2

2−

−=

( )

i

V v

LT I S

I

o v

RV v K

V

dv

d v

I I

⋅

−−

=

=

2

2

related to V I

constant for fixed

DC bias

( ) i LT I o vV V K v ⋅−−=

g m

Review:




Demo

Choosing a bias point:

DS i

Ov

L

S LT I

KR

V KRV v

211 ++−+=

T I V v =

2

O DS v2

K i <

load line L

O

L

S DS

R

v

R

V i −=

How to choose the bias point,using yet another graphical viewbased on the load line

OV

I V

input signalresponse

I Lm V ∝1. Gain

2. Input valid operating range for amp.

3. Bias to select gain and input swing.




III The Small Signal Circuit View

We can derive small circuit equivalentmodels for our devices, and thereby conductsmall signal analysis directly on circuits

( )2T I D V v2

K i −=

+

–OUT v V S

+ –

v 1

e.g. large signalcircuit modelfor amp

We can replace large signal models withsmall signal circuit models.

Foundations: Section 8.2.1 and also in the

last slide in this lecture.




Small Signal Models

MOSFET A

largesignal ( )2

2T GS DS V v

K i −=

D

S

GS v

Small signal?




Small Signal Models

MOSFET A

largesignal ( )2

2T GS DS V v

K i −=

D

S

GS v

Small signal:

smallsignal

D

S

gsv

( ) gsT GS ds vV V K i −=

gsmds vi =

( )22

T GS DS V v K

i −=

( )gs

V vT GS

GS ds

vV v K

vi

GS GS

⋅

−∂

∂=

=

2

2

( ) gsT GS ds vV V K i ⋅−=

g m

ids is linear in v gs !



6.002 Fall 2000 Lecture 1011

DC Supply V S

B

largesignal

S S V v =

s

I iS

S s i

i

V v

S S

⋅∂

∂=

=

0v s =

+ – S S V v =

S i

+

– sv

si

DC source behaves

as short to smallsignals.

Small signal



6.002 Fall 2000 Lecture 1111

Similarly, RC

largesignal

smallsignal

+

–

vi

+

–r v

r i

R iv =

( )r

I i R

Rr i

i

Riv

R R

⋅∂

∂=

=

r r iv ⋅=



6.002 Fall 2000 Lecture 1211

Large signal

( )22

T I DS V v K

i −=

( ) LT I S O RV v K

V v2

2−−=

L

Ov

+ – I v

+ – S V

DS i

L

ov

+ – iv dsi

( ) iT I ds vV V K i ⋅−=

0=+ o Lds vi

Ldso iv −=

( ) i LT I o vV V K v ⋅−−=

i Lm v g ⋅−=

Small signal

Amplifier example:

Notice, first we need to find operatingpoint voltages/currents.

Get these from a large signal analysis.



6.002 Fall 2000 Lecture 1311

To find the relationship between the small signal parameters ofa circuit, we can replace large signal device models withcorresponding small signal device models, and then analyze theresulting small signal circuit.

Foundations: (Also see section 8.2.1 of A&L)

KVL, KCL applied to some circuit C yields:

III The Small Signal Circuit View

b Bout OUT a A vV vV vV +++++++

Replace total variables withoperating point variables plus small signal variables

Operating point variables themselves satisfy thesame KVL, KCL equations

BOUT A V V V ++++

so, we can cancel them out

BOUT A vvv ++++++ 1

bout a vvv ++++

Leaving

2

Since small signal models are linear, our linear tools will nowapply…

But is the same equation as with small signalvariables replacing total variables, so must reflect sametopology as in C, except that small signal models are used.

2 1

2




6.002 CIRCUITS AND

ELECTRONICS

Capacitorsand First-Order Systems




5V

0V

C

A

B

5V

A

B

C

5

0

5

0

5

0

Reading:

Chapters 9 & 10

Demo 5V

Expected

Observed

Expect this, right?But observe this!

Delay!

Motivation




The Capacitor

G

D

S

n-channel MOSFET symbol

n-channelMOSFET

n-channel

s

i

l

i

co

n

n

met

al

++++++

oxi

de

drain

gate

source

C GS

G D

S

n

p




Ideal Linear Capacitor

obeys DMD!

total charge oncapacitor0qq =−+=

d

EAC =

+ ++ + + +

- -- - - - -

A

E

d

coulombs farads volts

vC q =

i

C

q +

–v




Ideal Linear Capacitor

dt dqi =

( )dt

Cvd =

dt dvC =

i

vC q =

C q +

–v

A capacitor is an energy storage device memory device history matters!

= 2

2

1Cv E




Apply node method:

C

+

–( )t vC

( )t v I + –

Thévenin Equivalent:

0=+−dt dvC vv C I C

I C C vv

dt

dvC R =+

0t t ≥

( )0t vC given

unitsof time

Analyzing an RC circuit




Let’s do an example:

( ) I I V t v =

( )0

0 V vC = given

I C

C

V vdt

dv

C R=+

X

C

+

–( )t vC

( )t v I +

–

R




Example…

Method of homogeneous and particular

solutions:1

2

3

Find the particular solution.

Find the homogeneous solution.

The total solution is the sum ofthe particular and homogeneoussolutions.

Use the initial conditions to solvefor the remaining constants.

( ) I I V t v =

( ) ( ) ( )t vt vt v CP CH C +=

total homogeneous particular

( )0

0 V vC = given

I C C V v

dt

dvC R =+ X




1 Particular solution

I CP CP V vdt

dvC R =+

I CP V v = works

I I I V V

dt

dV C R =+

0

In general, use trial and error.

vCP : any solution that satisfies the

original equation X



6.002 Fall 2000 Lecture 1012

2 Homogeneous solution

0=+CH

CH vdt

dvC R

YvCH : solution to the homogeneous

equation(set drive to zero)

Y

0=+ st st

e Adt

edAC R

0=+st st e Ae sCA R

st

CH e Av = assume solutionof this form. A, s ?

Discard trivial A = 0 solution,

01=+ sC Characteristic equation

C s 1−=

RC

t

CH Aev−

=or RC called timeconstant τ



6.002 Fall 2000 Lecture 1112

3 Total solution

Find remaining unknown from initialconditions:

CH CP C vvv +=

RC t

C e AV v−

+=

also ( ) RC

t

I 0C C eV V

dt dvC i

−

−−==

thus

Given,

so,

or

0C V v = at t = 0

V V I 0 +=

I 0 V V −=

( ) RC

t

I 0 I C eV V V v−

−+=



6.002 Fall 2000 Lecture 1212

t

C v

V

0V

( ) RC

t

0C eV V V v−

−+=

C 0



6.002 Fall 2000 Lecture 1312

t

C v

V 5

V 0

V V I 5=

V V O 0= 5

0 V V I 0=

V V O 5= 5

0

t

C v

V 5

V 0

RC

t

e−

+ 55RC

t

e

−

5

C =τ

Remember

demo B

Examples




6.002 CIRCUITS AND

ELECTRONICS

Digital Circuit




C +

–C vv +

–

t

C v

OV

I V

( ) RC

t

I O I C eV V V v−

−+= 1

( ) OC V v =0

t

V

I v

0

Review

time constant RC

C




Let’s apply the result toan inverter.

A

B

V S V S

X C GS

t

v

V 5

0

1 0 at A

A B

X

First, rising delay t r at B




A B

V S V S

X C GS

idealt

v

V 5

0

1 0 at A


observedt

Bv

V 5

0




A B

V S V S

X C GS

t

v

V 5

0

1 0 at AOH V

r t rising delay of X


t

Bv

V 5

0




Equivalent circuit for 01 at B

+

– BvS V v = +

–

L

GS C

( ) GS LC R

t

S S B eV V v

−

−+= 0

1From

Now, we need to find t for whichv B = V OH .

S V v =

for t ≥ 0( ) 00 = Bv




GS LC R

t

S S OH eV V v

−

−=

Or

Find t r :

OH S

C R

t

S V V eV GS L

r

−=

−

S

OH S

GS L

r

V

V V

C R

t −=

−ln

S

OH S GS Lr

V

V V C Rt

−−= ln




GS LC R

t

S S OH eV V v

−

−=

Or

Find t r :

OH S

C R

t

S V V eV GS L

r

−=

−

S

OH S

GS L

r

V

V V

C R

t −

=

−

ln

S

OH S GS Lr

V

V V C Rt

−−= ln

e.g. K L 1=

pF C GS 1.0=

V V S 5=

V V OH 4=

5

45ln101.0101t 123

r

−×××−=

−

ns16.0=

!1.0 nsC =




Falling Delay t f

S V + –

L

+

– Bv

GS

C ON

( )( )V V v S B

50 =

Falling delay t f is

the t for which v B falls to V OL

Equivalent circuit for 1 0 at B



6.002 Fall 2000 Lecture 1013

Falling Delay t f Equivalent circuit for 1 0 at B

ON LTH ||=

LON

ON S TH

R RV V

+=

Thévenin replacement …

+

– BvTH V

TH

GS C + –

S V + –

L

+

– BvGS C ON

( )( )V V v S B

50 =



6.002 Fall 2000 Lecture 1213

TH S

TH OLGS TH f

V V

V V C Rt

−

−−= ln

e.g.

5

1ln101.010 12−

⋅⋅−= f t

ps6.1=

!1 psC =

K L 1=

pF C GS

1.0=

V V S 5=

V V OL

1=

Ω=10ON

V V TH TH 0,10 ≈Ω≈



6.002 Fall 2000 Lecture 1313

For recitation: Slow may be better

Problem

pin 2

pin 1

chip

LC

So the engineers decided to speed it up…made R L smallmade RON small

R L

RON

ideal slow!observedv:

v



6.002 Fall 2000 Lecture 1413

For recitation: Slow may be better

Problem

pin 2

pin 1

chip

LC

ideal slow!observed

… but, disaster!

v:

v

expected

v:

V IL

observed



6.002 Fall 2000 Lecture 1513

Why? Consider…1Case 1

0

pin1

ok

Demo



6.002 Fall 2000 Lecture 1613

Why? Consider…

2Case1

0

pin1

2

pin2

P C

crosstalk!

Demo

model for crosstalk:

+

–

v

P C

+ –




State and Memory

6.002 Fall 2000 Lecture 14 1



Review

Recall

v I C + –

+vC –

v I

= V I for t ≥ 0 vC ( ) 0

−t

vC = V I + (vC ( )−V I ) e RC 0 1

Reading: Section 10.3 and Chapter 11

6.002 Fall 2000 Lecture 14 2



StateState : summary of past inputs relevant

to predicting the future

q = C V

for linear capacitors,capacitor voltage V is also state variable

state variable, actually

6.002 Fall 2000 Lecture 14 4



State

Back to our simple RC circuit 1

vC = f (vC (0),v I (t )) −t

vC = V I + (vC ( ) −V I ) e RC 0

Summarizes the past input relevantto predicting future behavior

6.002 Fall 2000 Lecture 14 5



State

We are often interested in circuitresponse for

zero state vC (0) = 0

zero input v I (t ) = 0

Correspondingly,

zero state response or ZSR −t

vC = V I −V I e RC

zero input response or ZIR

−t

vC = vC ( )e RC 0

2

3

6.002 Fall 2000 Lecture 14 6



One application of STATE

DIGITAL MEMORYWhy memory?Or, why is combinational logic insufficient?Examples

Consider adding 6 numbers on yourcalculator

2 + 9 + 6 + 5 + 3 + 8

M+ “Remembering” transient inputs

6.002 Fall 2000 Lecture 14 7



Building a memory element …A

d IN

*

vC d OUT

C store = 1

d IN

*

vC d OUT

Stored value leaks away

vC

t

5V

V OH

store = 0C

R L

−t T vC = 5 ⋅e

R LC from

T = − R LC lnV OH 5

2

store pulse width >> RON C

6.002 Fall 2000 Lecture 14 10



Building a memory element …Second attempt bufferB

R IN buffer

d IN d OUT

C *

store

Input resistance R IN

T = − R IN C lnV OH

5

R IN >> R L

Better, but still not perfect.

Demo

6.002 Fall 2000 Lecture 14 11



Building a memory element …C Third attempt buffer + refresh

store

d IN

store

d OUT

C

* Does this work?

No. External value caninfluence storage node.

6.002 Fall 2000 Lecture 14 12



Building a memory element …

D Fourth attempt

buffer + decoupledrefresh

stored IN

store

d OUT

C

* Works!

6.002 Fall 2000 Lecture 14 13



A Memory Array IN

4-bit memory store

Address

OUT

Decoder IN d

OUT d

S

IN d

OUT d S

IN d

OUT d S

IN d

OUT d S

A

B

C

D

00

10

01

11

IN storeOUT

A

B

C

M

M

M

M

a0a1 2Address

D

6.002 Fall 2000 Lecture 14 14



Truth table for decoder

a0 a1 A C D

0 0 0 0

0 1 0 0

1 0 1 0

1 1 0 1

B

01

10

00

00

6.002 Fall 2000 Lecture 14 15



Agarwal’s top 10 list on memory

10 I have no recollection, Senator.9 I forgot the homework was due today.8 Adlibbing ≡ ZSR

7 I think, therefore I am.6 I think that was right.5 I forgot the rest …

6.002 Fall 2000 Lecture 14 16




6.002 CIRCUITS AND

ELECTRONICS

Second-Order Systems





C A

B

5V

+ –

5V

C GS

large

loop

2 K Ω50Ω

2 K Ω

Demo

Our old friend, the inverter, driving another.The parasitic inductance of the wire and

the gate-to-source capacitance of theMOSFET are shown

[Review complex algebra appendix for next class]

S





C A

B

5V

+ –

5V

C GS

large

loop

2 K Ω50Ω

2 K Ω

Demo

+ –5V C GS

2K Ω B

LRelevant circuit:

S




Now, let’s try to speed up our inverter byclosing the switch S to lower the effectiveresistance

t

v A

5

0

v B

0 t

vC

0 t

Observed Output

2k Ω

2k Ω




t

v A

5

0

v B

0 t

vC

0 t

Observed Output ~50 Ω

50Ω

Huh!




v, i state variables

+ –

C L +

–

)(t v)(t v

)(t i

Node method:

dt

dvC t i =)(

dt dvC dt vv

L

t

I =−∫ ∞−

)(1

2

2

)(1

dt

vd C vv

LI =−

I vvdt

vd LC =+

2

2

time2

dt

di Lvv

I

=−

idt vv L

t

I =−∫ ∞−

)(1

Recall

First, let’s analyze the LC network




Recall, the method of homogeneous and

particular solutions:

( ) ( )t vt vv H P +=

1

2

3

Find the particular solution.

Find the homogeneous solution.

4 steps

The total solution is the sum of theparticular and homogeneous.

Use initial conditions to solve for theremaining constants.

Solving




And for initial conditionsv(0) = 0 i(0) = 0 [ZSR]

I v

0V

0t

Let’s solve

I vvdt

vd LC =+2

2

For input




1 Particular solution

02

2

V vdt

vd LC P

P =+

0V v P = is a solution.



6.002 Fall 2000 Lecture 1015

02

2

=+H

H

vdt

vd

LC

Solution to

Homogeneous solution2

Recall, v H : solution to homogeneousequation (drive set to zero)

Four-step method:

D t j

2

t j

1 H oo e Ae Av

ω ω −+=

General solution,

RootsC o j s ω ±= LC 1o =ω

Assume solution of the form*A? s , A , Aev st

H ==

so, 02 =+ st st ee LCAs

*Differential equations are commonlysolved by guessing solutions

1−= j LC

j s1

±=

B LC

s 12 −= characteristicequation



6.002 Fall 2000 Lecture 1115

Total solution3

Find unknowns from initial conditions.

t j

2

t j

10 oo e Ae AV )t ( vω ω −

++=

)()()( t vt vt v P +=

0)0( =v

2100 V ++=

0)0( =i

t j

o2

t j

o1oo e jCAe jCA )t ( i

ω ω

ω ω −−=

dt

dvC t i =)(

so, o2o1 jCA jCA0 ω ω −=

or, 21 =

V 20 =−

20

1

V A −=

( )t jt j00

oo ee2

V V )t ( v

ω ω −+−=so,



6.002 Fall 2000 Lecture 1215

Remember Euler relation

(verify using Taylor’sexpansion)

x j xe jx sincos +=

xee jx jx

cos2

=+ −

t sinCV )t ( i oo0 ω ω =

t cosV V )t ( v o00 ω −=so, where

LC

1o =ω

Total solution3

The output looks sinusoidal



6.002 Fall 2000 Lecture 1315

)(t v

02V

0V

0

2

π

2

3π π π 2t oω

)(t io0CV ω

02π

23π π π 2

to

ω

o0CV ω −

Plotting the Total Solution



6.002 Fall 2000 Lecture 1415

Summary of Method

1

2

3

Write DE for circuit by applyingnode method.

Find particular solution v P by guessingand trial & error.

Find homogeneous solution v H

4 Total solution is v P + v H ,solve for remaining constants usinginitial conditions.

Assume solution of the form Ae st .

Obtain characteristic equation.

Solve characteristic equationfor roots si .

Form v H by summing Ai e sit

terms.D

C

A

B



6.002 Fall 2000 Lecture 1515

What if we have:

We can obtain the answer directly from

the homogeneous solution (V 0 = 0).

V vC =)0(

0)0( =C iC L

C i +

–C v

Example



6.002 Fall 2000 Lecture 1615

We can obtain the answer directly fromthe homogeneous solution (V 0 = 0).

t j

2

t j

1C oo e Ae A )t ( v

ω ω −+=

V vC =)0(

0)0( =C i

21V +=

o2o1 jCA jCA0 ω ω −=

or2

21

V A A ==

( )t jt jC

oo ee2V v ω ω −+=or

t cosV v oC ω =

t sinCV iooC

ω ω −=

V vC =)0(

0)0( =C iC L

C i +

–C v

Example



6.002 Fall 2000 Lecture 1815

222

2

1

2

1

2

1CV LiCv C C =+Notice

Energy

2

2

1: C CvC

2

2

1: C Li L

t oω

π 2

C E

2

21 CV

t oω

π 2

L E

2

2

1CV

Total energy in the system is a constant,but it sloshes back and forth between theCapacitor and the inductor



6.002 Fall 2000 Lecture 1915

RLC Circuits

See A&L Section 13.2

add R

no R

+ –

C

R L

+

–

)(t v)(t v I

)(t i

)(t v

t

Damped sinusoids with R – remember demo!




Sinusoidal Steady State

6.002 Fall 2000 Lecture 16 1



Review

We now understand the why of:

5V

C

R

L

v

Today, look at response of networksto sinusoidal drive.

Sinusoids important because signals can berepresented as a sum of sinusoids. Response tosinusoids of various frequencies -- aka frequencyresponse -- tells us a lot about the system

6.002 Fall 2000 Lecture 16 2



MotivationFor motivation, consider our old friend,the amplifier:

S V

vO

vi

C v

+ – + – GS C

V BIAS

Observe vo amplitude as the frequency of theinput vi changes. Notice it decreases withfrequency.

Also observe vo shift as frequency changes(phase).

Need to study behavior of networks forsinusoidal drive.

Demo

6.002 Fall 2000 Lecture 16 3



Sinusoidal Response of RC NetworkExample:

+ –

iC +

v I vC

–

v I (t ) = V i cosω t for t ≥ 0 (V i real)= 0 for t < 0

vC (0) = 0 for t = 0 I v

0 t

6.002 Fall 2000 Lecture 16 4



1 1 1 1 e c t u r

Example:+ –

Our Approach

iC +

v I vC –

Determine vC (t) Indulge me !

E f f o r t

l e c t u r e

sneaky approach

very

sneaky

Usual

approach

agony

easyt e

0 : 0 : 0 0 2 1 0 : 2

l s

h i T t x e

N

6.002 Fall 2000 Lecture 16 5



Let’s use the usual approach…1 Set up DE.

2 Find v p.

3 Find v H .

4 vC = v P + v H , solve for unknownsusing initial conditions

6.002 Fall 2000 Lecture 16 6



Usual approach…

1 Set up DE

RC dvC + vC = v I

dt = V i cosω t

That was easy!

6.002 Fall 2000 Lecture 16 7



2 Find v p

RC

dv P +dt v P

= V i

cosω t

First try: v P = A Æ nope

Second try: v P = Acosω t Æ nope

Third try: v P = Acos(

amplitude

φ ω + t frequency)

phase

− RCAω sin(ω t +φ ) + Acos(ω t +φ ) = V i cosω t

− RCAω sinω t cosφ − RCAω cosω t sinφ + Acosω t cosφ − Asinω t sinφ = V i cosω t

.. gasp !.works, but trig nightmare!

6.002 Fall 2000 Lecture 16 8



6.002 ll 2000 Lecture 916

Let’s get sneaky!

Try solution st

p PS eV v = st

i

st

p

st

peV eV

dt

edV RC =+

st

i

st

p

st

p eV eV e sRCV =+ i p V V )1 sRC ( =+

sRC 1

V V

i p

+ =

Nicepropertyof

exponentials

IS PS

PS vvdt

dv RC =+ (S: sneaky :-))

st

ieV =

Find particular solution to another input…

pV complex amplitude

Thus, st i PS e

sRC 1

V v ⋅

+ = st

ieV is particular solution toeasy!

where we replace s = jω ly t j

ieV ω solution for

t ji e RC j

V ω ω ⋅

+1

Fa



2 Fourth try to find v P …

using the sneaky approach

Fact 1: Finding the response toV ie

jω t

was easy.

Fact 2: v I = V i cosω t

= real[V ie jω t ]= real[v IS ]

from Euler relation,

j

I v P vresponse

IS v PS vresponse

realpart

realpart

e jω t = cosω t + sinω t

an inverse superposition argument,assuming system is real, linear.

6.002 Fall 2000 Lecture 16 10



2 Fourth try to find v P …

so, complex

P v = Re[v PS ] =

Re[V pe

jω t

]

V i= Re

1+ jω RC

⋅ e jω t

= ReV i (1− jω RC ) ⋅ e jω t 1+ω 2 R2C 2

= Re

C 1

222

ω +

V i ⋅ e jφ e jω t ,tanφ = −ω RC

= Re + 222 C 1 ω

V i ⋅ e j( ω t +φ )

v P = C 1 222ω + V i ⋅ cos( ω t +φ )

Recall, v P is particular response to V i cosωt .

6.002 Fall 2000 Lecture 16 11



3 Find v H −t

Recall, v H =

Ae

RC

6.002 Fall 2000 Lecture 16 12



4 Find total solution

vC =

P v+

v H

t −

vC = 222 C 1+ ω

V i cos( ω t +φ ) + Ae RC

where φ = tan−1( −ω RC )

Given vC (0) = 0 for t = 0

so,

A = − 1 222ω C +

V i cos(φ )

Done! Phew !

6.002 Fall 2000 Lecture 16 13



Sinusoidal Steady StateWe are usually interested only in the

particular solution for sinusoids,i.e. after transients have died.

t −

Notice when t → ∞, vC → v P as e RC → 0

222

iC cos(

C 1

V

+ = ω

tanwhere φ = A − =

pV

RC

t

Ae )t −

+ +φ ω

) RC ( 1 ω −−

cos(1 222

φ ω C

V i

+

0 v

)

Described as

SSS: Sinusoidal Steady State

pV ∠

6.002 Fall 2000 Lecture 16 14



Sinusoidal Steady StateAll information about SSS is contained

in V p , the complex amplitude!

Recall RC j1

V V i

pω + = Steps 3 ,

were a waste oftime!

4

V p 1=

V i 1+ jω RC

V p

ω 222

i C R1V +

= 1e jφ

where

φ = tan−1 −ω RC

2221

1

C RV

V

i

p

ω + =

RC V

V

i

pω φ 1tan: phase −−=∠

magnitude

6.002 Fall 2000 Lecture 16 15



Sinusoidal Steady StateVisualizing the process of finding theparticular solution v

P

sneakin

V i e j ωt

drive

algebraicequation

+complex

algebra

takerealpart

t j

peV ω

particularsolution

t V i ω cos D.E.+

nightmaretrig.

drive [ p V t V ∠+ ω cos p

the sneaky path!

6.002 Fall 2000 Lecture 16 16



Magnitude Plottransfer function

V

H ( jω )=

V

p

i2221

1

C RV

V

i

p

ω +=

V p1

V i

logscale

ω log 1

ω =

scale RC

From demo: explains vo fall offfor high frequencies!

6.002 Fall 2000 Lecture 16 17



Phase Plotφ = tan−1 −ω RC

V φ = ∠ p

V i

0

π − 4π

− 2

ω C

1= ω

log scale

6.002 Fall 2000 Lecture 16 18




6.002 CIRCUITS AND

ELECTRONICS

The Impedance Model




Sinusoidal Steady State (SSS)Reading 14.1, 14.2

+

–Ovt V v i I ω cos= +

– C

Focus on steady state, only careabout v P as v H dies away.

Focus on sinusoids.

Reading: Section 14.3 from course notes.

SSS

Review

Sinusoidal Steady State (SSS)Reading 14.1, 14.2




3

4v

total

Review

V p contains all the information we need:

p

p

V

V

∠

Amplitude of output cosine

phase

sneakin

V i e j ωt

drive

complexalgebra

takerealpart

The Sneaky Path

pV

t V i ω cos [ p p V t V ∠+ω cos

setupDE

usualcircuitmodel

nightmaretrig.

1

v P

t j

p eV ω

RC j

V iω +1

2




i

p

V

V

transferfunction

( )ω

ω

j H RC jV

V

i

p =+

=1

1

( ) p pO V t V v ∠+= ω cos

2221

1

C ω +

break frequencyBode plot

ω

C

1=ω

1

C 1

ω

2

1

remember

demo

ω

RC

1=ω

4

π

−

2

π

−

0i

p

V

V ∠

−−

1

RC an

1 ω

The Frequency View

Review




Is there an even simpler wayto get V p ?

RC jV V i

pω +

=1

Divide numerator and denominator by jωC .

RC j

C jV V i p

+=

ω

ω

1

1

Let’s explore further…

Hmmm… looks like a voltage dividerrelationship.

R Z

Z V V

C

C i p

+=




The Impedance Model

Is there an even simpler way to get V p ?

Consider:t j

r R e I i ω =t j

r R eV v ω =

R R iv =t j

r

t j

r e RI eV ω ω =

r r I V =

Ri+

– Rv

Resistor

t j

C C e I i ω =

t j

C C eV v ω =C

C i+

–

C v

Capacitor C C I C j

1V

ω

=

dt

dvC i C

C =

t j

C

t j

C e jCV e I ω ω

ω =

C Z

L

Li+

– Lv

t jl L e I i ω

=

t j

l L eV v ω =

dt di Lv L

L =

t j

l

t j

l e j LI eV ω ω

ω =

Inductorl l L jV ω =

L Z




In other words,

For a drive of the form V ce jωt

,

complex amplitude V c is related to thecomplex amplitude I c algebraically,by a generalization of Ohm’s Law.

inductor

L j Z l ω =l l l Z V =

l I

+

–l V L Z

resistorr r r Z V =

Z r = R Z

r

+

–r V

capacitor

C j

1 Z C

ω

=

cC c Z V =

impedance

c+

–cV C Z

The Impedance Model




Impedance model:

All our old friends apply!KVL, KCL, superposition…

Back to RC example…

i

RC

C ic V

Z Z

Z V

RC j

1

C j

1

V +

=+

=

ω

ω

ic V RC j1

1V ω +

= Done!

+

–C vv +

– C

+

–cV iV +

–

Z R =

C j Z C

ω

1=

c




Another example, recall series RLC:

We will study this and other functionsin more detail in the next lecture.

RC j

L j

V V i

r

++=

ω

ω

1

C L

Rir

Z Z Z

Z V V

++=

CR j LC CR jV V i

r ω ω

ω

++−=

12

+ –

L

r

C +

–r V

iV t j

r eV

ω

( )r r V t V ∠+ω cos

t j

ieV

ω

t V i ω cos

Remember, we want only the steady-stateresponse to sinusoid



6.002 Fall 2000 Lecture 1017

The Big Picture…


setupDE

usualcircuitmodel

nightmaretrig.



6.002 Fall 2000 Lecture 1117

The Big Picture…


setupDE

usualcircuitmodel

nightmaretrig.

V i e j ωt

drive

complex

algebra

take

realpart



6.002 Fall 2000 Lecture 1217

The Big Picture…

No D.E.s, no trig!


setupDE

usualcircuitmodel

nightmaretrig.

V i e j ωt

drive

complex

algebra

take

realpart

complex

algebra

impedance-based

circuit model



6.002 Fall 2000 Lecture 1317

Back to

LC RC j1

C j

V

V 2

i

r

ω ω

ω

−+=

( ) ( ) RC j LC 1

RC j LC 1

RC j LC 1

RC j2

2

2ω ω

ω ω

ω ω

ω

−−

−−⋅

+−=

( ) ( )222

i

r

RC LC 1

RC

V

V

ω ω

ω

+−=

:Low ω C ω ≈

:High ω

Lω

≈

:1 LC =ω 1≈

Let’s study this transfer function

+ –

L

r I

+

–r V

i

R

LC RC j1

C j

V

V

2i

r

ω ω

ω

−+=

Observe



6.002 Fall 2000 Lecture 1417

Graphically

( ) ( )2221 RC LC

RC

V

V

i

r

ω ω

ω

+−=

More next week…

:Low ω C ω ≈

:High ω

Lω

≈

:1 LC =ω 1≈

i

r

V

V

LC

1 ω

Lω

RC ω

1 “Band Pass”

Remember this trick to sketch the form oftransfer functions quickly.




6.002 CIRCUITS AND

ELECTRONICS

Filters




Review

+

–C v I v +

– C

Reading: Section 14.5, 14.6, 15.3 from A & L.

+

–cV iV +

–

Z

C Z

i

RC

C c V

Z Z

Z V ⋅

+=

RC j11

RC j

1C j

1

V V

i

c

ω

ω

ω

+=

+=




A Filter

RC j11V

Z Z Z V i

RC

C c

ω +=⋅

+=

“Low Pass Filter”

ω

1( ) i

c

V

V

H =ω

Demowith audio

+

–cV iV +

–

Z

C Z




Quick Review of Impedances-Just as

21

ab

ab AB R R

I

V R +==

L j R I

V Z 1

ab

ab AB ω +==

1

ab +

–

abV

2

B

1

ab

+

–

abV

L jω

B




Quick Review of ImpedancesSimilarly

L2C 1 B Z || Z Z ++=

L2C

2C

1Z

R Z

Z R +

++=

L jCR j1

R2

21 ω

ω

++

+=

1

L

B

2C




We can build other filters bycombining impedances

( )ω Z

L

R

C ω

Z




We can build other filters bycombining impedances

HPFHigh Pass Filter

ω

( )ω H

ω

( )ω H

LPFLow Pass Filter

ω

( )ω H

HPF

( )ω Z

L R

C ω

Z

+ –

+ –

+ –




Check out:

RC j

1 L j

R

V

V

i

r

++=

ω

ω

RC j LC 1

RC j2

ω ω

ω

+−=

( ) ( )222i

r

RC LC 1

RC

V

V

ω ω

ω

+−=

ω

+ –

L C

+

–r V iV

LC

1o =ω

At resonance,ω = ωo

and Z L + Z C = 0,so V i seesonly R!

More later…

Intuitively:

i

r

V

V 1

C b l o c k s hi g h f r e q L b l o c k

s l o w f r

e q




What about:

+ –

LC

+ –lcV

iV

Band Stop Filteri

lc

V V

ω

1C open L open

Check out V l and V c in the lab.



6.002 Fall 2000 Lecture 1018

Another example:

+

–

+ –

LiV C oV

i

o

V

V

oω ω

BPF

C s h o r t L s h o r t

Application: see AM radio coming up shortly



6.002 Fall 2000 Lecture 1118

AM Radio Receiver

crystal radio demo

Théveninantenna

model

+ – LiV C

demodulator

amplifier

antenna



6.002 Fall 2000 Lecture 1218

AM Receiver

“Selectivity” important —relates to a parameter “Q” for the filter. Next…

+ – LiV C

demodulator

amplifier

f

signalstrength

540 …1000 1010 1020 1030 … 1600 KHz

10 KHz

filter WBZNewsRadio



6.002 Fall 2000 Lecture 1318

Recall,

Selectivity:Look at series RLC in more detail

+ –

L C

+

–r V

iV

C j1 L j R

R

V

V

i

r

ω

ω ++

=

i

r

V

V

ω

oω

21

higher Q1

Define quality factor ∆

=Q o

ω

ω

ω ∆bandwidth

⇒Qhigh more selective



6.002 Fall 2000 Lecture 1418

ω

ω

∆

= oQ

LC

1o =ω

Quality Factor Q

−+

=++

=

CR

1

R

L j1

1

C j

1 L j RiV

r V

ω

ω

ω

ω

?ω ∆

at =0ω ο

ω ο :



6.002 Fall 2000 Lecture 1518

Note that abs magnitude is2

1

when1 j1

1

CR

1

R

L j1

1

V

V

i

r

±=

−+

=

ω

ω

i.e. when 1CR

1

R

L±=−

ω

ω

0 LC

1

L

2 =−ω

ω ∓

:ω ∆

ω

ω

∆= oQ

Quality Factor Q

Looking at the roots of both equations,

LC

4

L

R

2

1

L2

R2

2

1 ++=ω

LC

4

L

R

2

1

L2

R2

2

2 ++−=ω

R=−=∆ 21 ω ω ω



6.002 Fall 2000 Lecture 1618

R

L

L

RQ oo ω ω

==

The lower the R (for series R),the sharper the peak

ω

ω

∆= oQ

Quality Factor Q

LC

1o =ω



6.002 Fall 2000 Lecture 1718

Another way of looking at Q :

cycle per lostenergy

storedenergy2π =Q

0

2

r

2

r

2 R I

2

1

I L21

2

ω

π

π =

LQ oω

=

Quality Factor Q




6.002 CIRCUITS AND

ELECTRONICS

The Operational AmplifierAbstraction




MOSFET amplifier — 3 ports

power

portinputport

outputport+

–

v

+

–

Ov

+

–

S V

Amplifier abstraction

+

– I v

+

–

S V

+

–Ov

I v

Ov

Function of v I

Review




Can use as an abstract building block for

more complex circuits (of course, needto be careful about input and output).

Today

Introduce a more powerful amplifier

abstraction and use it to build morecomplex circuits.

Reading: Chapter 16 from A & L.

I v

Ov

Function of v I

Review




Operational AmplifierOp Amp

OUT v

+

–

+

– N

v

More abstract representation:

input

port

S V

outputport

powerport

S V −

+ –

+ –

+

–




Circuit model (ideal):

i.e. ∞ input resistance

0 output resistance

“ A” virtually ∞

No saturation

Ov

v

∞→

+ –

+

–

v

v+

v –

0=i+

0=i –




(Note: possible confusion with MOSFET saturation!)

Using it…

+

–V V

S 12−=− L

R

Ov

+ –12V

+ –12V V V

S 12=

Demo

IN v

µV10µV10−

Ov

V12

V12−

6

10~but unreliable,temp. dependent

saturation

active region

N v




Let us build a circuit…Circuit: noninverting amplifier

Equivalent circuit model

1

Ov

+ –

2

N v

+v

−v

−+ − vv A+

–

0=i+

0=i –

o p a m p

1

Ov

+ –

2

IN v

+

–

+

v

−v




Let us analyze the circuit:

Find vO

in terms of v IN , etc.

What happens when “ A” is very large?

( )−+ −= vv AvO

+−=

21

2

R R

Rvv AO IN

IN

21

2

OAv

R R

AR1v =

++

21

2

IN

O

R R

AR1

vv

++

=




Let’s see… When A is large

Gain: determined by resistor ratio insensitive to A, temperature, fab variations

21

2

IN

O

R R

AR1

vv

++

=

( )

2

21

IN

Rv

+≈

gain

Demo

Suppose6

10=9

1=

=2

9 R101

v10v

6

IN

6

O

++

⋅=

10vv IN O

⋅≈10

1101

v10

6

IN

6

⋅+

⋅=

21

2

IN

R R

AR

v

+

≈



6.002 Fall 2000 Lecture 1019

e.g. v IN = 5VSuppose I perturb the circuit…

(e.g., force vO

momentarily to 12V somehow).

Stable point is when v+≈ v- .

Key: negative feedback portion ofoutput fed to – ve input.

e.g. Car antilock brakes small corrections.

Why did this happen?

Insight:

+

– IN Ov2v =

+ – IN

v

+v

−v

negativefeedback

2

vO

5V

5V

10V

0i = –

12V

6V6V



6.002 Fall 2000 Lecture 1119

Question: How to control ahigh-strung device?

Antilock brakes

Michelinno yes

f e e d b a

c kyes/no

is itturning?

it’sall aboutcontrol

d i s

c

v. v. powerful brakes

applyrelease



6.002 Fall 2000 Lecture 1219

More op amp insights:

Observe, under negative feedback,

0

v R R R

vvv

IN

1

21

O →

+

==− −+

−+ ≈ vv

We also knowi+≈ 0

i -≈ 0

yields an easier analysis method(under negative feedback).



6.002 Fall 2000 Lecture 1319

Insightful analysis methodunder negative feedback

+

–1

Ov

+ –

2

IN v

IN vc

2

21

IN O

Rvv +=g

IN vb

0=ie

2

IN

R

vd

2

IN

R

v

f

0i

0i

vv

≈

≈

≈

−

+

−+

IN va



6.002 Fall 2000 Lecture 1419

Question:

+

–Ov

+ – IN

v

+v

−v ?

01 =

∞=2

2

21

Rvv IN O

+=or

with

N Ovv ≈

IN vc

IN vb

IN va



6.002 Fall 2000 Lecture 1519

Buffervoltage gain = 1

input impedance = ∞

output impedance = 0

current gain =∞

power gain = ∞

+

–Ov

+ – IN

v

N Ovv ≈

Why is this circuit useful?




6.002 CIRCUITS AND

ELECTRONICS

Operational Amplifier Circuits




Operational amplifier abstraction

Building block for analog systems

We will see these examples:

Digital-to-analog convertersFilters

Clock generators

Amplifiers

Adders

Integrators & Differentiators

Reading: Chapter 16.5 & 16.6 of A & L.

+

–

Review

∞ input resistance

0 output resistance

Gain “ A” very large




Consider this circuit:

−

+

≈

+=

v

R Rvv

21

21

1

2

R

vvi

−−=

2iRvvOUT

−= −

2

1

2 R

R

vvv ⋅

−−=

−−

1

22

1

21 R

Rv

R

Rv −

+= −

1

22

1

21

21

21

Rv R R Rv −

+

⋅+=

( )21

1

2vv

R−=

subtracts!

+

–

2

+ –

1

+ –

1

2

+v

−

v

i

i

OUT v

+

–1v

2v




Another way of solving —use superposition

1

21

1

R

vvOUT

+⋅= +

1

21

21

21

R R R

v +⋅

+

⋅=

1

2

1 Rv=

2

1

22 v

RvOUT −=

+

–

21 ||

+ –

1

2

2OUT v2v

+

–+ –

1

2

1OUT v

1v

2

+v

1

21 OUT OUT OUT vvv +=

( )21

1

2vv

R−=

01→v 02

→v

Still subtracts!




Let’s build an intergrator…

dt iC

1v

t

O ∫ ∞−

=

Let’s start with the following insight:

vO

is related to dt i∫

I v

+

–O

v+ –

∫ dt

i + –

i

+

–

OvC

But we need to somehow convertvoltage v

I to current.




But, vO

must be very small compared

to v R, or else vi

I ≠

When is vO

small compared to v R

?

First try… use resistor

iv I →

O

Ov

dt

dv RC >>when

I

Ov

dt

dv RC ≈

dt v RC

1v

t

I O ∫ ∞−

≈or

I O

O

vvdt

dv

RC =+

v

larger the RC,smaller the v

O

for good

integratorω RC >> 1

I v +

–

i

+

–

OvC

v+ –

Demo




Now, let’s build a differentiator…

I v

+

–

Ov+

– dt d

But we need to somehow convert currentto voltage.

i is related todt

dv I

Let’s start with the following insights:

dt

dvC i

I =+

–

I v

i

C




Demo

C I vv =

dt

dvC i

I =

dt

dv RC v

I

O−=

Recall

+

–

i

i

currentto

voltage

iRvO

−=

V 0

+

–

+ –

v + – Ov

C

C v

i

Differentiator…

+

–i

+

–

R

vO




6.002 CIRCUITS AND

ELECTRONICS

Op Amps Positive Feedback




Consider this circuit — negative feedback

+

–

+ –

1 R

1 R

v IN

N v +

–IN OUT v

Rv

1

2−=

2

What’s the difference?

Consider what happens when there is a pertubation…Positive feedback drives op amp into saturation:

S OUT V v ±→

and this — positive feedback

+

–+ –

1 N v +

–

2

IN OUT v R

v1

2−=“ ”

s e e

a n a

l y s i s

o n n e x t

p a g

e

Negative vs Positive Feedback




+

–

+

–

1 R IN v

2 R

OUT v

)−+ −= vv AvOUT

+⋅+

−= IN 1

21

IN OUT v R R R

vv A

IN

21

IN 1OUT

21

1 Av R R

v ARv

R R

AR+

+−

+=

+= Av

IN

1

2 IN

21

1

21

1

OUT v R

R Av

R R

AR

R R

R1

v −=⋅

+−

+−

=

+−=

+−21

1 IN

21

1OUT R R

R1 Av R R

AR1v

+ –

1 IN v

2 OUT v+v

−v ( )−+ − vv A+ –

Static Analysis of Positive Feedback Ckt




Representing dynamics of op amp…

+v

−v

ov*v+

–

+

–

*v

)( −+ − vvC +

–




Representing dynamics of op amp…

Consider this circuit and let’s analyze itsdynamics to build insight.

+

–

1 2

ov

3 4

Let’s develop equation representing timebehavior of vo .

Circuit model

1

2

3 4

+

–

*v

)(−+ − vvC +

–

+ –

+

–ov

+v

−v

vo




vv Avv o

o == ** or

)γγ( A

C T where0

T

v

dt

dv oo

+−−==+or

oo v R R

vv +=

+=+

γ

21

1

oo v R R

vv

−=+

=−γ

43

3

0)γγ( =+

−−+ oo v

C dt

dv

1time−

0)γγ(1

=

+

−−++ oo v

RC RC dt

dvor

neglect

_ **

vvvdt

dv

RC −=+ +

ov)γγ(

−−+

=

Dynamics of op amp…

_ vvv

dt

dvC oo −=+ +

0 )0( vo =




Consider a small disturbance to vo

(noise).

Now, let’s build some useful circuits with

positive feedback.

+>−

γγif

stablee K v

positiveisT

T

t

o

−

=

−>+

γγif

unstablee K v

negativeisT

T

t

o =−=

+γγif

neutral K v

largeveryisT

o =

ov

t

neutral

stable

K

disturbance

unstable




One use for instability: Build on thebasic op amp as a comparator

+

–

+vov

S V +

S V −

−v

−+ − vv

ov

S V +

S V −

0

t 0v →−

+v

ov




Now, use positive feedback

+

–

2

ov

1

iv

21

1

R R

vv o

+

=+

5.7 v =+

5.7 v −=−

15vo =

15vo −=

15e.g. 21

==

S V

5.7 v

5.7 )vv( i

>

>=−

−

5.7−<

<−

+−

v

vv

iv



6.002 Fall 2000 Lecture 1021

Now, use positive feedback

+

–

2

ov

1

iv

21

1

R R

vv o

+

=+

21

1

R RV v S

+=+

21

1

R R

V v S

+

−=−

S o V v += 15

S o V v −= 15−

15e.g. 21

==

S V

5.7 v

v )vv( i

>

>=−

+−

5.7−<

<−

+−

v

vv

iv



6.002 Fall 2000 Lecture 1121

Why is hysteresis useful?e.g., analogto digital

ov

iv

S V

S V −

0 5.75.7−

15−

15

hysteresis

Demo

Demo

t

iv

5.7

5.7−

ov



6.002 Fall 2000 Lecture 1221

Without hysteresis

analogto digital

t

iv

5.7

5.7−

iv

ov



6.002 Fall 2000 Lecture 1321

Oscillator — can create a clock

Demo

+

–

C v

1

1

ov

2o

v

C

0

0at

=

==

C

S o

v

t V vAssume

t

S V

S V −

2S V

2

S V −

ov

+

v

+

v

−v

−vC v

−v

−vC v



6.002 Fall 2000 Lecture 1421

We built an oscillator using an op amp.

t

Why do we use a clock in a digital system?

(See page 735 of A & L)

sender receiver

1 1 0

a 1,1,0?

b When is the signal valid?

Discretization of timeone bit of information associated withan interval of time (cycle)

Clocks in Digital Systems

can use as a clock

common timebase -- when to “look” at a signal(e.g. whenever the clock is high)

clock




6.002 CIRCUITS AND

ELECTRONICS

Energy and Power




Why worry about energy?

small batteries

good

Today:

How long will the battery last?in standby modein active use

Will the chip overheat and self-destruct?

-




Look at energy dissipation in

MOSFET gates

Let us determinestandby poweractive use power

Let’s work out a few related examples first

C : wiring capacitance andC GS of following gate

V S

C

R

Ov

+

– I v+

–




Example 1:

Power

Energy dissipated in time T

R

V VI P

2

==

VIT E =

+ –

I

V

+

–V




Example 1:

for our gate

ON L

S

R R

V P +

=2

0= P

Ov

S V

ON

L

I v high

S V

ON

L

Ov

I v low




Example 2:

Consider

Find energy dissipated in each cycle.

Find average power . P

S V + –

1

C 2

1S 2S

openS

closed S

2

1

t

closed S

openS

2

1

1T 2T

T




T 1 : S 1 closed, S 2 open

t

C v

S V C R

t

1

S 1e R

V −

t

i

1

S

R

V

+

–C v

+ –

1

C S V

i assumevC = 0 at t = 0




Total energy provided by source during T 1

dt iV E

1T

0S

∫ =

dt e R

V C R

t T

0 1

2

S 1

1−

∫ =

1

1

T

0

C Rt

1

1

2S eC R

R

V −

−=

−=

−

C R

T

2

S 1

1

e1V C

1

2

S 1

2

S

Rindissipated V C 2

1 E

,C on stored V C 21

=

C RT if V C 11

2

S >>≈I.e., if we wait long enough

Independenof R!




T 2 : S 2 closed, S 1 open

+

–C v

2C

So, initially,

2

S CV 2

1=energy stored in capacitor

Assume T 2 >> R2C

So, capacitor discharges ~fully in T 2

So, energy dissipated in R2 during T 2

2

S 2 CV 2

1 E =

E 1, E 2 independent of R2 !

Initially, vC = V S (recall T 1 >> R1C )



6.002 Fall 2000 Lecture 1022

Putting the two together:

Energy dissipated in each cycle

2

S

2

S CV 2

1CV

2

1+=

21 E E E +=

C g dischargin&charging indissipated energyCV E

2

S =

Assumes C charges and discharges fully.

frequency

T

f 1

=

T P =

T

CV S

2

=

f CV S 2=

Average power



6.002 Fall 2000 Lecture 1122

Back to our inverter —

Ov

N v C

S V

L

ON

t

2

T

T

2

T

IN v

f T 1=

What is for the following input? P



6.002 Fall 2000 Lecture 1222

Equivalent Circuit

S V + –

L

C

ON

t

2

T

T

2

T

IN v

f T

1

=

What is for the following input? P



6.002 Fall 2000 Lecture 1322

We can show (see section 12.2 of A & L)

( ) ( )2ON L

2 L2

S

ON L

2S

R R

R f CV

R R2

V P

++

+=

f CV R2

V P

2

S

L

2S +=

when R L >> RON

What is for gate? P

r e m e

m b e r

r e m e m

b e r

STATIC P DYNAMIC P

related to switchingcapacitor

independent of f.MOSFET ON half

the time.



6.002 Fall 2000 Lecture 1422

f CV RV P S

L

S 2

2

2 +=

when R L >> RON

In standby mode,half the gates in achip can be

assumed to be on.So pergate is still .

Relates to standbypower.

STATIC

L

2

S

R2

V

What is for gate? P

In standby mode,

f 0 ,so dynamic poweris 0



6.002 Fall 2000 Lecture 1522

Some numbers…

a chip with 106 gates clocking

at 100 MHZ

V 5V

10100 f

k 10 R

F f 1C

S

6

L

=

×=

Ω==

×××+×

= − 6 15

4

6 101002510102

2510 P

[ ]microwatts5.2milliwatts25.1106 +=

problem!1.25KW! 2.5W

not bad

mW 150W 5.2

V 1V 5

V reduce

f

V

S

2

S

→

→

α

α

nextlecture

must get rid of this




6.002 CIRCUITS AND

ELECTRONICS

Energy, CMOS




Reading: Section 12.5 of A & L.

S V + –

1

C 2

1S 2S

f T T T

121=+=

f CV P S

2=

T 1: closed

T 2: open

open

closed

ON L

S

R R

V P

+=

2

Ov

S V

ON

L

I v

Review




Inverter —

Ov

I v C

S V

L

ON

f CV R

V P S

L

S 22

2+=

related to switchingcapacitor.

independent of f.MOSFET ON half

the time.

STATIC P DYNAMIC P

constant time

" RC " 2

T

ON L

>>

>>Square wave input f

T 1=

Demo

Review

In standby mode, halfthe gates in a chip canbe assumed to be on.So per gate isstill .

STATIC

L

2

S

R2

V

In standby mode,

f 0 ,so dynamic power is 0




f CV R

V P S

L

S 22

2+=

Chip with 106 gates clocking at 100 MHz

V 5V ,10100 f , K 10 R F, f 1C S

6

L =×=Ω==

problem!

1.25KWatts 2.5Watts

not bad

+

• independent of f

• also standby power(assume ½ MOSFETs

ON if f 0)• must get rid of this!

• α f • αV S

2

reduce V S

5V 1V 2.5V 150mW

[ ]watts5.2milliwatts25.1106 µ +=

×××+

××

= − 6 215

3

26 10100510

10102

510 P

gates

Review




How to get rid of static power

Intuition:

Ov

S V

ON

L

v high low

i

idea!

Ov

S V

v high low

S V

L

Ov

I v low

off MOSFET

high




New Device PFET

• N-channel MOSFET (NFET)

D

S

Gon when vGS ≥ V TN

off when vGS < V TN

e.g. V TN = 1V

• P-channel MOSFET (PFET)

on when vGS ≤ V TP

off when vGS > V TP

e.g. V TP = -1V

S

D

G

ON when

less than 4V

5V





S

DG

D

S G

Ovv+

–

S V

PU = pull up

PD = pull down

works like an inverter!

IN OUT





v I = 0V (input low)

V5

vO

=

V 5V S =

V 0v I =+

–

pON

v I = 5V (input high)

V 0

vO

=

V 5V S =

V 5v I =+

– nON

Called “CMOS logic” ComplementaryMOS

(our previous logic was called “NMOS”)

works like an inverter!

IN OUT




O

v I v

S V

C t

T

I v

T f

1=

From f CV P S

2=

Key: no path from V S to GND!no static power!

Let’s compute DYNAMIC P

S V + –

pON

C nON

closed for

v I low

closed for

v I high



6.002 Fall 2000 Lecture 1023

For our previous example —

1 , Hz 100 f ,V 5V F, f 1C S ===

“keep

allelse

same”

f CV P S

2=

6 215 10100510 ×××= −

gate per µwatts5.2=

chipgate10for µwatts5.2 6= P

PIII?~240watts1.2 GHz8x106

PIV?~1875watts3 GHz25x106

PII?

~30

watts

600

MHz2x106

PII?~15

watts300

MHz2x106

Pentium?~2.5

watts100

MHz106

f Gates

g a s p !



6.002 Fall 2000 Lecture 1123

and use big heatsink

How to reduce power

A V S 5V 3V 1.8V 1.5V

~PIV 170 watts better, but high

next time:power supply

B Turn off clock when not in use.C Change V S depending on need.



6.002 Fall 2000 Lecture 1223

CMOS Logic

NAND:

Z A B

0 0 1

0 1 1

1 0 1

1 1 0

S

DG

V0 on

V5

S

DG

V5 off

V5

S V

B

B

Z



6.002 Fall 2000 Lecture 1323

B A B A F +=⋅=e.g.

In general, if we want to implement F

short when A = 0 or B = 0,open otherwise

short when A · B is true,else open

B

shortwhen F is true,else open

S V

Z

shortwhen F is true,else open

r e m e m b e r

D eM o r g a n ’ s

l a w




6.002 CIRCUITS AND

ELECTRONICS

Power Conversion Circuits

and Diodes




Power Conversion Circuits (PCC)

Power efficiency of converter important,so use lots of devices:

MOSFET switches, clock circuits,inductors, capacitors, op amps, diodes

Reading: Chapter 17 of A & L.

PCC110V60Hz

+

–5V DC

solar cells,battery PCC +

–5V DC

3VDC

DC-to-DC UP converter

R




First, let’s look at the diode

Can use this exponential model withanalysis methods learned earlier

analytical graphical incremental

(Our fake expodweeb was modeled after this device!)

Dv

Di

Dv

Di

S − mV V

Dv

+

–

Di

−= 1e I i T

D

V

v

S D

A10 I 12

S

−=

V 025.0V T =

qT k V T =

Boltzmann’s constant

temperature in Kelvinscharge of an electron




Another analysis method:piecewise–linear analysis

P–L diode models:

Dv

Di

0

Ideal diode model

i D = 0

“open”or

off

v D < 0

v D = 0

“short”or on

i D ≥ 0




Dv

Di

V 6 .0

0v D =

0i D =

“Practical” diode modelideal with offset

V 6 .0

+ –


Open segment

Short segment





Replace nonlinear characteristic with

linear segments. Perform linear analysis within each

segment.

Piecewise–linear analysis method




(We will build up towards an AC-to-DC converter)

Ov

+

–

+ –

v

V6.0

+ –

Example

Consider

v I is a sine wave




0vO =

0i D =

“Open segment”:

+ –

v

+

–

+ –

V 6 .0

6 .0v I <

Ov

+

–

+ – I v

( ) R / 6 .0vi I D −=

6 .0vv I O −=

“Short segment”:

+ –

+

–

+ –

V 6 .0

6 .0v I ≥ v

ExampleV 6 .0

+ – Equivalentcircuit




Example

t

6 .0

I v

Ov



6.002 Fall 2000 Lecture 1024

Now consider — a half-wave rectifier

I vOv

+

–

+ –

V6.0

+ –

C



6.002 Fall 2000 Lecture 1124

A half-wave rectifier

t

diode on diode off

C

currentpulseschargingcapacitor

MIT’s supply shows“snipping” at the peaks(because current drawnat the peaks)

I v

Ov

Demo



6.002 Fall 2000 Lecture 1224

DC-to-DC UP Converter

The circuit has 3 states:

I. S is on, diode is offi increases linearly

II. S turns off, diode turns onC charges up, vO increases

III. S is off, diode turns offC holds vO (discharges into load)

t

S v

S closed

S open

T pT

Ov+

–

+ –DC

I V C

S v load

i

switchS

Do no t use

resis ti ve

e lemen ts !



6.002 Fall 2000 Lecture 1324

More detailed analysis

I. Assume i(0) = 0, vO(0) > 0

S on at t = 0, diode off

+ – I V C

i

LOv

t

i

L

T V T i I =)(

T

dt

di LV I =

i is a ramp L

V I

=slope

2 )T ( Li21:T t at stored energy E ==∆

L

T V E I

2

22

=∆



6.002 Fall 2000 Lecture 1424

II. S turns off at t = T

diode turns on (ignore diode voltage drop)

+ –

V C

LOv

S i

Diode turns off at T ′ when i tries to go negative.

t

i

T 0

L

T V I

LC O

1=ω

T ′ P T

State III starts here



6.002 Fall 2000 Lecture 1624

II. S turns off at t = T, diode turns on

Diode turns off at T ′ when I tries to go negative.

LC O

1=ω

ignorediodedrop

)(T vO

Ov

T ′t

T 0

Capacitor voltage

P T

Ov∆

t

i

T

0

L

T V I

T ′ P T

LC O

1=ω

III.

Let’s look at the voltage profile



6.002 Fall 2000 Lecture 1724

III. S is off, diode turns off

C holds vO after T ′

i is zero

+ – I V C S

Ov+

–

Eg, no load

Ov

T ′t 0

Capacitor voltage

P T



6.002 Fall 2000 Lecture 1824

III. S is off, diode turns off

C holds vO after T ′

i is zero

until S turns ON at T P , and cycle repeatsI II III I II III …

Thus, vO increases each cycle, if there is no load.

t

Ov

)(nvO

P T 2 P T 3

+ – I V C S

Ov+

–

Eg, no load

P T



6.002 Fall 2000 Lecture 1924

What is vO after n cycles vO(n) ?

Use energy argument … (KVL tedious!)

Each cycle deposits∆

E in capacitor.2 )T t ( i L

2

1 E ==∆

2

I

L

T V L

2

1

= L

T V

2

1 E

22

I =∆

After n cycles, energy on capacitor

L2

T nV E n

22

I =∆

This energy must equal 2

O )n( Cv2

1

or LC

T nV )n( v

22

I O =

LC

1O =ω

nT V )n( v OO ω =

so, L2

T nV )n( Cv

2

1 22

I 2

O =



6.002 Fall 2000 Lecture 2024

How to maintain vO

at a given value?

recall L

T V E I

2

22

=∆

Another example of negative feedback:

( ) ↑↓−

↓↑−

T vv

T vv

ref O

ref O

thenif

thenif

Ov

+

–

+ – I V load

control

change T T

pT

pwm

+ ref v

compare

–

Ov




6.002 CIRCUITS AND

ELECTRONICS

Violating the Abstraction Barrier




Case 1: The Double Take

Problem

iV

OV

“0” “1”

t

OV

“0”

“1” OV

“0”

“1”

observedexpected

in forbidden region!

huh?




(a) DC case

iV

OV

1V

very high

impedancelike opencircuit

OK DC V 5V i= DC V 5V

O= DC V 5V

1=




t

V5.2=O

V

t

iV

(b) Step

not ok!

t

1V

looks ok!

b.1

b.3

b.2

V0

V5

0=t

0=t

0=t T

T 2

V5

V5

iV

OV

1V

very highimpedancelike opencircuit

OV




iV

. . . .

instantaneous R dividerfinite propagation speedof signals

characteristicimpedance

→

T 2 T

5

2.5

0

V5

0

V5

0

V5




Question: So why did our circuits work?

More in 6.014

t

V5

V5.2

3. Termination

P a r a l l e l

t e r m i n a t i

o n

D E M O

a d d R a

t t h e

e n d

0

V O

2. Keep wires short

t

V5

00

V O

D E M O

u s e s m a

l l w i r e

“S o u rc e

T e r m i n a t i o n ”1. Look only at V

1

t 0 T

V5

0

V 1

D E M O




Case 2: The Double DipProblem strange spikes on supply

driving a 50 Ωresistor!

V

0 1

01

OK

Why?

input

driving a 50 Ωresistor!

V

0




V

dt

Ldi

Drop across inductor

Inverter current

v inductor

solution 1. short wires2. low inductance wires3. avoid big current swings

V S

V S




Case 3: The Double Team, or,Slower may be faster!Problem

a given chipworked,but was slow.

Let’s try speeding it up by using stronger

drivers

actual

ideal

ideal

C

Disaster!

L

ω

actual



6.002 Fall 2000 Lecture 1025

Why?Consider

crosstalk!

1

0

DEMO

2

C

dt

dV α

DEMO

ok

dt dV C



6.002 Fall 2000 Lecture 1125

How does this relate to chip?

Load output! — put cap on outputs of chip— jitter edges— slew edges

dt

dV small

DEMOSolution



Case 4: The Double JumpCareful abstraction violation for thebetter…

Recall

oV

iV

oV

iV

expect

but, observe

circuits and elektroniks

Documents