Chris Parkes for VELO software Group

VELO Software Overview &Shutdown Planning

•Organisation

•Milestones

•3 Critical Areas

2

Areas & Responsibilities• Overall Co-ord: CP

• PVSS: Stefano De Capua • DAQ Recipes: Karol Hennessy

• Timing & Gain: Kazu Akiba

• Error Bank Analyses: Ann van Lysebetten • Online Monitoring: Kurt Rinnert • Data Quality: Eduardo Rodrigues

• Simulation & Reconstruction: Tomasz Szumlak

• Tracking: David Hutchcroft

• Alignment: Silvia Borghi

• Closing Strategy: Malcolm John

• > 20 people contributing• Milestones defined for each, with one person

responsible and priorities assigned

3

Organisation• Weekly Monday commissioning meeting

– Report on previous week milestones– News from all, forum for discussing issues– Work plans for the week

• Integration Days: Thursdays– Integrate weekly releases (if any) at pit– Release: PVSS, recipes, Vetra

• Brief report bi-weekly Friday meeting– Report progress to whole group, no details– Specific presentations on items of general interest

• Shutdown progress logged on milestone Twiki pagehttps://lbtwiki/bin/view/VELO/SoftwareMilestones

4

Milestone Progress

•Proceeding close to schedule•Some delays due to FEST’08 production

VELO Shutdown Software Milestones

0

5

10

15

20

25

30

35

40

45

09/09/2008 29/10/2008 18/12/2008 06/02/2009 28/03/2009 17/05/2009

Date

Mile

sto

ne

Nu

mb

er

Expected

Achieved

5

Critical Path

• In September identified three key areas where progress is needed before we start running this year

– Timing

– TELL1 Parameter Uploading

– Monitoring

6

Timing studies• Set up timing for sampling of pulse

train and for optimal analogue signal height

• Automated timing scans implemented and being tested

• Firmware release being tested

7

Digitisation Delay

Time (CLK/channels)

AD

C C

ount

s

3 4 65

Delayed pulse

Measured VoltageARx Clock

Delayed Sampling phase

8

AD

C C

ount

s

25 50 10075

First Time Sample

SecondTime Sample

ThirdTime Sample

FourthTime Sample

...

Scan Points

Delayed pulse

Sampled pointsfor a given clock

Beetle Clock

Analogue Sampling Delay

Time (ns)

9

TELL1 Data Processing

• Velo Data Processing Raw -> Clusters in TELL1

Pedestal Following

Common Mode Suppression (MCMS)Beetle baseline shift

Reordering

Common Mode Suppression (LCMS)Clusterization

Beetle Cross-talk Correction

Cable Cross-talk Filter (FIR)

•Require 1M parameters

•Optimisation critical for data quality (see TED data talk)

• Pedestal & Clusterisation Thresholds most important

•Bit Perfect Emulation of Algorithms in full LHCb Software Framework

Lowerpriority

Lowerpriority

RAW

CLUSTERS

10

Vetra – TELL1 Emulation

•Parameter uploading achieved for first time in December•Firmware fixes made and used (November)•Testing & evaluation underway

11

Pedestal Processing

Raw data Pedestal corrected data

Pedestal correction monitoringBase line (zero)

level after pedestal correction

12

Beetle X-talk effect first channel in each analog link is affected

Noise after pedestal correction

Beetle X-talk correction monitoring

Measured noise in first channel before correction

Noise in first channel after correction

Average noise measured in unafected channel

Beetle X-talk correction

13

ADC count

Constant Pedestal OnlyADC count

All Parameters tuned

Effect of tuning

Non-Zero Suppressed Data critical– so that tuning parameters can be obtainedProcedure to take automatically during data

- One module at a time, under test

14

Monitoring• Monitoring package

– Package for “high-level” (= ZS) data• Monitoring based on clusters and tracks

– Package for NZS data• Noise calculation, time alignment study, beetle pulse shape, …

• Scripts and macros are being developed to analyse data

• Wiki pages with documentation and HowTo’s

Review of Monitoring status in February

15

Online monitoring• Running since August• Implementation of several plots• New features to be exploited

Online presenterOnline presenter

16

Cluster Monitoring• Cluster information:

– Cluster ADC value– Active chip links– Number of strip in a cluster– Cluster ADC value versus sampling– Number of cluster per events– More…

Some of these distributions versus sensor number and/or sensor strip

17

Example distributions from VeloRecMonitors

18

Track Monitoring• Tracks

– Number tracks– Pseudo-rapidity – Azimuthal Angle – Pseudo-efficiency – Biased and unbiased Residuals versus

sensor number– Total number of R cluster per track– Vertex information– Hits distribution in xy and xz– Mean sigma of residuals versus of

sensors– More…

19

Track monitoring: J/() Ks B

iase

dR

es

R Sensor #

Pseudo rapidity Azimuthal angle

X(c

m)

Z(mm)

20

Script and Macros

• Analysis of the data for the evaluation for:– Time alignment study,– Noise calculation, – High voltage scan, – beetle pulse shape,– More…

21

Noise monitoring macros – example of GUI

22

Noise monitoring macros – example of GUI

Common mode subtractionNo common mode

23

Noise performance

Common Mode Subtracted Noise of Each Run

Run Time11/10/06 11/12/06 11/14/06 11/16/06 11/18/06 11/20/06

Ave

rag

e N

ois

e

0

1

2

3

4

R DetectorsPhi Detectors

HP1 HP2 HP3 HP4

•Common mode pickup from beam requires data•At pit and in previous testbeams parameters highly stable

24

Noise – individual / whole system

No evidence that operation of full system induces more noise than single sensors

25

Noise versus VoltageE

xpec

ted

Sig

nal /

Noi

se

26

IV - scans• PVSS recipes available to automate IV scans

• Set initial voltage, target voltage, step, single or set of sensors

• A data file produced per sensor containing channel number, voltage, current, sensor temperature

• Analysis scripts for plotting IV scan data

27

Software Commissioning Summary • All baseline algorithms

– Completed for summer ’08

• Commissioning software – Milestones for data readiness in April 2009– 3 critical areas all proceeding according to plan

• TED data are the VELO ‘cosmics’Tremendous success of first tracksThis sample has been very useful for comissioningTED data this summer will allow us to:

Optimise timingTest and tune FPGA algorithmsIncrease alignment accuracy