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Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-1

Chapter 9: Sequential Logic Modules

Department of Electronic Engineering

National Taiwan University of Science and Technology

Prof. Ming-Bo Lin

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-2

Syllabus

ObjectivesFundamentals of sequential logic modulesFlip-flopsMemory elementsShift registersCountersSequence generatorsTiming generators

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-3

ObjectivesAfter completing this chapter, you will be able to:

Describe how to model asynchronous and synchronous D-type flip-flopsDescribe how to model registers (data register, register file, and synchronous RAM)Describe how to model shift registers Describe how to model counters (ripple/synchronous counters and modulo r counters)Describe how to model sequence generatorsDescribe how to model timing generators

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-4

Syllabus

ObjectivesFundamentals of sequential logic modulesFlip-flopsMemory elementsShift registersCountersSequence generatorsTiming generators

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-5

Basic Sequential Logic Modules

Synchronizer Finite state machine Sequence detectorData registerShift register CRC generator Register file Counters (binary, BCD, Johnson)Timing generatorClock generatorPulse generator

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-6

Options for Modeling Sequential Logic

Behavioral statementTask with delay or event controlSequential UDPInstantiated library register cellInstantiated modules

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-7

Syllabus

ObjectivesFundamentals of sequential logic modulesFlip-flopsMemory elementsShift registersCountersSequence generatorsTiming generators

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-8

Asynchronous Reset D-Type Flip-Flops

// asynchronous reset D-type flip-flopmodule DFF_async_reset (clk, reset_n, d, q);output reg q;

always @(posedge clk or negedge reset_n)if (!reset_n) q

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-9

Synchronous Reset D-Type Flip-Flops

// synchronous reset D-type flip-flopmodule DFF_sync_reset (clk, reset, d, q);output reg q;

always @(posedge clk)if (reset) q

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-10

Syllabus

ObjectivesFundamentals of sequential logic modulesFlip-flopsMemory elementsShift registersCountersSequence generatorsTiming generators

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-11

Types of Memory Elements

Data registersRegister filesSynchronous RAMs

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-12

Registers

Registers (or data registers) A flip-flop

Area: 10 to 20x of an SRAM cellIn Xilinx FPGAs

Flip-flopsDistributed memoryBlock memory

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-13

Data Registers

// an n-bit data registermodule register(clk, din, qout);parameter N = 4; // number of bitsinput [N-1:0] din;output reg [N-1:0] qout;

always @(posedge clk) qout

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-14

Data Registers

// an n-bit data register with asynchronous resetmodule register_reset (clk, reset_n, din, qout);parameter N = 4; // number of bitsinput [N-1:0] din;output reg [N-1:0] qout;always @(posedge clk or negedge reset_n)

if (!reset_n) qout

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-15

Data Registers

// an N-bit data register with synchronous load and // asynchronous resetparameter N = 4; // number of bitsinput clk, load, reset_n; input [N-1:0] din;output reg [N-1:0] qout;

always @(posedge clk or negedge reset_n)if (!reset_n) qout

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-16

A Register File

// an N-word register file with one-write and two-read portsparameter M = 4; // number of address bitsparameter N = 16; // number of words, N = 2**Mparameter W = 8; // number of bits in a wordinput clk, wr_enable;input [W-1:0] din;output [W-1:0] douta, doutb;input [M-1:0] rd_addra, rd_addrb, wr_addr;reg [W-1:0] reg_file [N-1:0];assign douta = reg_file[rd_addra],

doutb = reg_file[rd_addrb];always @(posedge clk)

if (wr_enable) reg_file[wr_addr]

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-17

An Synchronous RAM

// a synchronous RAM module exampleparameter N = 16; // number of wordsparameter A = 4; // number of address bitsparameter W = 4; // number of wordsize in bitsinput [A-1:0] addr;input [W-1:0] din;input cs, wr, clk; // chip select, read-write control, and clock signalsoutput reg [W-1:0] dout;reg [W-1:0] ram [N-1:0]; // declare an N * W memory array

always @(posedge clk)if (cs) if (wr) ram[addr]

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-18

Syllabus

ObjectivesFundamentals of sequential logic modulesFlip-flopsMemory elementsShift registersCountersSequence generatorsTiming generators

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-19

Shift Registers

Shift registers Parallel/serial format conversion

SISO (serial in serial out)SIPO (serial in parallel out)PISO (parallel in serial out)PIPO (parallel in parallel out)

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-20

Shift Registers

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-21

Shift Registers

// a shift register module examplemodule shift_register(clk, reset_n, din, qout);Parameter N = 4; // number of bits.output reg [N-1:0] qout;

always @(posedge clk or negedge reset_n)if (!reset_n) qout

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-22

A Shift Register with Parallel Load

// a shift register with parallel load module examplemodule shift_register_parallel_load

(clk, load, reset_n, din, sin, qout);parameter N = 8; // number of bits.input [N-1:0] din; output reg [N-1:0] qout;

always @(posedge clk or negedge reset_n)if (!reset_n) qout

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-23

Universal Shift Registers

A universal shift register can carry out SISOSIPOPISOPIPO

The register must have the following capabilitiesParallel loadSerial in and serial outShift left and shift right

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-24

Universal Shift Registers

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-25

Universal Shift Registers

// a universal shift register modulemodule universal_shift_register (clk, reset_n, s1, s0, );parameter N = 4; // define the default size always @(posedge clk or negedge reset_n)

if (!reset_n) qout

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-26

Syllabus

ObjectivesFundamentals of sequential logic modulesFlip-flopsMemory elementsShift registersCountersSequence generatorsTiming generators

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-27

Counters

Counter Types

CountersTimers

Chapter 9: Sequential Logic Modules

Digital System Designs and Practices Using Verilog HDL and FPGAs @ 2008~2010, John Wiley 9-28

Types of Counters

Types of countersAsynchronousSynchronous

Asynchronous (ripple) countersBinary counter (up/down counters)

Synchronous countersB

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