chapter 6 (ii) - 國立臺灣大學access.ee.ntu.edu.tw/course/vlsi_design_92first/ppt/chapter6-2...

EE1411

Combinational Circuits

Chapter 6 (II)Chapter 6 (II)Designing Designing CombinationalCombinationalLogic Circuits (II)Logic Circuits (II)

••Dynamic CMOS LogicDynamic CMOS Logic

V1.0 5/4/2003V1.2 5/15/2003V2.0 12/16/2003

EE1412


Revision ChronicleRevision Chronicle5/4:

Split Chapter 6 into two parts: Part I focuses on Static and Pass Transistor Logic. Part II focuses on Dynamic Logic

5/11: Make minor revision in figures and adding the summary

5/11: Make minor revision in figures and equations

12/17: Scan new figures and explain more details

EE1413


Dynamic CMOSDynamic CMOSIn Static CMOS circuits, at every point in time (except when switching), the output is connected to either GND or VDD via a low resistance path.

Fan-in of n requires 2n (n NMOS plus n PMOS) devices

Dynamic CMOS circuits rely on the temporary storage of signal values on the capacitance of high impedance nodes.

Requires on (n + 2) transistors (n+1 NMOS plus 1 PMOS) transistors

EE1414


Basic Dynamic GateBasic Dynamic Gate

In1

In2 PDNIn3

Me

Mp

Clk

ClkOut

CL

Out

Clk

Clk

A

BC

Me

Mp

PDN

EE1415


Two Phase OperationsTwo Phase Operations

In1

In2 PDNIn3

MeClk

ClkOut

CL

Out

Clk

Clk

A

BC

Me

Precharge (Clk = 0)Evaluate (Clk = 1)

on

off

1off

on

AB+C

MpMp

CLKCBACLKOut ⋅+⋅+= )(

EE1416


Example: Dynamic NOR2 GateExample: Dynamic NOR2 Gate

EE1417


Transient Response of NAND4 GateTransient Response of NAND4 Gate

EE1418


Conditions on OutputConditions on Output

Once the output of a dynamic gate is discharged, it cannot be charged again until the next prechargeoperation (one chance only).Inputs to the gate can make at most one transitionduring evaluation.Output can be in the high impedance state during the evaluation phase (PDN off), state is stored on CL

Different from Static CMOS Output is connected toEither Vdd or GND through low-resistance path.

EE1419


Properties of Dynamic Gates (I)Properties of Dynamic Gates (I)Logic function is implemented by the PDN only

Number of transistors is n + 2 (versus 2n for static complementary CMOS)

Full swing outputs (VOL = GND and VOH = VDD)Non-ratioed: Sizing of the devices does not affect the logic levels (c.f., Pseudo NMOS)Faster switching speeds:

Reduced load capacitance due to reduced Logical Effort of next stage (Cin is reduced from 2n to (n+2) )Reduced load capacitance due to smaller internal capacitance (less PMOS Network)No short-circuit current, Isc

EE14110


Properties of Dynamic Gates (II)Properties of Dynamic Gates (II)Power Dissipation

No static current path ever exists between VDD and GND (including Psc)No glitchingHigher transition probabilities: due to dynamic behaviorExtra loading on CLK circuits (clock tree)Overall power dissipation is usually higher than static CMOS

PDN starts to work as soon as the input signals exceed VTn, so VM, VIH and VIL are equal to VTn

Low noise margin (NML)Needs a precharge/evaluate clock (CLK)tPLH = 0, tPHL = Function of CL and PDN

10→P

EE14111


Issues in Dynamic Design 1: Issues in Dynamic Design 1: Charge LeakageCharge Leakage

(1) and (3): Reversed-biased diode (2) and (4): Subthreshold leakage current (dominated)

EE14112


Charge LeakageCharge Leakage

•Need minimum clock rate up to a few kHz•Not good for low-performance applications suchas watches, etc.

EE14113


•Adding Bleeder Transistor: Same approach as level restorer transistors for pass-transistor logic.•The Bleeder resistance is made high (device is small) to avoid ratio problem and static power consumption•A “feedback” configuration can be used to elimaite static power consumption

Solution to Charge LeakageSolution to Charge Leakage

EE14114


Issues in Dynamic Design 2: Issues in Dynamic Design 2: Charge SharingCharge Sharing

• PDN is not fully turned ON along the path

• Charge stored originally on CL is redistributed (shared) over CL and CA

• Lead to a voltage drop on the output voltage

• May cause incorrect output (e.g., the next stage is a Inverter gate).

B= 0

Clk

X

CL

Ca

Cb

A

OutMp

Ma

VDD

Mb

Clk Me

outV∆

EE14115


Charge SharingCharge Sharing

CLVDD CLVout t( ) Ca VDD VTn VX( )–( )+=

or

∆Vout Vout t( ) VDD–CaCL-------- VDD VTn VX( )–( )–= =

∆Vout VDDCa

Ca CL+----------------------

–=

case 1) if ∆Vout < VTn

case 2) if ∆Vout > VTn

B = 0

Clk

X

CL

Ca

Cb

A

Out

Mp

Ma

VDD

Mb

Clk Me

))(( XTnDDX VVVV −=

)( XOUT VV =

0)0(,)0( :Initial ==== tVVtV XDDOUT

)when ( TnOUTTnDD

Tn

L

a VVVV

VCC

=∆−

=

Boundary Condition:

pTout VV ,<∆⇒ : avoid turn-on of next-stage inverter

EE14116


Example of Charge Sharing (I)Example of Charge Sharing (I)

V

VV

56.194.05.2

94.05.2)5030(

30

=−

=×+

: Switching voltage of Inverter

0 at time0====⊕⊕=

dcba VVVVCBAY

One worst case:

101=CBA

EE14117


Example of Charge Sharing (II)Example of Charge Sharing (II)

1

721

51

0

72

Cin QCC into dumped is Cin Q

1clkwhen −

==

==−

− highAlowA

lowCC

!!inverter ontheTurn

65.133.036

3Vthen

&3C IF

)(

22

2n1

76543221

1

7

2

11

⇒

==⋅+

=

=====×=

+

⋅=

∑=

VVVCC

C

CCCCCCC

CC

VCV

DDDD

ii

DDn example) in this 5( VVDD =

EE14118


Solution to Charge RedistributionSolution to Charge Redistribution

Clk

Clk

Me

Mp

A

B

OutMbI

Clk

• Precharge critical internal nodes using a clock-driven PMOS transistor (at the cost of increased area and capacitance).

• Hence, all internal nodes are charged to Vdd during pre-charge No charge sharing occurs.

EE14119


Issues in Dynamic Design 3: Issues in Dynamic Design 3: Backgate Backgate (output(output--toto--input) Couplinginput) Coupling

Dynamic NAND2 Static NAND2

EE14120


BackgateBackgate Coupling EffectCoupling Effect

-1

0

1

2

3

0 2 4 6

Vol

tage

Time, ns

Clk

In

Out1

Out2

Clock feedthrough

• Voltage drop is too large Incorrect evaluation• Output of static NAND gate does not drop all the way

down to 0V with the degraded Out1 static power• Need to minimize capacitive coupling in layout

Backgate coupling

EE14121


Issues in Dynamic Design 4: Clock Issues in Dynamic Design 4: Clock FeedthroughFeedthrough

CL

Clk

Clk

B

AOut

Mp

Me

Coupling between Out and Clkinput of the precharge device due to the gate-to-drain capacitance. The voltage of Out can rise above VDD or below GNDFast rising (and falling edges) of the clock couple to Out.May cause Latch-up!

EE14122


Problem in Cascading Dynamic GatesProblem in Cascading Dynamic Gates

Clk

Clk

Out1In

Mp

Me

Mp

Me

Clk

Clk

Out2

V

t

Clk

In

Out1

Out2 ∆V

VTn

Only ONE 0 → 1 transition allowed at inputs during Evaluation Phase

???

EE14123


Domino LogicDomino Logic

In1

In2 PDNIn3

Me

Mp

Clk

Clk Out1

In4 PDNIn5

Me

Mp

Clk

ClkOut2

Mkp

1 → 11 → 0

0 → 00 → 1

Combat leakage &Charge sharing!

EE14124


Why the Name Why the Name ““DominoDomino””??

Clk

Clk

Ini PDNInj

IniInj

PDN Ini PDNInj

Ini PDNInj

Like falling dominos!

EE14125


Properties of Domino LogicProperties of Domino Logic

Only non-inverting logic can be implemented!

Very high speedtpHL=0. Inverter can be sized to match Fan-out.Input capacitance is reduced to one inverter

smaller logical effort

EE14126


Restructuring Logic for Domino CircuitsRestructuring Logic for Domino Circuits

Use simple Boolean Transform such as DeMorgan’s Law!

EE14127


MultipleMultiple--output Domino Circuitsoutput Domino Circuits

Function of

O3 = (C+D)

can be reused!

EE14128


Compound Domino Logic uses Complex Compound Domino Logic uses Complex Static Gates at the OutputStatic Gates at the Output

GHABCDEFOOO+=⋅+= 3)21(

Avoid Charge-sharing!

EE14129


Designing with Domino LogicDesigning with Domino Logic

Mp

Me

VDD

PDN

Clk

In1In2In3

Out1

Clk

Mp

Me

VDD

PDN

Clk

In4

Clk

Out2

Mr

VDD

Inputs = 0during precharge

Can be eliminated!

EE14130


Footless DominoFootless Domino

The first gate in the chain needs a foot switchPrecharge is rippling – short-circuit currentA solution is to delay the clock for each stage

VDD

Clk MpOut1

In1

1 0

VDD

Clk MpOut2

In2

VDD

Clk MpOutn

InnIn3

1 0

0 1 0 1 0 1

1 0 1 0

EE14131


Differential (Dual Rail) Domino Logic GateDifferential (Dual Rail) Domino Logic Gate

Solve the problem of non-inverting logic

EE14132


npnp--CMOSCMOS

In1

In2NMOSPDN

In3

Me

Mp

Clk

Clk Out1

In4PMOSPUNIn5

Me

MpClk

Clk

Out2(to PDN)

1 → 11 → 0

0 → 00 → 1

Only 0 → 1 transitions allowed at inputs of PDN Only 1 → 0 transitions allowed at inputs of PUN

EE14133


NORA Logic NORA Logic (np(np--CMOS) for MultiCMOS) for Multi--stage stage FunctionsFunctions

EE14134


Summary of Dynamic CMOSSummary of Dynamic CMOSDynamic circuits should be designed with care (watch out charge sharing, feedthrough, backgate, etc.)It has smaller footprint and higher speed, but may not be best for low-power designs.The current trend is towards an increased use of complementary static CMOSDesign Automation Tools: Optimization at the logic level, rather at the circuit level.

chapter 6 (ii) - 國立臺灣大學access.ee.ntu.edu.tw/course/vlsi_design_92first/ppt/chapter6-2...

Documents