Chapter 6 ARM Instruction Set

Hsung-Pin ChangDepartment of Computer ScienceNational Chung Hsing University

Outlineo Data Processing Instructionso Branch Instructionso Load-store instructionso Software interrupt instructionso Program status register instructionso Conditional Execution

ARM Instruction Set Format

6.1 Data Processing Instructionso Manipulate data within registerso Data processing instructionsn Move instructionsn Arithmetic instructionsn Logical instructionsn Comparison instructionsn Multiply instructions

6.1.1 Move Instructiono Syntax: <instruction> {<cond>} {S} Rd, Nn N: a register or immediate value

o MOV : moven MOV r0, r1; r0 = r1n MOV r0, #5; r0 = 5

o MVN : move (negated)n MVN r0, r1; r0 = NOT(r1)=~ (r1)

Preprocessed by Shiftero Example 1n PRE: r5 = 5, r7 = 8;

n MOV r7, r5, LSL #2; r7 = r5 << 2 = r5*4

n POST: r5 = 5, r7 = 20

6.1.2 Preprocessed by Shiftero LSL: logical shift left

n x << y, the least significant bits are filled with zeroeso LSR: logical shift right:

n (unsigned) x >> y, the most significant bits are filled with zeroeso ASR: arithmetic shift right

n (signed) x >> y, copy the sign bit to the most significant bito ROR: rotate right

n ((unsigned) x >> y) | (x << (32-y))o RRX: rotate right extended

n c flag <<31 | (( unsigned) x >> 1)n Performs 33-bit rotate, with the CPSR’s C bit being inserted above

sign bit of the word

Preprocessed by Shifter (Cont.)o Example 2n PRE: r0 = 0x00000000, r1 = 0x80000004

n MOV r0, r1, LSL #1 ; r0 = r1 *2

n POST r0 = 0x00000008, r1 = 0x80000004

6.1.3 Arithmetic Instructionso Syntax: <instruction> {<cond>} {S} Rd, Rn, N

n N: a register or immediate valueo ADD : add

n ADD r0, r1, r2; r0 = r1 + r2o ADC : add with carry

n ADC r0, r1, r2; r0 = r1 + r2 + Co SUB : subtract

n SUB r0, r1, r2; r0 = r1 - r2o SBC : subtract with carry

n SUC r0, r1, r2; r0 = r1 - r2 + C -1

6.1.3 Arithmetic Instructions (Cont.)o RSB : reverse subtractn RSB r0, r1, r2; r0 = r2 – r1

o RSC : reverse subtract with carryn RSC r0, r1, r2; r0 = r2 – r1 + C -1

o MUL : multiply n MUL r0, r1, r2; r0 = r1 x r2

o MLA : multiply and accumulaten MLA r0, r1, r2, r3; r0 = r1 x r2 + r3

6.1.4 Logical Operationso Syntax: <instruction> {<cond>} {S} Rd, RN, Nn N: a register or immediate value

o AND : Bit-wise ando ORR : Bit-wise oro EOR : Bit-wise exclusive-oro BIC : bit clearn BIC r0, r1, r2; r0 = r1 & Not(r2)

Logical Operations (Cont)o Example 3:n PRE: r1 = 0b1111, r2 = 0b0101

n BIC r0, r1, r2 ; r0 = r1 AND (NOT(r2))

n POST: r0=0b1010

6.1.5 Comparison Instructionso Compare or test a register with a 32-bit valuen Do not modify the registers being compared or

tested

n But only set the values of the NZCV bits of the CPSR registero Do not need to apply to S suffix for comparison

instruction to update the flags in CPSR register

Comparison Instructions (Cont.)o Syntax: <instruction> {<cond>} {S} Rd, N

n N: a register or immediate valueo CMP : compare

n CMP r0, r1; compute (r0 - r1)and set NZCVo CMN : negated compare

n CMP r0, r1; compute (r0 + r1)and set NZCV o TST : bit-wise AND test

n TST r0, r1; compute (r0 AND r1)and set NZCVo TEQ : bit-wise exclusive-or test

n TEQ r0, r1; compute (r0 EOR r1)and set NZCV

Comparison Instructions (Cont.)o Example 4n PRE: CPSR = nzcvqiFt_USER, r0 = 4, r9 = 4

n CMP r0, r9

n POST: CPSR = nZcvqiFt_USER

6.1.6 Multiply Instructiono Syntax: n MLA{<cond>} {S} Rd, Rm, Rs, Rnn MUL{<cond>} {S} Rd, Rm, Rs

o MUL : multiplyn MUL r0, r1, r2; r0 = r1*r2

o MLA : multiply and accumulaten MLA r0, r1, r2, r3; r0 = (r1*r2) + r3

Multiply Instruction (Cont.)o Syntax: <instruction>{<cond>} {S} RdLo, RdHi, Rm, Rs

n Multiply onto a pair of register representing a 64-bit value

o UMULL : unsigned multiply longn UMULL r0, r1, r2, r3; [r1,r0] = r2*r3

o UMLAL : unsigned multiply accumulate longn UMLAL r0, r1, r2, r3; [r1,r0] = [r1,r0]+(r2*r3)

o SMULL: signed multiply longn SMULL r0, r1, r2, r3; [r1,r0] = r2*r3

o SMLAL : signed multiply accumulate longn SMLAL r0, r1, r2, r3; [r1,r0] = [r1,r0]+(r2*r3)

6.2 Branch Instructionso Branch instructionn Change the flow of execution n Used to call a routine

o Allow applications to n Have subroutinesn Implement if-then-else structuren Implement loop structure

Branch Instructions (Cont.)o Syntax

n B{<cond>} lablen BL{<cond>} lable

o B : branchn B label; pc (program counter) = labeln Used to change execution flow

o BL : branch and linkn BL label; pc = label, lr = address of the next

address after the BLn Similar to the B instruction but can be used for subroutine

callo Overwrite the link register (lr) with a return address

Branch Instructions (Cont.)o Example 5

B forwardADD r1, r2, #4ADD r0, r6, #2ADD r3, r7, #4

Forward SUB r1, r2, #4

BackwardSUB r1, r2, #4B backward

Branch Instructions (Cont.)o Example 6:

BL subroutineCMP r1, #5MOVEQ r1, #0…

subroutine<subroutine code>MOV pc, lr ; return by moving pc = lr

6.3 Load-Store Instructionso Transfer data between memory and processor

registers

o Three typesn Single-register transfern Multiple-register transfern Swap

6.3.1 Simple-Register Transfero Moving a single data item in and out of

register

o Data item can ben A word (32-bits)n Halfword (16-bits)n Bytes (8-bits)

Simple-Register Transfer (Cont.)o Syntax

n <LDR|STR>{<cond>}{B} Rd, addressing1

n LDR{<cond>}SB|H|SH Rd, addressing2

n STR{<cond>} H Rd, addressing2

o LDR : load word into a register from memoryo LDRB : load byteo LDRSB : load signed byteo LDRH : load half-wordo LSRSH : load signed halfwordo STR: store word from a register to memory o STRB : store byteo STRH : store half-word

Simple-Register Transfer (Cont.)o Example 7

LDR r0, [r1] ;= LDR r0, [r1, #0] ;r0 = mem32[r1]

STR r0, [r1] ;= STR r0, [r1, #0];mem32[r1]= r0

n Register r1 is called the base address register

6.3.2 Single-Register Load-Store Addressing Modeo Index method, also called Base-Plus-Offset

Addressingn Base register

o r0 – r15n Offset, add or subtract an unsigned number

o Immediateo Register (not PC)o Scaled register

Single-Register Load-Store Addressing Mode (Cont.)o Preindex:

n data: mem[base+offset]n Base address register: not updatedn Ex: LDR r0,[r1,#4] ; r0:=mem32[r1+4]

o Postindex: n data: mem[base]n Base address register: base + offsetn Ex: LDR r0,[r1],#4 ; r0:=mem32[r1], then r1:=r1+4

o Preindex with writeback (also called auto-indexing)n Data: mem[base+offset]n Base address register: base + offsetn Ex: LDR r0, [r1,#4]! ; r0:=mem32[r1+4], then r1:=r1+4

Single-Register Load-Store Addressing Mode (Cont.)o Example 8n r0 = 0x00000000, r1 = 0x00009000,

mem32[0x00009000] = 0x01010101, mem32[0x00009004] = 0x02020202

n Preindexing: LDR r0, [r1, #4]o r0 = 0x02020202, r1=0x00009000

n Postindexing: LDR r0, [r1], #4o r0 = 0x01010101, r1=0x00009004

n Preindexing with writeback: LDR r0, [r1, #4]!o R0 = 0x02020202, r1=0x00009004

Single-Register Load-Store Addressing Mode (Cont.)

[Rn], +/-Rm, shift #shift_immScaled register postindexed

[Rn], +/-Rm!Register postindexed

[Rn], #+/-offset_12]Immediate postindexed

[Rn, +/-Rm, shift #shift_imm]Preindex writeback with scaled register offset

[Rn, +/-Rm]!Preindex writeback with register offset

[Rn, #+/-offset_12]!Preindex writeback with immediate offset

[Rn, +/-Rm, shift #shift_imm]Preindex with scaled register offset

[Rn, +/-Rm]Preindex with register offset

[Rn, #+/-offset_12]Preindex with immediate offset

Addressing syntaxAddressing mode and index method

Examples of LDR Using Different Addressing Modes

(r2 LSR 0x4)mem32[r1]LDR r0, [r1], r2 LSR #0x4

r2Mem32[r1]LDR r0, [r1], r2

0x4mem32[r1]LDR r0, [r1], #0x4Postindex

not updatedMem32[r1-(r2 LSR 0x4)]LDR r0, [r1, -r2, LSR #0x4]

not updatedmem32[r1+r2]LDR r0, [r1, r2]

not updatedmem32[r1+0x4]LDR r0, [r1, #0x4]Preindex

(r2 LSR 0x4)mem32[r1+(r2 LSR 0x4)]LDR r0,[r1, r2, LSR#0x4]!

r2mem32[r1+r2]LDR r0, [r1,r2]!

0x4mem32[r1+0x4]LDR r0, [r1, #0x4]!Preindex with writeback

r1+=r0=Instruction

6.3.3 Multiple-Register Transfero Transfer multiple registers between memory

and the processor in a single instruction

o More efficient than single-register transfern Moving blocks of data around memoryn Saving and restoring context and stack

Multiple-Register Transfer (Cont.)o Load-store multiple instruction can increase interrupt

latencyn Interrupt can be occurred after an instruction has been

completedn Each load multiple instruction takes 2 + N*t cycles

o N: the number of registers to loado t: the number of cycles required for sequential access to memory

n Compilers provides a switch to control the maximum number of registers between transferredo Limit the maximum interrupt latency

Multiple-Register Transfer (Cont.)o Syntax:

n <LDM|STM>{<cond>} <mode> Rn{!}, <registers>{^}

n Address mode: See the next pagen ^: optional

o Can not be used in User Mode and System Modeo If op is LDM and reglist contains the pc (r15)

n SPSR is also copied into the CPSR.

o Otherwise, data is transferred into or out of the User mode registers instead of the current mode registers.

Addressing Mode

Rn+4*NRn – 4Rn-4*Ndecrement address before each transfer

DB

Rn-4*NRnRn-4*N +4decrement address after each transfer

DA

Rn+4*NRn+4*NRn + 4increment address before each transfer

IB

Rn+4*NRn+4*N -4Rnincrement address after each transfer

IA

Rn!End address

Start address

DescriptionAddressing mode

Multiple-Register Transfer (Cont.)o Example 9

n PRE: mem32[0x80018] = 0x03, mem32[0x80014] = 0x02, mem32[0x80010] = 0x01, r0 = 0x00080010, r1 = r2 = r3= 0x00000000

n LDMIA r0!, {r1-r3}, or LDMIA r0!, {r1, r2, r3}o Register can be explicitly listed or use the “-” character

Pre-Condition for LDMIA Instruction

0x000000000x8000c

0x000000010x80010

0x000000020x800140x000000030x80018

0x000000040x8001c

0x000000050x80020

Memory Address Data

R0 = 0x80010 R1=0x00000000

R2=0x00000000

R3=0x00000000

Figure 1

Post-Condition for LDMIA Instruction

0x000000000x8000c

0x000000010x80010

0x000000020x800140x000000030x80018

0x000000040x8001c

0x000000050x80020

Memory Address Data

R0 = 0x8001c

R1=0x00000001

R2=0x00000002

R3=0x00000003

Figure 2

Multiple-Register Transfer (Cont.)o Example 9 (Cont.)n POST:

r0 = 0x0008001c, r1 = 0x00000001, r2 = 0x00000002, r3 = 0x00000003

Multiple-Register Transfer (Cont.)o Example 10n PRE: as shown in Fig. 1n LDMIB r0!, {r1-r3}n POST:

r0 = 0x0008001cr1 = 0x00000004 r2 = 0x00000003 r3 = 0x00000002

Post-Condition for LDMIB Instruction

0x000000000x8000c

0x000000010x80010

0x000000020x800140x000000030x80018

0x000000040x8001c

0x000000050x80020

Memory Address Data

R0 = 0x8001c

R1=0x00000002

R2=0x00000003

R3=0x00000004

Figure 3

Multiple-Register Transfer (Cont.)o Load-store multiple pairs when base update used (!)

n Useful for saving a group of registers and store them later

LDMIASTMDBLDMIBSTMDALDMDASTMIBLDMDBSTMIA

Load multipleStore multiple

Multiple-Register Transfer (Cont.)o Example 11

n PRE: r0 = 0x00009000 r1 = 0x00000009, r2 = 0x00000008r3 = 0x00000007

n STMIB r0!, {r1-r3} MOV r1, #1MOV r2, #2,MOV r3, #3

Multiple-Register Transfer (Cont.)o Example 11 (Cont.)

n PRE (2): r0 = 0x0000900cr1 = 0x00000001, r2 = 0x00000002r3 = 0x00000003

n LDMDA r0!, {r1-r3} n POST:

r0 = 0x00009000 r1 = 0x00000009, r2 = 0x00000008r3 = 0x00000007

Multiple-Register Transfer (Cont.)o Example 11 (Cont.)n The STMIB stores the values 7, 8, 9 to memory

n Then corrupt register r1 to r3 by MOV instruction

n Finally, the LDMDA o Reloads the original values, and o Restore the base pointer r0

Multiple-Register Transfer (Cont.)o Example 12: the use of the load-store multiple

instructions with a block memory copy;r9 points to start of source data;r10 points to start of destination data;r11 points to end of the sourceloop

LDMIA r9!, {r0-r7} ;load 32 bytes from source and update r9STMIA r10!, {r0-r7} ;store 32 bytes to desti. and update r10CMP r9, r11 ;have we reached the endBNE loop

Multiple-Register Transfer (Cont.)

Source

Destination

r9

r11

r10

High memory

Low memory

Copy memoryLocation(transfer 32 bytes in two instructions)

6.3.4 Stack Operationso ARM architecture uses the load-store multiple

instruction to carry out stack operationsn PUSH: use a store multiple instructionn POP: use a load multiple instruction

o Stackn Ascending (A): stack grows towards higher

memory addressesn Descending (D): stack grows towards lower

memory addresses

6.3.4 Stack Operations (Cont.)o Stackn Full stack (F): stack pointer sp points to the last

valid item pushed onto the stackn Empty stack (E): sp points after the last item on

the stacko The free slot where the next data item will be placed

o There are a number of aliases available to support stack operationsn See next page

6.3.4 Stack Operations (Cont.)o ARM support all four forms of stacks

n Full ascending (FA): grows up; base register points to the highest address containing a valid item

n Empty ascending (EA): grows up; base register points to the first empty location

n Full descending (FD): grows down; base register points to the lowest address containing a valid data

n Empty descending (ED): grows down; base register points to the first empty location below the stack

Addressing Methods for Stack Operations

STMDASTMEDLDMIBLDMEDEmpty descending

ED

STMIASTMEALDMDBLDMEAEmpty ascending

EA

STMDBSTMFDLDMIALDMFDFull descending

FD

STMIBSTMFALDMDALDMFAFull ascending

FA

=STMPush=LDMPopDescriptionAddressing mode

6.3.4 Stack Operations (Cont.)o Example 13

n PRE: o r1 = 0x00000002o r4 = 0x00000003o sp = 0x00080014

n STMFD sp!, {r1, r4}n POST:

o r1 = 0x00000002o r4 = 0x00000003o sp = 0x0008000c

6.3.4 Stack Operations (Cont.)o Example 13 (Cont.)

n STMFD – full stack push operation

Empty0x8000c

Empty0x80010

0x000000020x80014

0x000000010x80018

Address Data

sp

PRE

0x000000020x8000c

0x000000030x80010

0x000000020x80014

0x000000010x80018

Address Data

sp

POST

6.3.4 Stack Operations (Cont.)o Example 14

n PRE: o r1 = 0x00000002o r4 = 0x00000003o sp = 0x00080010

n STMED sp!, {r1, r4}n POST:

o r1 = 0x00000002o r4 = 0x00000003o sp = 0x00080008

6.3.4 Stack Operations (Cont.)o Example 14 (Cont.)

n STMED – empty stack push operation

Empty0x8000c

Empty0x80008

Empty0x80010

0x000000020x80014

0x000000010x80018

Address Data

sp

PRE

0x000000020x8000c

Empty0x80008

0x000000030x80010

0x000000020x80014

0x000000010x80018

Address Data

sp

POST

6.3.3 SWAP Instructiono A special case of a load-store instructionn Swap the contents of memory with the contents

of a registern An atomic operation

o Cannot not be interrupted by any other instruction or any other buy access

o The system “holds the bus” until the transaction is complete

o Useful when implementing semaphores and mutual exclusion in an operating system

6.3.3 SWAP Instruction (Cont.)o Syntax: SWP{B}{<cond>} Rd, Rm, [Rn]n tmp = mem32[Rn]n Mem32[Rn] = Rmn Rd = tmp

o SWP: swap a word between memory and a register

o SWPB: swap a byte between memory and a register

6.3.3 SWAP Instruction (Cont.)o Example 15

n PRE: o Mem32[0x9000] = 0x12345678o r0 = 0x00000000o r1 = 0x11112222o r2 = 0x00009000

n SWP r0, r1, [r2]n POST:

o mem32[0x9000] = 0x11112222o r0 = 0x12345678o r1 = 0x11112222o r2 = 0x00009000

6.3.3 SWAP Instruction (Cont.)o Example 15 (Cont.)

SPINMOV r1, =semaphoreMOV r2, #1SWP r3, r2, [r1] ;hold the bus until completeCMP r3, #1BEQ spin

o The address pointed by the semaphore either contains the value of 1 or 0

o When semaphore value == 1 , loop until semaphore becomes 0 (updated by the holding process)

6.4 Software Interrupt Instructiono SWI: software interrupt instructionn Cause a software interrupt exceptionn Provide a mechanism for applications to call

operating system routinesn Each SWI instruction has an associated SWI

numbero Used to represent a particular function call or routines

6.4 Software Interrupt Instruction (Cont.)o Syntax: SWI{<cond>} SWI_numbern lr_svc = address of instruction following the SWIn spsr_svc = cpsrn pc = vector table + 0x8 ; jump to the swi

handlingn cpsr mode = SVCn cpsr I = 1 (mask IRQ interrupt)

6.4 Software Interrupt Instruction (Cont.)o Example 16

n PRE: o cpsr = nzcVqift_USERo pc = 0x00008000o lr = r14 = 0x003fffff

n 0x00008000 SWI 0x123456n POST:

o cpsr = nzcVqIft_SVCo spsr = nzcVqift_USERo pc = 0x00000008o lr = 0x00008004

6.5 Program Status Register Instructionso MRSn Transfer the contents of either the cpsr or spsr

into a register

o MSRn Transter the contents of a register into the cpsr or

spsr

6.5 Program Status Register Instructions (Cont.)o Syntax

n MRS{<cond>} Rd, <cpsr|spsr>n MSR{<cond>} <cpsr|spsr>_<fields>, Rmn MSR{<cond>} <cpsr|spsr>_<fields>, #immediate

o Field: any combination ofn Flags: [24:31]n Status: [16:23]n eXtension[8:15]n Control[0:7]

PSR Registers

6.5 Program Status Register Instructions (Cont.)o Note: You cannot access the SPSR in User or

System Moden Assembler cannot warn you because it does not

know which mode will be executed in

6.5 Program Status Register Instructions (Cont.)o Example 17

n PRE: o cpsr = nzcvqIFt_SVC

n MRS r1, cpsrn BIC r1, r1, #0x80 ;0b10000000, clear bit 7n MSR cpsr_c, r1 ;enable IRQ interruptsn POST:

o cpsr = nzcvqiFt_SVC

n Note that, this example must be in SVC modeo In user mode, you can only read all cpsr bits and can only update

the condition flag field f, i.e., cpsr[24:31]

6.6 Conditional Executiono Almost all ARM instruction can include an

optional condition coden Instruction is only executed if the condition code

flags in the CPSR meet the specified conditionn The default is AL, or always execute

o Conditional executions depends on two componentsn The condition field: located in the instructionn The condition flags: located in the cpsr

Conditional Execution (Cont.)o Example 18

ADDEQ r0, r1, r2; r0 = r1 + r2 if zero flag is set

Condition Codes

6.6 Conditional Execution (Cont.)o Thus, before activate conditional execution n There must be an instruction that updates the

conditional code flag according the resultn If not specified, instructions will not update the

flagso To make an instruction update the flagsn Include the S suffixn Example: ADDS r0, r1,r2

6.6 Conditional Execution (Cont.)o However, some instructions always update the flags

n Do not require the S suffixn CMP, CMN, TST, TEQ

o Flags are preserved until updatedo Thus, you can execute an instruction conditionally,

based upon the flags set in another instruction, either:n Immediately after the instruction which updated the flagsn After any number of intervening instructions that have not

updated the flags.

6.6 Conditional Execution (Cont.)o Example 18n Transfer the following code into the assembly

languagen Assume r1 = a, r2 = b

while ( a!= b ){

if (a > b) a -= b; else b -= a;}

6.6 Conditional Execution (Cont.)o Example 18: Solution 1

gcdCMP r1, r2BEQ completeBLT lessthanSUB r1, r1, r2B gcd

lessthanSUB r2, r2, r1B gcd

complete

6.6 Conditional Execution (Cont.)o Example 18: Solution 2

gcdCMP r1, r2SUBGT r1, r1, r2SUBLT r2, r2, r1BNE gcd

o Solution 2 dramatically reduces the number of instructions !!!

Referenceso Andrew N. Sloss, “ARM System Developer’s

Guide: Designing and Optimizing System Software,” Morgan Kaufmann Publishers, 2004n Chapter 3: Introduction to the ARM Instruction

Set