Chapter 1_4 Chapter 1_4 Part IIPart II

CountersCounters

OverviewOverview

Part 1 - Registers, Microoperations and ImplementationsPart 1 - Registers, Microoperations and Implementations

– Registers and load enableRegisters and load enable– Register transfer operationsRegister transfer operations– Microoperations - arithmetic, logic, and shiftMicrooperations - arithmetic, logic, and shift– Microoperations on a single registerMicrooperations on a single register

Multiplexer-based transfersMultiplexer-based transfersShift registers

Part 2 - Counters, register cells, buses, & serial operationsPart 2 - Counters, register cells, buses, & serial operations

– Microoperations on single register (continued)Microoperations on single register (continued)CountersCounters

– Register cell designRegister cell design– Multiplexer and bus-based transfers for multiple registersMultiplexer and bus-based transfers for multiple registers– Serial transfers and microoperationsSerial transfers and microoperations

Standard Graphic Symbols for Standard Graphic Symbols for Latch and Flip-FlopsLatch and Flip-Flops

Flip-Flop Characteristic TableFlip-Flop Characteristic Table

Flip-Flop Excitation TablesFlip-Flop Excitation Tables

Counters - Definition Counters - Definition

A counter is:

A register that “counts” through a specific sequence of states upon the application of a sequence of input pulses e.g. clock or other signals.

Counters can count up, count down, or count through other fixed sequences.

Binary CounterBinary Counter

An n-bit binary counter:An n-bit binary counter:

– Consists of n flip-flops.Consists of n flip-flops.

– Counts from 0 to (2Counts from 0 to (2n n -1).-1).

Two Counter Categories Two Counter Categories

1.1. Synchronous counterSynchronous counter

2.2. Ripple counters (Asynchronous Ripple counters (Asynchronous counter)counter)

… … CountersCounters

1.1. Ripple CountersRipple Counters– FF output transition serves as a source for FF output transition serves as a source for

triggering other FFs.triggering other FFs.– C input not triggered by the common clock C input not triggered by the common clock

pulse.pulse.

2.2. Synchronous countersSynchronous counters– C inputs of all FFs receive the common C inputs of all FFs receive the common

clock pulse.clock pulse.– The change of state is determined from the The change of state is determined from the

present state of the counter.present state of the counter.

Counter ExamplesCounter Examples

Binary CounterBinary Counter

Decade CounterDecade Counter

Up-Down Counter Up-Down Counter

Arbitrary Sequence CounterArbitrary Sequence Counter

Johnson CounterJohnson Counter

Ring CounterRing Counter

Synchronous CountersSynchronous Counters

Synchronous CountersSynchronous Counters

The clk inputs of all flip-flops receive a The clk inputs of all flip-flops receive a commoncommon clock pulse clock pulse (directly connected)(directly connected)..

The change of state is determined from The change of state is determined from the present state.the present state.– By using combinational logic.By using combinational logic.

4-bit Synchronous Binary Counter4-bit Synchronous Binary Counter

Johnson CounterJohnson Counter

The complement of the output of the last flip-flop The complement of the output of the last flip-flop is connected back to the input of the first flip-flop.is connected back to the input of the first flip-flop.

The counter will “fill up” with 1’s from left to right, The counter will “fill up” with 1’s from left to right, and then will “fill up” with 0’s againand then will “fill up” with 0’s again

Figure 9–24Figure 9–24 Timing sequence for a 4-bit Johnson counter. Timing sequence for a 4-bit Johnson counter.

Convert the waveform results into table form.Convert the waveform results into table form.

Thomas L. FloydThomas L. FloydDigital Fundamentals, 9eDigital Fundamentals, 9e

Copyright ©2006 by Pearson Education, Inc.Copyright ©2006 by Pearson Education, Inc.Upper Saddle River, New Jersey 07458Upper Saddle River, New Jersey 07458

All rights reserved.All rights reserved.

Ring CounterRing Counter

A “1” is always retained in the counter and simply shifted “around A “1” is always retained in the counter and simply shifted “around the ring”, advancing one stage for each clock pulse.the ring”, advancing one stage for each clock pulse.

Output of 10-bit Ring CounterOutput of 10-bit Ring Counter

Initial state is 1010 0000 00

Convert the waveform results into table form.Convert the waveform results into table form.

Johnson Counter vs Ring CounterJohnson Counter vs Ring Counter

Asynchronous CountersAsynchronous Counters

Ripple Counters – clk SourceRipple Counters – clk Source

The clk inputs of some flip-flops are supplied by the outputs on other flip-flops.

– The (Master) CLOCK is connected to the clk input on the LSB bit flip-flop.

– For all other bits, a flip-flop output is connected to the clock input,

– Thus, the circuit is not synchronous.

Ripple Counters – Pros & ConsRipple Counters – Pros & Cons

Advantage– Simple Hardware (Decoder gates not

required).– Low power consumption.

Disadvantage– Slow– Output change is delayed more for each bit

towards the MSB.

4-Bit Ripple Counter4-Bit Ripple Counter

Both J and K inputsof the flip-flops aretied to logic 1flip-flop complements

5-45-4 Ripple CountersRipple Counters

Figure 5-8Figure 5-8

J and K of all FFs – tied together to logic 1J and K of all FFs – tied together to logic 1

Negative edge triggered clock inputs.Negative edge triggered clock inputs.

QQ00 serves as clock input to 2 serves as clock input to 2ndnd FF, and so FF, and so

on.on.

N(Clear) – clears registers to 0 N(Clear) – clears registers to 0 asynchronously. asynchronously.

Design of Synchronous Design of Synchronous Binary CountersBinary Counters

1.1. Using D flip-fops Using D flip-fops

2.2. Using JK flip-flopsUsing JK flip-flops

Counting Sequence of a 4-bit Counting Sequence of a 4-bit Binary CounterBinary Counter

4-bit Binary Counter4-bit Binary Counter

Using D flip-flopUsing D flip-flop

State Table and Flip-Flop Inputs for Binary State Table and Flip-Flop Inputs for Binary CounterCounter

What’s next? .. What’s next? ..

K-maps (4) K-maps (4)

Minimized Equations for:Minimized Equations for:D0D0

D1D1

D2D2

D3D3

4-Bit Binary Counter with D Flip-Flops4-Bit Binary Counter with D Flip-Flops

4-bit Binary Counter4-bit Binary Counter

Using JK flip-flopUsing JK flip-flop

State Table and Flip-Flop Inputs for Binary State Table and Flip-Flop Inputs for Binary CounterCounter

K-MapsK-Maps

Count-Enable InputCount-Enable Input

To control the operation of counter, EN.To control the operation of counter, EN.JJQ0Q0 = K = KQ0Q0 = EN = EN

JJQ1Q1 = K = KQ1Q1 = Q = Q0 0 . EN. EN

JJQ2Q2 = K = KQ2Q2 = Q = Q00 . Q . Q1 1 . EN. EN

JJQ3Q3 = K = KQ3Q3 = Q = Q00 . Q . Q1 1 . Q. Q22 . EN . EN

EN = 0; all J and K inputs equal to 0, FFs- EN = 0; all J and K inputs equal to 0, FFs- no change.no change.

EN = 1; JEN = 1; JQ0Q0 = K = KQ0Q0 = 1, and the other = 1, and the other

equations follow Fig. 5-9.equations follow Fig. 5-9.

4-Bit Synchronous Binary Counter4-Bit Synchronous Binary Counter

Binary Counter with Parallel LoadBinary Counter with Parallel Load

Counters in digital systems, e.g. Counters in digital systems, e.g. computers, often require a parallel-load computers, often require a parallel-load capability.capability.– To transfer an initial binary number into the To transfer an initial binary number into the

counter before the count operation.counter before the count operation.– Load = 1; count operation disabled, data Load = 1; count operation disabled, data

transferred from the 4 parallel inputs into the 4 transferred from the 4 parallel inputs into the 4 FFs.FFs.

– Load = 0 and Count = 1; normal operation. Load = 0 and Count = 1; normal operation.

4-Bit Binary Counter with Parallel Load4-Bit Binary Counter with Parallel Load

Up-Down Binary CounterUp-Down Binary Counter

Synchronous Count Down CounterSynchronous Count Down Counter

Sequence (reverse):Sequence (reverse):– From 1111 to 0000 and back to 1111 to From 1111 to 0000 and back to 1111 to

repeat the count.repeat the count.

The logic diagram is similar to the count-The logic diagram is similar to the count-up counter, except that the inputs to the up counter, except that the inputs to the AND gates must come from the AND gates must come from the complement outputs of the flip-flops.complement outputs of the flip-flops.

Synchronous Up-Down CounterSynchronous Up-Down Counter

Needs a mode input to select between the Needs a mode input to select between the two operations.two operations.– S=1: count upS=1: count up– S=0: count downS=0: count down

Also need a count enable input, EN:Also need a count enable input, EN:– EN=1; normal operation (up/down)EN=1; normal operation (up/down)– EN=0; disable both countsEN=0; disable both counts

4-bit BCD Counter4-bit BCD Counter

Using T flip-flopUsing T flip-flop

State Table and Flip-Flop Inputs for State Table and Flip-Flop Inputs for BCD CounterBCD Counter

The scHeMatiCThe scHeMatiC

Draw the K-maps and get the minimized Draw the K-maps and get the minimized equations. equations.

.. Draw with four T flip-flops, four AND .. Draw with four T flip-flops, four AND gates and one Or gate.gates and one Or gate.

Arbitrary Sequence CounterArbitrary Sequence Counter

Using JK flip-flopUsing JK flip-flop

Counter with Arbitrary CountCounter with Arbitrary Count

State Table and Flip-Flop Inputs for State Table and Flip-Flop Inputs for CounterCounter

Counter with Arbitrary CountCounter with Arbitrary Count

Question …Question …

What does this mean: What does this mean:

– “ “This counter is presettable…” ?This counter is presettable…” ?