chapter 10 - v3.1.pdf
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Programmable Timer Subsystem The timer section in the M68HC11 is based ona 16-bit counter operating from the system E-clock. It provides basic real time functions with the following features: Timer overflow to extend the 16-bit capability of the timer section counter. Output compare function that can generate a variety of waveforms by comparing the 16-
bit timer counter with the contents of a programmable register. Input capture function that can latch the value of the 16-bit timer counter on selected
edges of external control signals. Programmable and periodic interrupt generator, called the real time interrupt. Pulse accumulator to count external events or act as a gated timer counting internal clock
pulses. Computer operating properly (COP) watchdog timer. The timer subsystem is the most complex subsystem in the M68HC11 and it involves many control registers and control bits. All timer functions have interrupt controls and separate interrupt vectors. Figure 10.1 illustrates the timer subsystem block diagram. Timer subsystem registers: Data registers TCNT Timer count register TIC1-TIC3 Timer input capture registers 1 to 3 TIC1-TIC5 Timer output compare registers 1 to 5 PACNT Pulse accumulator count register Control registers TCTL1 Timer control register 1 (output compare specifications) TCTL2 Timer control register 2 (input capture edge specifications) TMSK1 Main timer interrupt mask register 1 (output compare and input capture
interrupt enable bits) TMSK2 Miscellaneous timer interrupt mask register 2 (other interrupt enable bits) PACTL Pulse accumulator control register OC1M Action mask register OC1D Action data register Status registers TFLG1 Main timer interrupt flag register 1 (output compare and input capture flags) TFLG2 Miscellaneous timer flag register 2 (other system flags) For the names and positions of various control and status bits see also Fig 11.1 in your reference book (Spasov).
Fig. 10.1 Main timer system block diagram
Port A Pins If the timer function is not enabled Port A pins can be used as general input/output pins. Otherwise port A pins have certain other functionality related to the specified timer subsection operation. Basic Timer The key to the operation of the M68HC11 is the 16-bit, free running counter called the TCNT. It is input is the system E-clock, which may be prescaled (divided) by 1, 4, 8 or 16. Starting from $0000 at system reset, the counter counts forever and the programmer can read its
contents at any time. When it reaches $FFFF, it is reset to $0000 and the timer overflow flag (TOF in TFLG2) is set. This state can be detected either by polling or by an interrupt if timer overflow interrupt enable (TOI in TMSK2) bit is set. Clearing Timer Flag The flag bits in both of the status registers TFLG1 and TFLG2 are cleared by writing a 1 to the bit to be cleared. For example to clear TOF, you may use the following instructions: LDAA #$80 STAA TFLG2, X (assuming IX=$1000 and TFLG2 is the offset relative to
the base register address) Example: LDS #STACK LDAA #%10000000 STAA TFLG2 ; clear the TOF bit REPEAT LDAA #NTIMES STAA COUNTER ; init the counter variable SPIN1 TST TFLG2 BPL SPIN1 ; wait until TOF (bit-7 in TFLG2) is set LDAA #%10000000 STAA TFLG2 ; reset TOF DEC COUNTER ; decrement the counter BNE SPIN1 JSR RING_A_BELL ; ring a bell if the counter reaches to 0 BRA REPEAT ; continue by re-initializing the counter The above program rings a bell every NTIMES*65536 E-clock cycles assuming a prescaling factor of 1 (NTIMES*32.768 ms with a 2 Mhz E-clock). The same example with interrupt driven approach: Timer overflow interrupt vector: $FFDE:$FFDF Buffalo monitor vector jump table (pseudovector) for timer overflow interrupt: $D0:$ D2)
ORG $00D0 JMP ISR ; set the timer overflow interrupt pseudo vectors ORG PROG
LDS #STACK CLR DATA
LDAA #%10000000 STAA TFLG2 ; reset TOF flag STAA TMSK2 ; enable the timer interrupts (set TOI bit) CLI ; enable processor interrupts START BRA START ISR INC DATA ; increment DATA
CMPA #NTIMES ; check if it is equal to NTIMES BNE ENDIF
JSR RING_A_BELL ring a bell if DATA is equal to NTIMES
CLRA STAA DATA ; reinitialize DATA
ENDIF LDAA #%10000000 STAA TFLG2 ; reset TOF RTI Output Compare The output compare allows more accurate timing delays than the timer overflow flag. The following figures describe the output compare operation
A 16-bit timer output compare register, TOCn, may be written by the program with a double-byte store instruction, e.g., STD TOC5. The other 16-bit compare register is the free-running TCNT counter. A comparison is made at every bus clock cycle (E-clock cycle) and when the TOCn is identical to TCNT, the output compare flag, OCnF, is set. OCnF is also ANDed with an output compare interrupt eneable bit to generate an interrupt. The output compare functions are controlled by several registers as follows:
Example: Generate a 10 msec (which is less than the minimum timer overlow duration) pulse assuming a 2 Mhz E-clock. * Drive one-shot high pulse for 10 ms * with E = 2 MHz and prescale = 1 ORG $100 PWIDTH EQU 20000 LDD TCNT,X ;prevent premature STD TOC2,X ;OC2 compare PULSE BSET PORTA,X $40 ;drive PA6/OC2 high LDAA #$80 ;configure OC2 to clear STAA TCTL1,X ;and disconnect other OCx's LDAA #$40 ;clear OC2F if set STAA TFLG1,X LDD TCNT,X ;arm TOC2 for 10-ms trigger ADDD #PWIDTH-17 STD TOC2,X PULSE1
BRCLR TFLG1,X $40 PULSE1 ;wait for trigger by polling for OC2F high ;now OC2 becomes low automatically BCLR PORTA,X $40 ;clear internal latch bit for PA6 and LDAA #$40 ; STAA TFLG1,X ; then clear OC2F BCLR TCTL1,X $80 ;disconnect OC2 * BRA * ;end for now
One Output Compare Controlling Up to Five Outputs The Output Compare 1 channel has special features that are controlled by the OC1M and OC1I registers. Output Compare 1 can simultaneously switch up to five outputs.
OC1M and OC1D work together to define the action taken on port A, bits 7-3. OC1M is a mask register and a 1 in a bit position in the mask means that the corresponding data bit in the data register, OC1D, is transferred to the output bit in port A. The transfer from OC1D to port A occurs when a successful output comparison is made. Thus up to five bits can be simultaneously changed by one output comparison. Note that Output Compare 1 can be used with another output compare channel to produce very short duration pulses (as short as one E-clock) (see the example program below). Forced Output Compares CFORC register bit is ORed with the output compare flag. Therefore, writing a one to this register forces a comparison action to occur at the output pins. This forced comparison does not set the output compare flag and therefore no interrupt will be generated.
The above figure illustrates some of the capabilities of the timer subsection. Using the output compare function, it is possible to generate a one shot or a fixed or variable duty cycle continuous waveforms.
Example: A 2 s (very short duration) pulse generation at every 32.768 ms on port A bit-6.
TCNT EQU $0E TFLG1 EQU $23 TCTL1 EQU $20 TOC1 EQU $16 TOC2 EQU $18 OC1M EQU $0C OC1D EQU $0D
PROG EQU $C000 DATA EQU $D000 STACK EQU $DFFF
REGS EQU $1000
ORG PROG LDS #STACK LDX #REGS
LDD TCNT, X ; grab the value of the TCNT register STD TOC1, X ADDD #4 ; set TOC2 to compare 4 cycles later STD TOC2, X
LDAA #%11000000 ; reset output compare flags STAA TFLG1, X LDAA #%01000000 ; init the data and mask registers STAA OC1D, X STAA OC1M, X LDAA #%10000000 ; setup OC2 to reset the bit STAA TCTL1, X
BRCLR TFLG1, X %01000000 SPIN ; wait until OC2F is set LDAA #%11000000 ; reset OC1F, OC2F STAA TFLG1, X BRA SPIN ; continue
The input capture hardware is shown above. Three 16-bit Timer Input Capture registers, TIC1-TIC3, latch the value of the free-running counter in response to a program-selected, external signal. For example the length of a positive pulse can be measured by capturing the time at the rising edge and then again at the falling edge.
The above figure illustrates again some of the capabilities of the timer subsection. Using the input capture function, it is possible to make pulse width measurements, period measurements or count pulses.
Example: Write a subroutine, which determines the period of a square wave in units of clock cycles (assume that the period is
In four-phase stepper motors, the direction (polarity) of the current through the windings determines which position the motor steps to next. A high level of current called the rush current is required to cause shaft rotation. Each change of polarity at the terminal of a winding is called a step of phase shift. A sequence of logic pulses steps the motor from one position to the next.
This causes the shaft (rotor) to rotate in precise angular increments per step. The phase sequence may begin anywhere but it must continue in the specified order. For example, the following waveform rotates the motor for 10 steps clockwise.
During the period when no rotation occurs, the motor windings must be supplied with a lower level of current called the hold current. Since high currents are required to drive the stepper moto