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Current Applied Physics 11 (2011) e101ee103

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Current Applied Physics

journal homepage: www.elsevier .com/locate/cap

Challenges and opportunities for future non-volatile memory technology

Yoshio NishiDepartment of Electrical Engineering, Center for Integrated Systems, Stanford University, Stanford, CA 94305-4070, United States

Keywords:Nonvolatile memoryRRAMRERAMCBRAMReDoxab-initio modeling

E-mail address: yoshio.nishi@stanford.edu.

1567-1739/$ e see front matter � 2011 Elsevier B.V.doi:10.1016/j.cap.2011.01.022

a b s t r a c t

Recent progress made in new non-volatile semiconductor memory materials such as chalcogenide,binary metal oxides, perovskites, ferromagnetics, ferroelectrics, organic materials and carbon basedmaterials is quite exciting and will open new horizon for the future terabit memory era. It is, however,interesting to note that most of such new non-volatile memory operation can be described by a “changeof resistance” of materials. For instance, phase change memory depends upon the change of resistivitybased upon whether the material is amorphous or crystalline, but the function of resistive switchingmemory family, often called ReDox, RRAM, ReRAM, CBRAM, is ascribed to motion of either ions orvacancies resulting in creation of nanoscale conductive path inside of the material. Here we can clearlysee a new paradigm, as opposed to traditionally accepted notion of semiconductor device operationwhere only electrons and holes contribute to current and charge storage in structurally stable crystallattice, is now emerging; and non-volatile memory functionality is contributed by the structural changesof the material itself coupled with motion of electrons and holes or even include such state variables asspin involved.

This creates an enormous challenge to our technical community in terms of needs for cross-boundarycollaborations of multi-disciplinary expertise and knowledge base.

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1. Introduction

Semiconductor memory together with logic devices has playeda critical role on the growth of the IC industry in terms of providingcost effective solutions for ever increasing needs for data storagewhich has created a number of applications for computer andcommunication fields.

Further, technology evolution in ubiquitous communicationsand computing based upon mobile handsets has changed the ICindustry with respect to memory-bit consumption and memoryusage. Especially looking into 3G and beyond which supportsmultimedia functions such as digital photography, MP3, video ondemand, it is apparent that a significantly larger number of bits ofmemory are required on a single chip. An important fact to notewould be the share of non-volatile memory, e.g. flash memory,which already far surpassed volatile memory by a factor of 20 [1]out of total memory consumption in the world. Embeddedmemory may consume as much as 90% or more of a typical chip ofthis nature. Power consumed by such memory areas of the chipincluding in the active and stand-by states will quickly becomea substantial portion of the entire power budget. On the other hand,MOSFET performance in terms of Ion/Ioff ratio continues to

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deteriorate as geometry scaling proceeds, which is presentinga major challenge for typical embedded memory, i.e. SRAM. Alsothe scalability of flash memory is now questioned as theprogramming voltage and data retention have fundamental phys-ical conflicts with each other beyond certain small geometry. Facedwith such a situation, there has been a variety of research in newmemory opportunities, especially non-volatile memory, world-wide. Nanoparticle-based memory to replace floating gate, resis-tance change memory, phase change memory, ferroelectricmemory, magnetic spin basedmemory and even organic/molecularmemory are being pursued. Whenwe look at these varieties of newnon-volatile memories, one obvious characteristic is the need fornew materials that go far beyond the common practice of thetraditional IC industry and technology, and another characteristic isto utilize resistance change phenomena of materials whenprogramming power is applied to a diode structure.

2. Resistance change for non-volatile memory

It is an interesting coincidence that most, if not all, of newlyemerging non-volatile memory devices are based upon resistancechange of materials when programming voltage/current is appliedto two terminals sandwiching the resistive change material. Phasechange memory, and ReDox memory (RRAM) are typical examples.Therefore,memoryarrayconfiguration canbeverysimilar, i.e. cross-

Table 1Known examples which show resistive switching.

Binary metaloxide

TiO2, NiO, CuxO, ZrO2, MnO2, HfO2, WO3, Ta2O5, Nb2O5, VO2,Fe3O

Perovskite PCMO(Pr0.7Ca0.3MnO3), LCMO(La1�xCaxMnO3)BSCFO(Ba0.5Sr0.5Co0.8Fe0.2O3�d), YBCO(YBa2Cu3O7�x)(Ba,Sr)TiO3(Cr, Nb-doped), SrZrO3(Cr,V-doped), (La, Sr)MnO3

Sr1�xLaxTiO3, La1�xSrxFeO3, La1�xSrxCoO3, SrFeO2.7, LaCoO3

K2NiF4 La2�xSrxNiO4, La2CuO4þd

Others GexSe1�x(Ag,Cu,Te-doped), Ag2S, Cu2S, CdS, ZnS, CeO2, SiO2,Carbon (sp2esp3 transition)

Y. Nishi / Current Applied Physics 11 (2011) e101ee103e102

point bit with selection diode or transistor integrated. There arecertain common advantages in such configurations, i.e. 4F2 capable,3-D integration on top of active device layers, possibly lower cost,and still fast enough for programming and readout, even thoughscalability of programming power, data retention and set/resetendurance still remains opportunity for further research.

Phase change memory, out of those resistance change memo-ries, seems closer to practical applications, indeed, there have beenseveral announcements made in the past years, and the latest workwith 45 nm technology realized 1 Gbwith power supply of 1.8 V [2].A number of basic studies for the phase change characteristics havebeen reported, but the choice of materials seems converging intoGeeSbeTe, GST, and their compositional variations. Due to theneeds for temperature dependent phase change between amor-phous state and crystalline state, a question about how such heat isgenerated and supplied to the phase change material, and also howcontrollably remove the heat poses optimization issue of thermaldesign of the cell structures. Programming current seems, so far,staying around mA range which should be reduced substantially tobe used at below 15 nm technology based ultra high densitymemory. This is even more stringent requirement when it isembedded into logic chips.

Metal oxides, metal sulfides and Perovskite group exhibitresistance change with several different mechanisms. Resistancechange devices due to reversible filamentary percolation path, bulkdefect/trap conduction or interface modifications represent a high-risk, high-payoff approach to embedded non-volatile memory(NVM). There appears to be two broad classes of devices, one basedon solid ionic conductors and the other based on the transitionmetal oxides. Resistive switching materials offer a low cost, lowtemperature, non-volatile memorymodule that may be compatiblewith back-end processing. They offer the possibility for highlyscalable, low power operation with non-destructive readout andeven multiple bits per cell. But little is known about the funda-mental switching mechanisms, so it is difficult to gauge reliability,endurance, retention or even the true scaling limits of the devices.

A number of earlier studies for solid ionic conductors lookedinto films such AgS, ZnCdS, etc. These films can achieve very lowon-resistance as a result of the metallic conducting filament, andwithout exception they exhibits bipolar switching, i.e. set and resetvoltages are in opposite polarity to each other.

The interest in the complex transition metal doped oxidesemerged from research on high temperature superconductivity[3e6] and DRAM capacitor dielectrics, but the reason for theirresistive switching behavior is not well understood. Indeed, thefirst report that ascribed the switching behavior to ordereddomains in the bulk material [3] has been roundly criticized.Instead, a switching mechanism was postulated that relies oncarrier trapping in the interfacial layer and interfacial barriermodification due to field induced defects at surfaces [4,5]. Butfilamentary paths cannot be ruled out either in this class of mag-netoresistive materials [6]. The IBM group has focused on thecomplex transition doped perovskites, and demonstrated repro-ducible switching and even multiple-bit addressing in simplecapacitor structures [7,8]. The electronic character of the transitionmetal impurities and defect states has been studied by electronspin resonance, and shows charge transfer and trapping states. Aplausible mechanism suggests that charge transfer processes viastates in the energy gap give rise to carrier creation and transportwith the insulator which could be relevant to the memory andswitching behavior.

Simple binarymetallic oxides (NiO, Cu2O) also exhibit switching,first observed in the early 1960’s [9,10], and rediscovered alongwiththemetal sulfides as a potentially scalablememory solution [11e13].Filamentary mechanisms are thought to be at work, though the

influence of simultaneous electronic and ionic conduction throughlatticevacanciesmayalso contribute tothe fundamentalmechanismof switching [14].

In recent years, significant progress has been made on binarymetal oxides. Notably, the use of NiO, HfOx, AlOx, TiOx has beenintensively studied. Continuous exploration for the use of theseRRAM materials and study for the interaction between the RRAMmaterials with the electrode materials (e.g. Pt, Ti, TiN, W, Al, Cu etc)are in progress. Table 1 summarizes a variety of resistive switchingmaterials. Some of them tend to show unipolar switching, while theother exhibit bipolar switching.

One of the unique features of resistance change memory whichcan differentiate from traditional semiconductor devices whenconsidering the switching model is that we would have far moreparameters to consider in terms of modeling the set/reset opera-tions and retention as compared to traditional counterparts such asfloating gate flash, SONOS. In the past once device structure is built,only moving charges are electrons and holes, therefore we can dealwith the device operation with a set of equations for electrons andholes only. On the contrary, most of resistance change devices doinclude movements of atoms, ions, vacancies and interstitials ontop of electrons and holes during an ordinary operation of devicesof set/reset and data retention. This situation has forced us to utilizefar more sophisticated tools to describe the performance of thedevices. Atomistic ab-initio modeling/simulations and moleculardynamic/modeling find broad applications here. In other words, wecan have more control knobs to optimize/create memory func-tionality. Recent works published [15,16] by means of atomisticab-initio simulations revealed the on-state conduction mechanismwhich consists of vacancy induced d-electron redistributioncreating conductive path depending upon the direction of vacancyarrays. Regarding the theoretical model for filament formationmechanism and formation energy calculations would requiremolecular dynamic simulations, and have not reached anyconclusive picture yet, but experimental observations have beenreported for binary oxide such as TiO2 inwhich creation of Magneliphase reported [17] has attracted attention.

3. Challenges and conclusive remarks

Considering the ever increasing bit capacity for non-volatilememory, while most of them would be embedded on logic chipwith the least amount of power consumption for programming andlong enough retention with lower cost of manufacturing againsttheir predecessor, the magnitude of challenges should growsignificantly. Resistance switchingmemory family such as RRAM, inprinciple, seems having a good potential of meeting thoserequirements, but we need to ask a set of rather fundamentalquestions before a large scale implementation with peripheralcircuits design considerations:

� Is it possible to achieve a cross-point RRAM array with noselection device?

Y. Nishi / Current Applied Physics 11 (2011) e101ee103 e103

� What is the read/write circuits required?� How do SET current and RESET current affect the circuits?� Can the array be placed on top of the circuits to improve areaefficiency?

� Can 3D stacking be achieved?� How much operational margin is obtainable for multi-levelimplementation?

� Can a rectifying device be integrated into the RRAM stack?� Do we have enough fundamental understanding of theswitching mechanism?

Those are just a beginning of questions, followed by a number ofmanufacturability questions.

Perhaps the good news would be possible separation of logicdevice fabrication process and new non-volatile memory fabrica-tion process, one in the front end and the other in the back end ofwafer processing, and still share the common platform of siliconbased CMOS. Out of the above list, the last itemwould requiremuchbroader spectrum of scientific/engineering efforts as we need to

handle larger number of knobs to turn and optimize, but this mayresult in another break-through in terms of materials, processes,device structures and integration.

References

[1] C.Y. Lu, H. Kuan, IEEE Nanotechnology Magazine 1 (2009) 4.[2] C. Villa, et al., ISSCC Digest of Technical Papers (2010) p. 270.[3] S.Q. Liu, et al., Applied Physics Letters 76 (2000) 2749.[4] A. Baikalov, et al., Applied Physics Letters 83 (2003) 957.[5] S. Tsui, et al., Applied Physics Letters 85 (2004) 317.[6] S. Duhalde, et al., Physica B 354 (2004) 11.[7] A. Beck, et al., Applied Physics Letters 77 (2000) 139.[8] Y. Watanabe, et al., Applied Physics Letters 78 (2001) 3738.[9] J.F. Gibbons, W.E. Beadle, Solid State Electronics 7 (1964) 785.

[10] D.C. Bullock, D.J. Epstein, Applied Physics Letters 17 (1970) 199.[11] S. Seo, et al., Applied Physics Letters 85 (2004) 5655.[12] S. Seo, et al., Applied Physics Letters 86 (2005).[13] T. Sakamoto, et al., Applied Physics Letters 82 (2003) 3032.[14] R. Waser, M. Aono, Nature Materials 6 (2007) 833.[15] S.-G. Park, et al., Physical Review B 81 (2010) 115109.[16] H.D. Lee, et al., Physical Review B 81 (2010) 193202.[17] D.-H. Kwon, et al., Nature Nanotechnology 5 (2010) 148.