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NanSun

UniversityofTexasatAustin

[email protected]

NyquistRateDACs

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Overview Topologies

ResistorstringDAC

VoltageswitchingDAC

CurrentsteeringDAC

SwitchedcapacitorDAC

R2R

DAC

CurrentsteeringDACarchitectures

Staticerrors

Dynamicerrors

Exampleimplementations

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Resistor

String

Voltage

DAC Digitallycontrolledpotentiometer

Advantages

Simple

Monotonic

Unsuitableforhighspeed

Treetypeofdecoderhasa

largeresistance

LargeandunequalRCtimeconstantattheoutput

Addanopampwillhelp

Highpower

&

low

speed

Unsuitableforhighresolution

Toomanyresistors&switches

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Voltage

Switching

DAC

4

Useanalog

adders

Nonlinearityduetononzeroswitchturnonresistance

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Current

Steering

DAC

5

MOSswitchesaremuchbetteratswitchingcurrentthanvoltage!

Canbuild

very

good

current

sources

with

high

impedances

Suitableforhighspeed

Avoidtheuseofopamps

SmallRCtimeconstantsattheoutput

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Switched

Capacitor

DAC

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Initialization

Phase

(=Vdd)

7

0Qout

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Evaluation

Phase

(=0)

8

Dueto

charge

conservation:

0C2)VD(VCVQ i1-B

0i

refioutoutout

1-B

0ii

-Bi

refoutD2VV

NonlinearcapatVout isabigproblem

Useanopampwithafeedbackcap

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R

2R

DAC

Concept

9

Aforementionedtechniquesallrequirelargedeviceratios

Assumingthesizeofthesmallestdeviceisfixedbymatching

requirement,

a

large

device

ratio

leads

to

a

large

area Isitpossibletogetexponentiallyweightedvoltage/currentsbyusing

similarsizeddevices?

R2Rladder

Howtopullthecurrentout?

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R

2R

DAC

Implementation

10

OTAscanbeusedtoremoveVGS variations

Extrapower,area,andslow

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Drain

R

2R

Ladder

11

Thistopologyensuresthesamecurrent

Lowoutput

impedance

of

R

2R

ladder

necessitate

opamp

unsuitableforhighspeed

Nowadays,mosthighspeedDACsarecurrentsteeringDACs

WewillfocusoncurrentsteeringDACsfromnowon

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Overview

Topologies


BinaryweightedDAC

ThermometerDAC

SegmentedDAC

Staticerrors

Dynamicerrors


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BinaryWeightedCurrentSteeringDAC

Simplestructure

Noencoderneeded

Howtomatchthecurrentsources?

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HowtoAchieveGoodMatching

Allcurrentsourcesaremadebyidenticalunitcurrentsourcesputin

parallel.

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BinaryWeightedDACPrinciple

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MSBTransitionProblem

16

MSBtransition

problem

Cannotensuremonotonicity

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ThermometerCurrentSteeringDAC

Inherentlymonotonic

Needlargeencoderwith2B1outputs

ImpracticalforlargeB

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ThermometerDACPrinciple

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MonotonicityGuaranteed

19

Always

monotonic

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SegmentedDAC

BinarysegmentwithBb bits;thermometersegmentwithBt =B Bb bits EasiertoensuremonotonicitythanpurelybinaryDAC

SmallerencoderthanpurelythermometerDAC

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SegmentedDAC(22)

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EasiertoEnsureMonotonicity

22

Stillmonotonic

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Overview

Topologies


Staticerrors

Mismatch

Finiteoutputimpedance

Dynamicerrors


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SystematicMismatch

DNLandINLduetounitelementmismatch

Systematicmismatches

IRdropduetocontactandwiringresistance

Processartifact

Edgeeffects

Gradients Systematicmismatchescanbemitigatedthroughproperlayout

Adddummycell

Commoncentroidlayout

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Layout

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RandomMismatch

Randommismatchesaremorefundamentalandcannotbeimprovedthroughlayout

Random

number

of

dopants

(Vt variation) Randometching(W&Lvariation)

ForawelldesignedDAC,itsnonlinearityshouldbelimitedbyrandommismatch,notsystematicmismatch

Whatisthedistributionoftherandommismatch:

Normaldistribution

(central

limit

theorem)

ForaunitcurrentsourceI[k]

Mean:I

Standarddeviation:

Wecan

write

I[k]

=I(1+I/I),thenthepercentagemismatchI/I has: Mean:0

Standarddeviation:I/I

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MismatchinMOSCurrentSources

Example

W=10m,L=0.1m,gm/I=10S/A,AVt=5mVm,A=1%m

MismatchisusuallydominatedbyVt mismatch.

27

I

Vg

I

I tm

WL

A

Vt

Vt WL

A

/ LW

C2

1 ox

2

/

2

Vtm

I/I I

g

%1.5%)1(%)5()01.0()005.00(1 2222uI/I

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HowtoReduceRandomMismatch

UselargertransistorswithbiggerWandbiggerL

Largerarea

Largerparasitics

Reducegm/I

Biasinstronginversion largeVov reducedoutputswing

Reduce

Avt and

A Betterprocess increasedcost

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DACINL/DNLAnalysis

Questiontoask:

Givenu,howlargeareDAC INLandDNL?

Itdependsondifferentarchitectures

ThermometerDAC

BinaryweightedDAC

Segmented

DAC

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ThermometerDACDNLAnalysis

ForthermometerDAC,thestepsizeforcodekequalsthemagnitudeof

thekth currentsource.

30

I

I

I

II

Step

StepStep[k]DNL[k] k

avg

avg

uI/IDNL[k]

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ThermometerDACDNLYield

Questiontoask:

Wehavea8bitthermometerDACwithu =1%.WewanttheDACDNLtobewithin0.03LSB.Whatistheyieldafterfabrication?

Analysis

0.03LSB=3%=3u Foronecode,itswidthfallsinbetween3 is99.73%,accordingto

normal

distribution. Wewantall28=256codessatisfytherequirement,thus,theyieldis:

(99.73%)256 50%

Howabouta12bitDAC?

All4096

codes

satisfy

the

requirement

yield

=(99.73%)4096

0 LetusrelaxtheDNLrequirementto0.05LSB yield 99%

Abigchange,why?

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ThermometerDACINLAnalysis

kY

XNk

I

I

N

IN

1

IN

kI

Step

[k]I[k]IINL[k]

N

1jj

k

1j

j

N

1jj

k

1j

N

1j

jj

avg

out

0

Y

XvarNk

Y

XNvarINL[k]var 2

32

YXY

2

Y

X

2

X

2

Y

X

Y)cov(X,2

Y

Xvar

2uk/N)k(1INL[k]var k/N)k(1[k] uINL

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ThermometerDACINL

Plot

INL ismaximumatmidscale(k=N/2=2B1)

ThisisaBrownianbridge:summationofrandomDNLs

UnlikeDNL,INL growsasBincreases.

33

1-B/2u

uuINL 2N

2

NN/21

2N[N/2]

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ThermometerDACINL

34

1runfora10bDACwithu=1%

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ThermometerDACINL

Plot

35

100runs,plotINL Matchwellwiththeory

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ThermometerDACINLYield

Questiontoask:

Wehavea8bitthermometerDACwithu =1%.WewanttheDACINLto

be

within

0.03LSB.Whatistheyieldafterfabrication? Itturnsoutthatthisisnoteasytosolveanalytically

Unlike{DNL[k]},{INL[k]}arenotindependent

Ingeneral,DACdesignerswillrelyonnumericalMonteCarlosimulations

toestimate

the

DNL/INL

yield

instead

of

solving

analytical

solutions

Thismethodisconceptuallyverysimple

ItworksforalltypesofDACs(thermometer,binary,andsegmented)

Yet

a

basic

understanding

will

be

very

helpful

for

finding

errors

in

the

simulation

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BinaryWeightedDACDNLAnalysis

{DNL[k]}aredifferentanddependontransition

Worst case:01111111 1000000

Turningoff

all

LSBs

and

turn

on

the

MSB

Forexample,B=10, u =1% DNL,worst =0.32LSB MuchlargerthanthatofthethermometerDAC(DNL=0.01LSB).

37

1-2

2i

1-2

1j

ji

1-B

B

1B

1B

II]Step[2

1-2

2i

1-2

1j

ji

avg

avg

1-B

1-B

B

1B

1B

II

II

StepStep]Step[2]DNL[2

2

u

B2

u

1B2

u

1B2

worstDNL, 12122

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BinaryWeightedDACDNL

38


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39

Anotherrun,worstDNLdoesnothappenattheMSBtransition

Duetorandomness

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40

100runs,plotDNL Matchwellwiththeory

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BinaryWeightedDACINLAnalysis

INL isthesameasthatforathermometerDAC

Why?

INLis

the

overall

deviation

from

the

ideal

straight

line

Itdoesnotmatterhowweselecttheelements

WhatisthedifferenceintheINLofabinaryweightedDAC?

TherearelargediscontinuitiesduetolargeDNLs

41

avg

out

Step

[k]I[k]IINL[k] 0

k/N)k(1[k] uINL

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BinaryWeightedDACINL

42


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BinaryWeightedDACINL

Plot

43


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SegmentedDACDNL/INLAnalysis

WorstcaseDNL

WhenallLSBDACelementsturnoffand1MSBDACelementturnson

SameDNL

as

abinary

weighted

DAC

with

Bb+1bits

INL

INL isthesameasthatofthermometerDAC

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SegmentedDACDNL

45

1runfora10bsegmentedDAC(3bMSBand7bLSB)withu=1%

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SegmentedDACDNL Plot

46

100runs,plotDNL Matchwellwiththeory

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SegmentedDACINL

47

1runfora10bsegmentedDAC(3bMSBand7bLSB)withu=1%

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SegmentedDACINL Plot

48


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Summary

Thermometer SegmentedBinary

Weighted

INL

DNL(worstcase)

u 2(Bb+1)/2u 2B/2u

#elements 2B1 Bb

+2Bt1 B

49

k/N)k(1[k] uINL

SegmentedDACingeneralachievesthebesttradeoff.

MosthighperformanceDACsadoptsegmentedDACstructure.

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FiniteOutputImpedance

Currentsourcewithfiniteoutput

resistanceR

Thenumber

of

closed

switches:

2

Vout=2

R||

AsDin increases,dothecode

widthsgetwiderornarrower?

NeedtomakeRlargeenough

Cascode

Sourcedegeneration

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O i

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Overview

Topologies


Staticerrors

Dynamicerrors


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D i DAC E

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DynamicDACErrors

DynamicDACerrorsaregenerallyhardtomodel

DACoutputiscontinuousintime,andthus,anyerroratanytime

instancecausestrouble!

Highperformance

DAC

design

is

nontrivial.

Glitchesduetotimingerrors

Currentsourcesdonotswitchsimultaneously

Clockfeedthrough

CouplingfromswitchsignalstoDACoutput

Finitesettlingtimeandslewing

FiniteRCtimeconstant

Signaldependent

slewing

Intersymbolinterference

Unmatchedrisingandfallingedges

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U f l R f

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UsefulReferences

Doris,vanRoermund,Leenaerts,WideBandwidthHighDynamicRange

D/AConverters,Springer,2006.

Bosch,Steyaert,

Sansen,

Static

and

Dynamic

Performance

Limitations

for

HighSpeedD/AConverters,Kluwer,2004.

Gustavsson,Chapter12

M.Albiol,J.L.Gonzalez,E.Alarcon,"Mismatchanddynamicmodelingof

currentsources

in

current

steering

CMOS

D/A

converters,"

IEEE

TCAS

I,pp.

159169,Jan.2004

T.ChenandG.G.E.Gielen,"Theanalysisandimprovementofacurrent

steeringDAC'sdynamicSFDR,"IEEETrans.Ckts.Syst.I,pp.315,Jan.2006.

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B i Diff ti l P i S it h

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BasicDifferentialPairSwitch

For

high

speed,

never

turn

off

the

current

source

Parasiticcapneedstoberecharged

MinimizetheswingatVx

Notdoneyet

54

Nonlinearcap

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Glitch Impulse Error

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GlitchImpulseError

Currentsourcesneedtobe

turnedon/offsimultaneously

Considerbinaryweighted

DACtransition0111 1000

Worstcaseglitchimpulsearea:

t 2B1

LSBarea:Ts

t 2B1

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DesignTechniques

Dataretiming

Useaglobalclocktoresampledatanearthecurrentcells,sothat

theyswitchsimultaneouslyindependentofencoderdelays

Makebefore

break

Ensurethatthecurrentisneverturnedoff

SandS_bar arenotsimultaneouslyoff

Lowswingdriver

Drivedifferentialpairwithlowswingtominimizecouplingfromcontrolsignalstooutput

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Data Retiming

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DataRetiming

57

UseasegmentedDACwillhelptoo.

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Make Before Break

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MakeBeforeBreak

58

Ensurethatthecurrentsourceisneverturnedoff

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Example Current Cell Implementation

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ExampleCurrentCellImplementation

[Barkin &Wooley,JSSC4/2004]

59

inarrivesfirst,

clk arriveslater

Latch

retiming

Reducedswing(nottoground)

Buffertransistor

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Overview

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Overview

Topologies


Staticerrors

Dynamicerrors


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High Performance DAC Example #1

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HighPerformanceDACExample#1

[T.Miki,Y.Nakamura,M.Nakaya,S.Asai,Y.Akasaka,andY.Horiba,An80MHz8

bitCMOSD/AConverter,IEEEJ.ofSolidStateCircuits,pp.983988,Dec.1986.]

61

2umCMOS

SegmentedDAC

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Decoder Design

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DecoderDesign

62

FastdecodingLatchretiming

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Mitigating IR Drop

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MitigatingIRDrop

63

Systematicallydecreasingcurrents

ReducingINL

INLcanbereducedbyrearrangingDNLs

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Floor Plan

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FloorPlan

[VandenBosch,JSSC3/2001]

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Measurements

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Measurements

1GHz

100MHz

66

DACtype?

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High Performance DAC Example #3

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[Schafferer,ISSCC2004]

67

Optimalswitching;noglitchatvtail

ReplicaRef.

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Measurements

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easu e e ts

[Schafferer,ISSCC2004]

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g p

[Lin,ISSCC2009]

69

Latchretiming

DACtype?

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