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 Adder (electronics)From Wikipedia, the free encyclopedia

In electronics, an adder  or summer  is a digital logic circuit that performs addition of numbers. Inmany computers and other kinds of processors, adders are used not only in thearithmetic logic units,but also in other parts of the processor, where they are used to calculate addresses, tableindices, increment and decrement operators, and similar operations.

 Although adders can be constructed for many numerical representations, such as binary-codeddecimal or  excess-3, the most common adders operate on binary numbers. In cases where twoscomplement or  ones complement is being used to represent negati!e numbers, it is tri!ial to modifyan adder into an adder"subtractor . #ther signed number representations re$uire a more complexadder.

Contents

  %hide& 

• '(alf adder 

•

)Full adder 

• 3*ore complex adders

o 3.'+ipple-carry adder 

o 3.)ookahead carry unit

o 3.3arry-sa!e adders

• 3/) compressors

• 0+eferences

• 12xternal links

Half adder%edit&

(alf adder logic diagram

he half adder  adds two single binary digits A and B. It has two outputs, sum 4S5 and carry 4C 5. hecarry signal represents an o!erflow into the next digit of a multi-digit addition. he !alue of the sumis )C  6 S. he simplest half-adder design, pictured on the right, incorporates an 7#+ gate for S andan  A89 gate for C . With the addition of an #+ gate to combine their carry outputs, two half adderscan be combined to make a full adder .%'&

he half adder adds two input bits and generates a carry and sum, which are the two outputs of ahalf adder. he input !ariables of a half adder are called the augend and addend bits. he output!ariables are the sum and carry. he truth table for the half adder is/

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Inputs Outputs

 A B C S 

0 0 0 0

1 0 0 1

0 1 0 1

1 1 1 0

Full adder%edit&

:chematic symbol for a '-bit full adder with C in and C out drawn on sides of block to emphasi;e their use in a multi-bit adder 

 A full adder  adds binary numbers and accounts for !alues carried in as well as out. A one-bit fulladder adds three one-bit numbers, often written as A, B, and C in< A and B are the operands, and C in isa bit carried in from the pre!ious less significant stage. %)& he full adder is usually a component in acascade of adders, which add =, '1, 3), etc. bit binary numbers. he circuit produces a two-bitoutput, output carry and sum typically represented by the signals C out and S,

where . he one-bit full adders truth table is/

Full-adder logic diagram

Inputs Outputs

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-bit adder with logic gates shown

It is possible to create a logical circuit using multiple full adders to add N -bit numbers. 2achfull adder inputs a C in, which is the C out  of the pre!ious adder. his kind of adder is calleda ripple-carry adder , since each carry bit ?ripples? to the next full adder. 8ote that the first4and only the first5 full adder may be replaced by a half adder 4under the assumptionthat C in = 0 5.

he layout of a ripple-carry adder is simple, which allows for fast design time< howe!er, theripple-carry adder is relati!ely slow, since each full adder must wait for the carry bit to becalculated from the pre!ious full adder. he gate delay can easily be calculated byinspection of the full adder circuit. 2ach full adder re$uires three le!els of logic. In a 3)-bitripple-carry adder, there are 3) full adders, so the critical path 4worst case5 delay is 3 4frominput to carry in first adder5 6 3' @ ) 4for carry propagation in later adders5 10 gate delays.

he general e$uation for the worst-case delay for an-bit carry-ripple adder is

he delay from bit position B to the carry-out is a little different/

he carry-in must tra!el through n carry-generator blocks to ha!e an effect on thecarry-out

 A design with alternating carry polarities and optimi;ed A89-#+-In!ert gates

can be about twice as fast.%3&

-bit adder with carry lookahead

o reduce the computation time, engineers de!ised faster ways to add two

binary numbers by using carry-lookahead adders. hey work by creating twosignals 4P  and G5 for each bit position, based on whether a carry is propagatedthrough from a less significant bit position 4at least one input is a '5, generatedin that bit position 4both inputs are '5, or killed in that bit position 4both inputsare B5. In most cases, P  is simply the sum output of a half adder and G is thecarry output of the same adder. After P  and G are generated the carries fore!ery bit position are created. :ome ad!anced carry-lookahead architecturesare the *anchester carry chain, Crent"Dung adder , and theDogge":toneadder .

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:ome other multi-bit adder architectures break the adder into blocks. It ispossible to !ary the length of these blocks based on thepropagation delay of thecircuits to optimi;e computation time. hese block based adders includethe carry-skip 4or carry-bypass5 adder which will determine P  and G !alues foreach block rather than each bit, and the carry select adder  which pre-generatesthe sum and carry !alues for either possible carry input 4B or '5 to the block,

using multiplexers to select the appropriate result when the carry bit is known.#ther adder designs include the carry-select adder , conditional sumadder , carry-skip adder , and carry-complete adder .

Lookahead carry unit%edit&

 A 1-bit adder 

Cy combining multiple carry lookahead adders e!en larger adders can becreated. his can be used at multiple le!els to make e!en larger adders. Forexample, the following adder is a 1-bit adder that uses four '1-bit As withtwo le!els of >s

Carry-save adders%edit&Main article: Carry-save adder 

If an adding circuit is to compute the sum of three or more numbers it can bead!antageous to not propagate the carry result. Instead, three input adders areused, generating two results/ a sum and a carry. he sum and the carry may be

fed into two inputs of the subse$uent 3-number adder without ha!ing to wait forpropagation of a carry signal. After all stages of addition, howe!er, acon!entional adder 4such as the ripple carry or the lookahead5 must be used tocombine the final sum and carry results.

3:2 compressors%edit&

We can !iew a full adder as a 3: lossy co!pressor / it sums three one-bitinputs, and returns the result as a single two-bit number< that is, it maps = input!alues to output !alues. hus, for example, a binary input of "0" results in anoutput of "#0#"="0  4decimal number )5. he carry-out represents bit one ofthe result, while the sum represents bit ;ero. ikewise, a half adder can be used

as a : lossy co!pressor , compressing four possible inputs into three possibleoutputs.%citation needed &

:uch compressors can be used to speed up the summation of three or moreaddends. If the addends are exactly three, the layout is known as the carry-sa!eadder . If the addends are four or more, more than one layer of compressors isnecessary and there are !arious possible design for the circuit/ the mostcommon are 9adda and Wallace trees. his kind of circuit is most notably usedin multipliers, which is why these circuits are also known as 9adda and Wallacemultipliers.

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