capacitance–voltage and impedance-spectroscopy characteristics of nanoplate eisoi capacitors

Phys. Status Solidi A 208, No. 6, 1327–1332 (2011) / DOI 10.1002/pssa.201001211 p s sa

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applications and materials science

Capacitance–voltage andimpedance-spectroscopy
characteristics of nanoplate EISOI capacitors
Maryam H. Abouzar1,2, Werner Moritz3, Michael J. Schoning1,2, and Arshak Poghossian*,1,2

1 Institute of Nano- and Biotechnologies, Aachen University of Applied Sciences, 52428 Julich, Germany2 Institute of Bio- and Nanosystems (IBN-2), Research Centre Julich GmbH, 52425 Julich, Germany3 Institute of Chemistry, Humboldt University Berlin, 12489 Berlin, Germany

Received 9 November 2010, revised 28 December 2010, accepted 3 January 2011

Published online 6 May 2011

Keywords silicon-on-insulator, SOI, nanoplate capacitive sensor, field effect, (bio-)chemical sensor, impedance spectroscopy

* Corresponding author: e-mail [email protected], Phone: þ49 2461 612605, Fax: þ49 241 6009 53235

Frequency-dependent capacitance–voltage (C–V) and impe-

dance-spectroscopy characteristics of nanoplate capacitive

field-effect electrolyte-insulator-silicon-on-insulator (EISOI)

structures with various thicknesses (30, 60 and 350 nm) of the

top p-Si layer are investigated for the first time. The frequency-

dependent C–V curves of EISOI structures show an unusual

behaviour, which significantly differs from that of conventional

EIS structures. Due to the large series resistance of the

nanoplate top Si, the C–V curves of the EISOI structures show

stronger frequency dependence in the accumulation region. In

addition, C–V curves show typical low-frequency behaviour

even at higher frequencies (up to 8 kHz). An equivalent circuit

of an EISOI structure is discussed taking into account the series

resistance of the nanoplate top Si.

� 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

1 Introduction Currently, semiconductor field-effectdevices based on an electrolyte-insulator-semiconductor(EIS) system represent one of the key structural elements forchemical and biological sensing. Sensing occurs in thesedevices by modulation of the flatband (or threshold) voltageinduced by the particular (bio-)chemical reaction at theelectrolyte/gate interface. These devices have been widelyutilized for the detection of pH value, ion concentration,enzymatic reactions, charged macromolecules, action poten-tials of living cells as well as for the creation of molecular logicgates (see e.g., [1–7]). The simplest field-effect-based (bio-)-chemical sensor is the capacitive EIS structure whichrepresents a (bio-)chemically sensitive capacitor. It isobtained from a conventional metal-oxide-semiconductor(MOS) structure by replacing the metal gate by a referenceelectrode and an electrolyte solution to be analysed. Althoughcapacitive EIS single sensors are simple in layout and easy infabrication, nevertheless, the one-chip integration of multipleEIS sensors is problematic due to technological difficulties inrealization of the electrically isolated, separate EIS capacitors.When several EIS capacitors are fabricated on a conventionalsilicon wafer, they stay interconnected through the commonsilicon substrate.

To resolve this problem, recently, we realized an array ofelectrically isolated, individually addressable nanoplatefield-effect capacitive EIS sensors using a silicon-on-insulator (SOI) wafer [8]. In these structures, the bottom Silayer serves as a substrate while the top thin Si layer is used tofabricate the nanoplate field-effect capacitors. The feasi-bility of this approach has been exemplarily demonstrated byrealizing capacitive EIS sensors (further referred to as EISOIsensors) for pH measurements as well as for the label-freedetection of charged macromolecules. In previous exper-iments, the SOI technology has been utilized for therealization of (bio-)chemically sensitive field-effect transis-tors [9–11], nanowire transistors [12, 13] and silicon thin-film resistors [14].

The capacitance–voltage (C–V) measurement is one ofthe most convenient methods to characterize field-effectcapacitive structures. While the C–V characteristics ofconventional Si-based MOS [15, 16] and EIS [17–21]structures as well as SOI-based MOS structures [22–24] havewidely been studied, to our best knowledge, no work hasbeen done on the C–V characterization of nanoplate EISOIcapacitors. In this study, frequency-dependent C–V andimpedance-spectroscopy (IS) characteristics of field-effect


1328 M. H. Abouzar et al.: Spectroscopy characteristics of nanoplate EISOI capacitorsp

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Figure 1 Scanning electron microscopy micrographs of the layerstructure of the fabricated SOI-based nanoplate capacitors withdifferent thicknesses of top Si layer of 30 nm (a), 60 nm (b), and350 nm (c), respectively.

nanoplate EISOI structures with various thicknesses of thetop Si layer are investigated for the first time. In contrast toSOI-based MOS devices, where the C–V measurements areusually performed by biasing both the front and back gates,which form two space-charge regions, the C–V and IScharacteristics of EISOI structures have been recorded byapplying a front-gate voltage between the referenceelectrode and the metal contact deposited on the uppersurface of the top Si layer. Based on these experiments, anelectrical equivalent-circuit model for nanoplate EISOIsensors has been developed. For comparison, the C–V andIS characteristics of conventional EIS structures have beenstudied, too.

2 Experimental2.1 Preparation of EIS and EISOI structures For

the fabrication of capacitive EIS structures (Al/p-Si/SiO2),30 nm SiO2 layer was thermally grown on the Si wafer(h100i, boron doped, r¼ 1–10V cm, thickness: 360Vm).After etching of the SiO2 layer from the rear surface of thewafer, a 300 nm Al was deposited as a rear-side contact layer.Then, the wafer was cut to 10 mm� 10 mm chips.

Three groups of nanoplate capacitive EISOI structureswith various thicknesses (350, 60 and 30 nm) of the top Silayer were fabricated from an SOI wafer (Soitech, France)with a buried silicon oxide (BOX) thickness of 400 nm and atop Si layer of 360 nm thickness (p-Si h100i, boron doped,r¼ 14–22V cm). For the preparation of the field-effectcapacitors with various thicknesses of the top Si layer, theoriginal top Si layer was thinned by means of partial thermalwet oxidation followed by etching the formed SiO2 layer. Asa result of this thinning process, top Si layers with differentthicknesses of 350, 60 and 30 nm have been obtained. Then, ahigh-quality thermal silicon oxide layer (30 nm) was grownon the top Si layer as gate insulator. In the next step, the topSiO2 layer was patterned by optical lithography and etched(wet etching) to open the contact windows to the top Si layer.As contact layer, a 300 nm Al layer was deposited on theupper surface of the top Si layer followed by lift-off andannealing processes. Finally, the wafer was cut to12 mm� 12 mm chips. Figure 1 shows scanning electronmicroscopy micrographs of the layer structure of thefabricated SOI-based nanoplate capacitors with differentthicknesses of the top Si layer.

2.2 Measurement set-up The developed EIS andEISOI structures have been characterized in a buffer solutionof pH 7 by means of frequency-dependent C–V and ISmethods using an impedance analyser (IM6, ZahnerElektrik, Germany). For the experiments, the EIS andEISOI chips were mounted into a home-made measuringcell, sealed by an O-ring and contacted on their front side bythe electrolyte and a conventional liquid-junction Ag/AgClreference electrode (Metrohm). The contact area of the EISand EISOI structure with the solution was about 0.65 and0.17 cm2, respectively. For the measurements, a DCpolarization voltage in the range from �4 to 3.5 V and a


small AC voltage (20 mV) of different frequencies tomeasure the capacitance of the system have been appliedbetween the reference electrode and rear-side contact of theEIS structure, or front-side contact on the upper surface ofthe top Si layer in case of the nanoplate EISOI capacitor. Theedge of the metal contact on the top nanoplate Si was about3.5 mm away from the contact area of the SiO2 gate insulatorwith electrolyte solution. The IS measurements were carriedout in accumulation, depletion and inversion regions in a

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Figure 2 (online colour at: www.pss-a.com) Frequency-depend-ent C–V curves of EISOI structures with top Si thickness of 30 nm(a) 60 nm (b), 350 nm (c), respectively, and of an EIS sensor (d).

frequency range varying from 10 Hz up to 1 MHz. Allpotential values are referred to the Ag/AgCl electrode. Thenumber of tested sensors from each group was three.

3 Results and discussion3.1 Capacitance–voltage curves The C–V curves

of the EIS sensor as well as EISOI sensors with differentthicknesses of the top Si layer of 30, 60 and 350 nm recordedin a buffer solution of pH 7 at different frequencies from 30 to1000 Hz are presented in Fig. 2.

As can be seen, at a low frequency of f¼ 30 Hz, the C–Vcurves of both the EIS and the EISOI structures show a well-known low-frequency behaviour with typical accumulation,depletion and inversion regions. The maximal capacitance inthe accumulation region is frequency-dependent, where-atwith increasing the frequency, theC–V curves shift along thecapacitance axis towards smaller maximal capacitancevalues. Moreover, this shift of the C–V curves is not parallel.This effect is a direct indication of a series resistance‘problem’ [25–28]. The nonlinear nature of the capacitancedistortion by the series resistance also changes the shape ofthe obtainedC–V plots. Similar effects have been observed inEIS structures modified with high-resistive ion-selectivemembranes [20, 21, 27, 28] as well as in MOS structures witha high-resistive substrate [25, 26].

At the same time, however, there are significantdifferences between the C–V curves of the EIS and EISOIstructure:

1. In comparison to an EIS sensor, the C–V curves of theEISOI structures possess a stronger frequency dependence inthe accumulation region. To explain this effect, an equivalentcircuit of the EISOI structure should be considered.

The complete AC equivalent circuit of capacitive field-effect devices based on an EIS system is complex andcombines components, like the bulk resistance and space-charge capacitance of the semiconductor, the contactresistance, the capacitance of the gate insulator, thedouble-layer capacitance at the insulator–electrolyte inter-face, the resistance of the bulk electrolyte solution and theimpedance of the reference electrode. However, for usualvalues of insulator thickness (10–100 nm) and electrolyteconcentration (>10�4 M) used, the interferences fromseveral components are negligible [19, 21] and theequivalent circuit of an EIS system can be simplified as aseries connection of the insulator capacitance, Ci, the space-charge capacitance of the semiconductor depletion layer(Csc), and an equivalent resistance (R¼RcþRSiþRRE),consisting of the Al–Si contact resistance (Rc), bulkresistance of Si (RSi), and resistance of the referenceelectrode (RRE). As it has been demonstrated in Refs. [20,21, 25–28], the existence of any series resistance can lead to afrequency-dependent deformation ofC–V plots of capacitivefield-effect structures and even to practically flat curves athigh frequencies.

Figure 3 depicts a schematic of the EISOI structure withthe embedded simplified equivalent circuit in the accumu-lation (a) and depletion (b) region. If a large negative

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Figure 3 (online colour at: www.pss-a.com) Schematic of anEISOI structure with embedded simplified equivalent circuit inthe accumulation (a) and depletion (b) region.

potential is applied to the reference electrode, an accumu-lation layer of positively charged holes is formed near the Si-insulator interface, and the total capacitance is determined bythe insulator capacitance, C¼Ci. The measured capacitanceCm will be given by

� 20

Cm ¼ Ci

1 þ ð2pfRCiÞ2: (1)

As far as the condition 2pfRCi� 1 is met, the measuredCm will be equal to the real capacitance. If this condition isnot satisfied, the measured capacitance in the accumulationrange will be affected by a series resistance. As a result, Cm

can be much smaller than the real capacitance of the system.For the EIS structure used in this study, RSi is very small.

The estimated values for Rc using the Al–Si specific contactresistance of 700–800V cm [15] and contact area of 1 and0.4 cm2, respectively, are about 0.7 and 2 kV for the EIS andEISOI structures. The value of RRE is in the range of5–10 kV. Thus, the frequency-dependent C–V curves of the

11 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

EIS structure will be mostly affected by the series resistanceof the reference electrode. In contrast, due to the higherresistivity and smaller thickness of the top Si layer as well asthe larger distance (3.5 mm) between the Al–Si contact andthe gate electrolyte region, the frequency-dependent C–Vcurves of the EISOI structure will be mostly affected by thelarge lateral resistance RSi, resulting in a stronger frequencydependence, in comparison to the EIS capacitor.

Similar to EIS or MOS devices, in the depletion region,the total capacitance of the EISOI structure can be modelledas series connection of Ci and the depletion capacitance, Csc.The measured frequency-dependent total capacitance in thedepletion region will be, therefore, given by

Cm ¼ Cið1 þ Ci=CscÞð1 þ Ci=CscÞ2 þ ð2pfRCiÞ2

: (2)

As the total capacitance decreases with increasing thegate voltage, the measuredCm will get closer to the real valueof the capacitance of the EISOI structure. The minimumvalue of capacitance (Cmin), is usually defined by themaximum width of the depletion layer, Wm [15, 16]:

Cmin ¼ei

d þ ðei=esÞWm

; (3)

where ei and es are the relative dielectric permittivity of SiO2

(3.9) and Si (11.9), and d is the thickness of the gateinsulator. In our EISOI structures, the thickness of the top Si(dSi¼ 30, 60 and 350 nm) is smaller than the maximumdepletion width (0.8–1mm [15]), and therefore, the top Si isfully depleted (see Fig. 3b) with Csc¼ es/dSi. Since themaximum width of the depletion layer in the top Si layer islimited by the Si thickness, a decrease of the Cmin withincreasing thickness of the top Si layer could be expected.However, this is not the case. In our experiments, due to theformation of an additional lateral depletion layer (seeFig. 3b), the maximum depletion width is not limited by thethickness of top Si layer, and will be rather defined by boththe width of the lateral depletion layer and the thickness ofthe top Si layer.

2. In contrast to an EIS sensor, which shows typical high-frequency C–V characteristics already at f> 0.5–1 kHz (seeFig. 2d), it was not possible to achieve this high-frequencyC–V behaviour in the inversion region for EISOI sensors at afrequency of f¼ 1 kHz (see Fig. 2a–c) or even at higherfrequencies (up to 8 kHz, not shown). The following twomechanisms could be responsible for such a C–V behaviourof EISOI structures:

It is known, that the frequency response of MOScapacitors in the inversion region depends on the rate (orresponse time) at which minority carriers (in our structures,electrons) can be supplied to, or removed from, the inversionlayer. If the response time of minority carriers is fast, at highfrequencies, the supply of charge carriers to the inversionlayer is sufficiently rapid and therefore, the inversion chargecan follow variations of the applied AC voltage. It has beendemonstrated that in high resistivity Si the minority carriers

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respond much faster than in low resistivity substrates [26,29]. In our experiments, the resistivity of the top nanoplate Siin the EISOI structures is several time higher than that of thebulk Si substrate in EIS structures. As a consequence, even athigh frequencies, the C–V curves of EISOI structures in theinversion region show low-frequency behaviour. Anotherexplanation could be a larger distance between the Al–Sicontact and gate-contact regions. As it has been discussed inRef. [16], for p-type field-effect devices, in which the oxidelayer extends over an area greater than the gate-contact area,the transition frequency between the low and high-frequencyC–V characteristics can be very high.

3.2 Impedance-spectroscopy characterizationThe impedance spectra for the developed nanoplate EISOIfield-effect capacitors with different thicknesses of the top Silayer were recorded in the accumulation, depletion and

Figure 4 (online colour at: www.pss-a.com) Impedance-spectro-scopycurvesofanEISOIstructurewith350 nmtopSi layer (a)andanEIS (b) structure recorded in buffer solution of pH 7 at differentapplied gate voltages.

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inversion ranges by applying different polarization voltages.As an example, Fig. 4a shows the impedance spectra of anEISOI structure with a 350 nm thick top Si layer at appliedgate voltages of�4, �0.97, 0.3 and 2 V. For comparison, theimpedance spectra of the EIS sensor recorded at polarizationvoltage of �2, �0.4 and 0.5 V are also presented (Fig. 4b).

For both structures, a linear behaviour is observed atfrequencies above 40 kHz, which bends over to a plateau ofconstant impedance at lower frequencies (<10–15 kHz).Such behaviour of the impedance curve can be assigned tothe existence of a series resistance. The impedance value inthe plateau range is about 22 and 11 kV for the EISOI and EISstructure, respectively, verifying the higher series resistanceof the EISOI structure discussed in Section 3.1.

Due to the stronger deformation of the C–V plots inthe accumulation region by the series resistance, in thefrequency range of 100 Hz–3 kHz, the impedance of theEISOI structure in the accumulation region (atVG¼�4 V) ishigher than in the inversion region (at VG¼ 2 V). However,at very low frequencies (<30 Hz), the impedance of theEISOI structure in the accumulation range becomes equal tothe impedance in the inversion range, which can be attributedto the low frequency C–V behaviour of the structure. Theseobservations are in good agreement with measured C–Vcurves of EISOI structures.

4 Conclusions The C–V and IS characteristics ofnanoplate capacitive field-effect EISOI structures withvarious thicknesses of the top p-Si layer (30, 60 and350 nm) are studied in pH buffer solution and comparedwith those of conventional EIS structures. The C–V and IScurves of EISOI structures have been recorded by applying afront-gate voltage between the reference electrode and themetal contact deposited on the upper surface of the top Silayer. Due to the large series resistance of the nanoplate topSi, the frequency-dependent C–V curves of the EISOIstructures significantly differ from the C–V plots of EISstructures. The C–V curves of the EISOI structures show: (a)a stronger frequency dependence in the accumulation region;and (b) a typical low-frequency behaviour even at higherfrequencies (up to 8 kHz). The results of IS measurementsconfirm the existence of a high-series resistance in thenanoplate EISOI structures. An equivalent circuit of anEISOI structure is discussed taking into account the seriesresistance of the nanoplate top Si.

In further works, the EISOI sensor design will beoptimized to minimize the effect of the series resistance onthe frequency dependent C–V characteristics.

Acknowledgements The authors thank S. Ingebrandt andX. T. Vu for valuable discussions, and Y. Zhang, A. Pedraza andH. P. Bochem for technical support.

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capacitance–voltage and impedance-spectroscopy characteristics of nanoplate eisoi capacitors

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