buses - york university · instructions are pipelined if the fetch-execute cycle is divided into...
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ITEC 1000 Introduction to Information Technologies
Buses
A bus is the physical connection - electrical conductors - wires or connections on printed circuit - that allow transfer of data from one spot to another
Each conductor called a line - carries and electric signal
• Data lines - carry data being moved for instance - memory to MDR
• Address lines - pass address for instance to address decoder
• Control lines - pass timing signals for data transfer and other parameters signals to and from status registers: power failure, computer error, arithmetic overflow, ...........
• Power lines - passes electrical power from one part of computer to another - USB bus carries data and power
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ITEC 1000 Introduction to Information Technologies
Bus types:
point-to-point: form specific source to specific destination - e.g. cable connecting port to peripheral device
broadcast/multipoint: sends signal to many points - but most often with code identifying desired destination - many configurations
Serialport Modem
Controlunit ALU
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Computer
CPU
Disk controller
Computer
Computer Computer
Memory
Video controller
sends signal to many points - but most often with code identifying desired destination
Broadcast/multipoint bus:
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Buses to handle peripherals
ISA (Industry Standard Architecture) bus Originated in dawn of time 1981 with 8 bit PC (XT) Latter extended to AT 16 bit architecture. Cards controlling function of different devices plugged into ISA slots users had to configure card in various ways: interrupt lines (IRQ), I/O addresses, direct memory access lines (DMA).
Now obsolete
PCI (Peripheral Component Interface): first appeared 1993 - built by Intel gradually replaced ISA and ISA related buses cards following PCI standards are plugged into slots all connected devices share same 32/64 bit signal path - a bottle neck
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PCI-E or PCIe (PCI Express):• first introduced in 2004 by Intel• replaces PCI and its upgrade PCI-X and the AGP (accelerated graphics port video bus)• built about pairs of serial(1 bit), unidirectional connections called lanes• PCI-e 1.1 (most current version 2007) each lane sends info at 250 MB/sec• architecture leads to parallelism - more than 1 pair of devices may communicate at same time
• increased bandwidth on PCI- e fast enough to replace almost all existing internal buses, including AGP and conventional PCI.
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Bus bridge
A bus bridge is a bus that connects two different types of busses
Northbridge: typically handles communications between the CPU, RAM, AGP or PCI-e, and the southbridge. Some contain integrated video controllers Also known as a Graphics and Memory Controller Hub (GMCH) in Intel systems.
Southbridge: chip that implements the "slower" capabilities of the motherboard -
I/O related functions not directly connected to the CPU.
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In personal computers frontside bus carries info between CPU and northbridge.
Depending on processor backside bus connects CPU to cache memory.
Special buses
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A bus diagram
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ITEC 1000 Introduction to Information Technologies
Motherboard pentium 4
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IDE
CNR slot
VIA VT8235
Slots in motherboard into which cables to external plug is attached
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Dual, quad, & multi core processors
2001 IBM introduced first dual-core processor. now many varieties.
• 2 complete execution cores per physical processor - each with with independent interface to system bus
• has combined 2 processors and their caches and cache controllers onto single chip• well-suited for multitasking environments • 80% faster• can handle intensive tasks in parallel - e.g. email, downloads, system updates do not slow down foreground applications• helps solve excessive heat problem of single- core processors
Common use with Intel Core Duo - first introduced January 2006
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• each core is made by different chips put together in a single package.
• must pass through frontside bus for:- communication between cores- to access data stored in cache of other core
• cores are already manufactured in only one chip.
• front side bus not necessary for communication - already built stuck together.
• memory cache is shared between the two cores.
• performance wise best option.
Two approaches to multi-chip design
multi-chip:
monolithic:
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• mix both methods.
• two monolithic dual-core chips installed together in a single package.
• cores 1 and 2 share the same memory cache, as do cores 3 and 4.
• If cores 1 or 2 needs to talk with core 3 or 4 or to access the other cache, they need to this externally, using front side bus
Quad-core CPUs from Intel
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Instruction Set Architectureor CPU Architecture
CPU architectures fall loosely into two types• CISC (complex instruction set computers) or • RISC (reduced instruction set computers)
CISC architecture exemplified by Intel x86 style processors - first Intel 8086 in 1978 with 16 bit address space occurred in first PC computers.Subsequent incarnations:
1982: Intel 80186 1982: Intel 802861985: Intel 3861989: Intel 4861993: Pentium
1995: Pentium Pro1997: Pentium II & III2000: Pentium 42006: Intel Core Duo2007: Intel Core i7
http://en.wikipedia.org/wiki/X86See:
Many other manufacturers - notably AMD
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CISC chip architecture characterized by variable length instructions.
• important for early computers with limited memory - each instruction takes up only as much space as necessary• programming done in assembly encouraged powerful easy to use instructions that could do as much work as possible• to ease compiler implementation every possible addressing mode included - hardware easier to design than compilers so complexity went into
Backward compatibility issues and success of early PCs allowed basic design to propagate past the point where initial design constraints were important
Alternative - Reduced instruction set computer (RISC)
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RISC philosophy Found that:
many complex addressing modes not used and compliers oftendid not implement them
operations using complex instructions ran slower than same operation coded by sequence of simpler operations
Goal to make instructions simple so that they could easilybe pipelined to speed up executions
Instructions are pipelined if the fetch-execute cycle is divided intostages in which more than one instruction is loaded into the pipeline at a time and more than one instruction is operated on at a time at the various stages
Variable length instructions complicate pipelining
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RISC solution -
fixed length instructionsregister intensive instructionsmemory accessible only by load and store operations
One of most successful implementations created by 1991 byApple-IBM-Motorola alliance AIM was PowerPC CPU foundin different guises in Apple Macintosh 1994-2006
Abandoned by Apple in 2006 for Intel Duo Core because ofperformance issues - heat generation, energy usage, speed
Still alive an kicking in servers for large businesses
http://en.wikipedia.org/wiki/PowerPCSee
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Input/Output
Variety of types of input and output with different non-compatible requirements and characteristics
Mouse and keyboard input - intrinsically slow - each keystroke -each mouse movement interrupts CPU with distinct fetch executecycle - referred to as programmed I/O
Data movement to and from hard drive or optical CD/DVD - occurs inbursts of large packets
Output to printer occurs bursts
Normal output to screen occurs in bursts
Video/audio input occurs in steady stream and output to screen or audio out also in steady stream
Input/output to internet occurs in bursts
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Problems to be solved
• means of addressing different devices with different requirements
• method for devices to interrupt CPU to initiate action
mouse movement - keystrokes - network - emergency status toexecuting programs or CPU itself
• method of handling different data rate requirements - can some actions be accomplished in background
• means of handling different control requirements - what aspects are in common? - to what extent can unified method be applied?
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Specific problems:
different interface hardware for different devices - data in differentformats speed incompatibilities - create problems when different devices try tooperate at same time - synchronization - buffers
allowance for steady stream input
electro-mechanical control of devices
Solution - devices have associated I/O module with specialized to meet requirements of device
Software in ROM forming hardware-independent interface between CPU and peripherals (e.g. keyboard, disk drives, video display, I/O ports) is called the BIOS = basic input output system
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I/O modules
Simple configuration -
device with dedicated module called device controller example - disk controller
Complex configuration -
I/O module which may function for one or more deviceaddressing mechanism necessary - address of module + address of associated device
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CPU I/O Module I/O Device
Simple I/O configuration
I/O
data
reg
I/O
address
reg
I/O module
I/O module
I/O
device
I/O
device
I/O
device
CPU
Complex I/O arrangement
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Interrupts
Circumstances when normal flow should be stopped and special action takenunexpected command from userunexpected external inputpower failurekeyboard inputmouse input
Solutions
Intel solution: special control lines (circuits) called interrupt lines connected to CPU - labeled IRQ0 through IRQn (IRQ = Interrupt ReQuest)Modified to handle multi-processorsPower PC solution not the same. Some operating systems prefer one or the other
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Servicing Interrupts
Interrupt causes action of a decision modulewhich decides on action - what type of interrupt.Some interrupts may mean
a message saying the computer is shutting down due to internal errorsuspension of a specific application
Complication in multi-core machines in which there ismulti-processing - more than one application running at once.Decision - which application to suspend ?
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Interrupt for external event
• temporary suspension of program in progress
• storing of all pertinent information
• branch to interrupt handler to determine action
• the subroutine (interrupt routine) for the action is executed
• control branches to program and execution continues
Example - printer out of paper
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InterruptSuspended
Special character ?
Keyboard program executring
Yes - do whatis necessary
Resume No
Add character
Keyboard interrupt
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Interrupt for controlling processes
When several applications time share - small segments of CPUtime allocated to each.An application is interrupted (put on hold) while another begun.Time between impulses of operation called quantum
Prog 1 Prog 2 Op sys
dispatcher
Clock interrupt
Clock interrupt
executing
suspended
select nextprog
execute
prog 2
suspend
prog2
select nextprog
One
quantum
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Other interruptsAbnormal events
power failureillegal instruction - divide by zero or non-existent op codedecisions - repair problem rather than stop application or shut down ? important if multi-tasking or multi-user
Software interrupts
initiated by applicationused by application to request I/O from operating systemexamples - interrupt print handler - sending email
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Multiple Interrupts and Prioritization
When interrupt occurs:For systems without dedicated lines to device - how to identify device?
Two methods:• vectored interrupt with address of device as part of interrupt signal• general interrupt is shared by all - but devices polled to see which initiated interrupt
If several interrupts are waiting to be serviced, prioritization takes place. Set by hardware or system manager Programs can temporarily disable interrupts - such an interrupt putback in queue
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Direct Memory Access (DMA)
For transfer of large amounts of data from external source - hard drive, cd/dvd, network
To happen:
• I/O interface and memory must connect • I/O module needs to simulate CPU -memory interface• handle conflicts between CPU and I/O module accessing memory - one solution being to assign different parts of memory to CPU and I/O
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For CPU to initiate direct memory transfer, I/O controller (module ) for device must be provided with:
• direction of I/O - read data from I/O device to memory or write data from memory to device
• location on I/O device from which data is to be read or to which data is to be written
• starting location for a block in memory from which data is to be written or to which data is to read
• size of the block to be transfered
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More on Buses
An external interface bus connects external device to a internal PCI or ISA bus and hence to CPU if necessary
Parallel bus - separate lines - as many as 64 - for • each bit of a block of data• each of address if there is one• each control bit
Uses - advantages -
• fast because of block transfer• common as internal buses within computer, - between CPU and memory - between CPU and high speed devices
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Disadvantages of parallel bus
• expensive because of multitude of wires• reliable over short distance - long parallel cables susceptible to electronic interference between wires.
Serial bus
• data transfered serially one bit at a time• few lines necessary - at most one for data and perhaps to for control• cheap• reliable• good over longer distance• fast enough - especially with current tweaking
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Specific external interface buses and ports
The external interface bus for a given device can be considered to be -
the wire connecting the device to the computerthe plug-in connector or portassociated I/O module which may contain software called port controllerconnection of I/O module to internal PCI bus
Often some device control is built into the device itselfComputer software programs that control I/O module software - often called device drivers
The words serial port and parallel port refer to special connectors on the back of a PC - a serial port usually connects a serial bus and a parallel port to a parallel bus
Both now obsolete - parallel ports for old style printers - serial ports for mouse & keyboard
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typical 9 pin serial port connector with pin description
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A typical parallel port -
has a 25 pin connector on the back of the computer allows input up to 9 bits - output up to 12 bitcomposed of 4 control lines, 5 status lines, 8 data lines
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Universal Serial Bus (USB)
Intended to replace variety of older serial and parallel interfaces for:mouses(mice), keyboard, printers, cameras, scanners, gamepads, joysticks ...
• Has gone through improvements - USB 1.0 - Jan 1996 - 12 Mbits/s = 1.5 MB/sUSB 2.0 - April 200 - 480 Mbits/s = 60 MB/sUSB 3.0 - standard approved August 2008 - 4.8 Gbits/s = 600 MB/s
• multi-point bus - host controller (I/O module) connects to a root hub from which other hubs or devices can be connected in hierarchical order - further down tree less the default priority
• data transfered in packets - each contains identity of destination and small piece of data.
• USB protocol has packets scheduled for delivery at regular intervals i.e. isochronous transfer
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A USB system has an asymmetric design, consisting of a host, a multitude of downstream USB ports, and multiple peripheral devices connected in a tiered-star topology. Additional USB hubs may be included in the tiers, allowing branching into a tree structure with up to five tier levels. A USB host may have multiple host controllers and each host controller may provide one or more USB ports. Up to 127 devices, including the hub devices, may be connected to a single host controller.
USB devices are linked in series through hubs. There always exists one hub known as the root hub, which is built-in to the host controller. So-called "sharing hubs", which allow multiple computers to access the same peripheral device(s), also exist and work by switching access between PCs, either automatically or manually. They are popular in small-office environments. In network terms, they converge rather than diverge branches.
A physical USB device may consist of several logical sub-devices that are referred to as device functions. A single device may provide several functions, for example, a webcam (video device function) with a built-in microphone (audio device function).
USB endpoints actually reside on the connected device: the channels to the host are referred to as pipes.USB device communication is based on pipes (logical channels). Pipes are connections from the host controller to a logical entity on the device named an endpoint. The term endpoint is occasionally used to incorrectly refer to the pipe. A USB device can have up to 32 active pipes, 16 into the host controller and 16 out of the controller.
Each endpoint can transfer data in one direction only, either into or out of the device, so each pipe is uni-directional. Endpoints are grouped into interfaces and each interface is associated with a single device function. An exception to this is endpoint zero, which is used for device configuration and which is not associated with any interface.
When a USB device is first connected to a USB host, the USB device enumeration process is started. The enumeration starts by sending a reset signal to the USB device. The speed of the USB device is determined during the reset signaling. After reset, the USB device's information is read by the host, then the device is assigned a unique 7-bit address. If the device is supported by the host, the device drivers needed for communicating with the device are loaded and the device is set to a configured state. If the USB host is restarted, the enumeration process is repeated for all connected devices.
The host controller polls the bus for traffic, usually in a round-robin fashion, so no USB device can transfer any data on the bus without an explicit request from the host controller.
The following overview of USB protocol is fromhttp://en.wikipedia.org/wiki/Universal_Serial_Bus
This entire wiki web page is supplementary reading
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IEEE 1394 Serial Bus
• Different implementations -different names -
Apple - FireWireSony - I.LINKTexas Instruments - Lynx
• Initiated by Apple as replacement for parallel SCSI (small computer system interface) bus providing connectivity for audio and video.
• FireWire 400 (1995) or IEEE 1394 -1995) allows max of 12 MB/s.
• FireWire 800 (IEEE 1394b-2002) - allows max of 100 MB/s
• FireWire S1600 & S3200 - still on drawing board - will provide 1.6 Gbits/s and 3.2 Gbits/s or 200 and 400 MB/s - slower than USB 3.0
Many of characteristics of USB
Unlike USB - FireWire allows networking
IEEE = Institute of Electrical and Electronics Engineers
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http://en.wikipedia.org/wiki/Network_card
Further reading
http://www.intel.com/technology/itj/2006/volume10issue02/art01_Intro_to_Core_Duo/vol10_art01.pdf
http://en.wikipedia.org/wiki/SCSI
http://hubpages.com/hub/after-silicon
http://en.wikipedia.org/wiki/Multi-core
http://en.wikipedia.org/wiki/AT_Attachment
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