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7/24/2019 BTech & MTech VLSI PBTech & MTech VLSI Projectsrojects

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M. Tech VLSI ProjectsIEEE 2014

S.No Project Titles YEAR /Month

EVD_001 Low-Power and Area-Efficient Carry Select Adder Jan 2014

EVD_002 Design of Dedicated Reversile !"ant"# Circ"itry for S$"areCo#%"tation

Jan 2014

EVD_003 Ra&or 'ased Progra##ale (r"ncated )"lti%ly and Acc"#"late*Energy-Red"ction for Efficient Digital Signal Processing

Jan 2014

EVD_004 A Deci#al+'inary )"lti-o%erand Adder ,sing a ast 'inary toDeci#al Converter

Jan 2014

EVD_005 All .%tical Reversile )"lti%le/er Design "sing )ac-endernterfero#eter

Jan 2014

EVD_006 )e#ory oot%rint Red"ction for Power-Efficient Reali&ation of 2-D inite #%"lse Res%onse ilters

Jan 2014

EVD_007 Designing 3ardware-Efficient i/ed-Point R ilters in anE/%anding S"e/%ression S%ace

Jan 2014

EVD_008 Area-Delay-Power Efficient i/ed-Point L)S Ada%tive ilter itLow Ada%tation-Delay

e 2014

EVD_009 Low 5 Power Digital signal Processor Arcitect"re for wirelesssensor 6odes

e 2014

EVD_010 (i#e-'ased All-Digital (ecni$"e for Analog '"ilt-in Self-(est e 2014

EVD_011 Analysis and Design of a Low 5 voltage Low 5 Power Do"le (ailCo#%arator

e 2014

EVD_012 A new ydrid #"lti%lier "sing Dadda and allace #etod e 2014

EVD_013 Parallel #"lti%lier 5 acc"#"lator ased on radi/- 2 #odified 'ootalgorit# y "sing a 7LS arcitect"re

e 2014

EVD_014 "lly Re"sed 7LS Arcitect"re of )0 + )ancester encoding,sing S.LS (ecni$"e for DSRC A%%lications

e 2014

EVD_015 Reverse Converter Design 7ia Parallel 5 Prefi/ Adders8 6ovelCo#%onents* )etodlogy * and #%le#entations

e 2014

EVD_016 'it 5 Level .%ti#i&ation of Adder 5 (rees for )"lti%le Constant

)"lti%lications for Efficient R ilter #%le#entation

e 2014

EVD_017 #%le#entation of floating %oint )AC ,sing Resid"e 6"#erSyste#

e 2014

EVD_018 4-2 Co#%ressor Design wit 6ew 9.R-96.R )od"le e 2014

EVD_019 Reali&ation of 284 reversile decoder and its a%%lication e 2014

EVD_020 6ovel ield :Progra##ale ;ate Array Arcitect"re forCo#%"ting te Eigen 7al"e Deco#%osition of Para 5 3er#itianPolyno#ial )atrices

)ar 2014


2/5

EVD_021 Data Encoding (ecni$"es for Red"cing Energy Cons"#%tion in6etwor< :on :ci%

)ar 2014

EVD_022 Low-Co#%le/ity Low-Latency Arcitect"re for )atcing of DataEncoded wit 3ard Syste#atic Error 5 Correcting Codes

)ar 2014

EVD_023 A Synergetic ,se of 'loo# ilters or Error Detection and

Correction

)ar 2014

EVD_024 3;3 SPEED 7EDC ),L(PLER DES;6SA RE7E )ar 2014

EVD_025 3ig- (ro"g%"t )"lti Standard (ransfor# Core S"%%orting)PE;+3=2>4+7C-1 ,sing Co##on Saring Distri"tedArit#etic

)ar 2014

EVD_026 !"aternary Logic Loo


3/5

EVD_046 Reviewing 3ig 5Radi/ Signed - Digit Adders J"ne 2014

EVD_047 Area 5 Delay 5 Power Efficient Carry 5Select Adder J"ne 2014

EVD_048 )etod for designing )"lti-Cannel R6S Arcitect"res to %reventPower Analysis SCA

J"ne 2014

EVD_049 An .%ti#i&ed )odified 'oot Recoder for Efficient Design of te

Add- )"lti%ly .%erator

J"ly 2014

EVD_050 Energy Efcient Programmable MIM !eco"er#ccelerator $hi% in &'(nm $MS

J"ly 2014

EVD_051 Precise 7LS Arcitect"re for A 5 'ased 1-D+2-D Da" ->avelet ilter 'an< wit Low Adder - Co"nt

J"ly 2014

EVD_052 A )etod to E/tend .rtogonal Latin S$"are Codes J"ly 2014

EVD_053 Low 5 Power Progra##ale PRP; it (est Co#%ressionCa%ailities

J"ly 2014

EVD_054 Efcient )P*# an" #SI$ +eali,ations o- a !#(ase"+econ/grable )I+ !igital )ilter

J"ly 2014

EVD_055 6ovel S$"are root algorit# and its P;A #%le#entation J"ly 2014

EVD_056 3ig 5 (ro"g%"t ("ro Decoder wit Parallel Arcitect"re forL(E ireless Co##"nication Standards

A"g" 2014

EVD_057 ast Radi/ -10 )"lti%lication ,sing Red"nant 'CD A"g"2014

EVD_058 A %arallel radi/ 5sort 5ased 7LS arcitect"re for finding te first #a/i#"#+#ini#"# val"es

A"g"2014

EVD_059 Perfor#ance Analysis of te CS-DCS +'PS Co##"nicationSyste#

Se% 2014

EVD_060 7LS Design of a Large 5 6"#er )"lti%lier for "lly 53o#or%ic Encry%tion

Se% 2014

IEEE 201 2012

S.No Project Titles 3E#+

EVD_061 3ig-S%eed Low-Power 7iteri Decoder Design for (C) Decoders 201

EVD_062 Efficient )aKority Logic a"lt Detection it Difference-Set Codesfor )e#ory A%%lications

201

EVD_063 Soft-Error-Resilient P;As ,sing '"ilt-n 2-D 3a##ing Prod"ctCode

2012

EVD_064 Error Detection in )aKority Logic Decoding of E"clidean ;eo#etry

Low Density Parity Cec< GE;-LDPCI Codes

201

EVD_065 )"lti o%erand Red"ndant Adders on P;As 201

EVD_066 Data Encoding Sce#es in 6etwor


4/5

EVD_070 Low Co#%le/ity Digit Serial Systolic )ontgo#ery )"lti%liers orS%ecial Class .f ;G2)I

201

EVD_071 S%lit-%at "sed loating Point )"lti%ly Acc"#"late GP)ACI= 201

EVD_072 Design of Digit-Serial R ilters8 Algorit#s* Arcitect"res* and aCAD (ool=

201

EVD_073 Low Power and Design Reed 5Solo#on Encoder 201EVD_074 A S%"rio"s-Power S"%%ression (ecni$"e for )"lti#edia+DSP

A%%lications G)ACI2011

EVD_075 Digital ilter #%le#entation 'ased on te R6S wit Di#inised-1Encoded Cannel

2012

EVD_076 Low Power >4it )"lti%lier Design y 7edic )ate#atics 201

EVD_077 7LS i#%le#entation of ast Addition "sing !"aternary Signed Digit6"#er Syste#

201

EVD_078 An Efficient 3ig S%eed allace (ree )"lti%lier 201

EVD_079 Low Latency Systolic )ontgo#ery )"lti%lier for finite ield ; G2#I'ased on Pentano#ials

201

EVD_080 Radi/-4 and radi/- oot encoded #"lti-#od"l"s #"lti%liers 201

EVD_081 7iteri 'ased Efficient (est Data Co#%ression 201

EVD_082 C.RDC Designs for i/ed Angle of Rotation 201

EVD_083 Prod"ct codes of )LC 6A6D las )e#ories 201

EVD_084 Pi%elined Parallel ( Arcitect"res via olding (ransfor#ation 2012

EVD_085 3ig S%eed Parallel Deci#al )"lti%lication wit Red"ndant nternalEncodings

201

EVD_086 Scalale Digital C).S Co#%arator ,sing a Parallel Prefi/ (ree 201

EVD_087 Design and #%le#entation of 3ig-S%eed and Energy-Efficient7ariale-Latency S%ec"lating 'oot )"lti%lier G7LS')I=

201

EVD_088 6ew 3ig-S%eed )"ltio"t%"t Carry Loo


5/5

(ro"g Sce#e

EVD_100 Constant Delay Logic 201

EVD_101 Parallel AES Encry%tion Engines for )any- Core Processor Arrays= 201

EVD_102 (oe%lit& )atri/ A%%roac for 'inary ield )"lti%lication ,sing!"adrino#ials

2012

EVD_103 7LS Arcitect"re of Arit#etic code "sed in SP3( 2012

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