board designer addon

CR-5000 Board Designer Add on Rev. 10.0

Chapter 1 Artwork

1-1 Potential Distribution 1-2 Fillet/Chamfer 1-3 Improvement of inputting tangent arc 1-4 Construction Line command 1-5 Improvement of Generate Offset Figure

1-1 Potential distribution Potential distribution

Summary When user ships their products especially to abroad, they have to pass a screening of safety standard (for example, US Standards.) To pass it, they have to prepare documentation and to show that adjacent patterns have enough clearance. To make this documentation easily, new command is released as optional tool.

Function <Main function> � Measure the minimum length between a pair of adjacent patterns. � Display the measured point with dimension arrow and label on canvas. � List the result from the measuring. � Edit the list � Export the list into an ASCII file (CSV). � Output dimension arrow and label into document layer. <Operation> 4. Set the net voltage and the clearance by electric potential difference if

necessary. 5. Launch the command.

Artwork Tool, Utilities � Potential distribution. 6. Set the condition to measure. A : Calculate

If you set a value here, it checks pairs only whose clearance are narrower than the length you set. If the check box Check Area is off, it checks all pairs. The smaller value you set, the faster the check goes.

B : Layer Outer Layer : Top/bottom layers are checked. All Layer : All layer, top, bottom, and inner, are checked.

7. Measure. Click Check Execute. Conductive figures on target layer and

New

A

B

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plating holes are checked. Each pair of nets can be checked on each layer. After Check Execute, dimension arrow is displayed.

NOTE : 1. When checking, the construction point in each object is referred

to measure the clearance. Therefore, it happens not to measure the narrowest point.(Refer the label 11 above picture.)

2. If a pair has the minimum clearance points more than one, it is indefinite which point is picked up.

8. Edit the list. Enter the value for the following items. � Measured E-Potential (actual number more than zero) � Judgment (OK/NG/Ignore/Not Set) � Comment (text string)

There are some tools to edit the list. Exchange nets To exchange nets, click Exchange Net in the assist menu. Set items to display It is possible to choose items to display by layers and by judgment.

Click

5

Zoom To zoom one point, double-click a net name. Sort To sort the list, use Sort in the assist menu. 9. Export the list to CSV.

Set items to display. When you click Export CSV button, the current content in the table is exported.

Double-click

Click

Set

Click

6

10. Output dimension arrow and label into document layer. 1. In the list dialog, select the layer and judgment you want to generate

dimension arrows for. 2. Set the parameters for dimension arrow and text. 3. Preview it. 4. Select the layer to output arrows. 5. Output.

11. Save the result (this is done automatically.)

When you exit the command, a result file (PCB_name.vmr) is created automatically in the directory where PCB/RUL are located. Next time you launch the tool, this file is loaded and dimension line and label are displayed on canvas. The content of the list also is loaded. NOTE : 1. If the result file is older than the current design

(PCB/RUL), it cannot be checked. 2. Net color is not saved in the result file.

1 2

3

4

5

7

1-2 Fillet/Chamfer Fillet/Chamfer

Summary Fillet/Chamfer command is now available for area and line. <Fillet> A: Change corner to tangent arc with specified radius. B: Change tangent arc and arc to specified radius. C: Change tangent arc and arc to corner. D: Change chamfer to tangent arc <Chamfer> A: Chamfer corner with specified cut length. B: Chamfer corner of tangent arc or arc corner with specified cut length. C: Change the cut length of chamfer. D: Change a chamfer to corner.

New

B A

D C

DC

BA

8

<Target object> � Area � Line � Component Area � Height Limit Area � RulesByArea <Related tool> � PC Board Shape Edit � Artwork � Panel � Pad Canvas Editor � Footprint Editor

Function <Operation> 1. Launch the tool. Edit � Fillet/Chamfer, or click . 2. Set the parameter.

Radius / Cut Length If you have specified Min Radius/Min Length and you set a smaller value for Radius/Cut Length, the Min Radius/Min Length is changed to the Radius/Cut Length value. Min Radius / Min Length If the radius/cut length needs to be corrected to execute Fillet/Chamfer, this value is referred. If the radius/cut length is corrected to the smaller value than this setting, Fillet/Chamfer is not executed. If you set a greater value for Min Radius/Min Length than Radius/Cut Length, the Radius/Cut Length is changed to the Min Radius/Min Length value.

<Fillet> <Chamfer>

Radius Cut Length

9

Tangent Arc and Arc Only (Fillet only) If you check this ON, Fillet works on tangent arc and arc. It does not work on corner.

3. Click the object, or Select them by Frame Select.

Note <Fillet> � If the apex of arc is not on the cross-point of both lines, it cannot be a

target. � If fillet cannot be generated with the radius you set, because of the

distance between a target and the construction point, the radius is decreased.

� In BD and BP, if you run Fillet on a square line, the line changes to a

round line. � In Footprint Editor, if a figure is set pin, fillet is not generated. � If the radius gets less than half of line width and/or outline width of the

object after generating/changing fillet, fillet is not generated. � It is impossible to fillet the start-end point of a closed line. � If any part gets narrower than the outline width of the area, it behaves

according to the setting in board.rsc. If any figure cannot exist after correcting, fillet is not generated and an error message appears.

Tool Resource file Keyword

BP, BP board.rsc photoErrorSurface Pad Canvas Editor pad.rsc Pad*photoErrorSurface Footprint Editor footprint.rsc Footprint*photoErrorSurface

2

<Target> < Not Target>

Start-end point.

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<Chamfer> � The target corner should consist of two lines whose relative degree is 90. � If the apex of arc is not on the cross-point of both lines, it cannot be a

target. � If chamfer cannot be generated with the cut length you set, because of the

distance between a target and the construction point, the cut length is shortened.

� If a target corner has a tangent arc, a chamfer is generated leaving the tangent arc as it is.

� If the length of the target corners is shorter than twice the cut length,

chamfer is generated with the half of the line length. � In BD and BP, if you run Fillet on a square line, the line changes to a

round line. � In Footprint Editor, if a figure is set pin, fillet is not generated. � It is impossible to chamfer the start-end point of a closed line. � If the line has different widths in it, the line width of the line that is drawn

first applies to the chamfer part. � Generate/Change by Frame Select works for apex and tangent arc only.

It cannot be used to chamfer arc or to change cut length of chamfer part.

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<Target> <Not Target>

11

� Delete by Frame Select works for chamfer part that consists of vertical, 45 degree, and horizontal lines.

� Even if a chamfer part has tangent arc, the cut length can change.

However, the tangent arc become apex. � If the cut length gets less than half of line width and/or outline width of the

object after generating/changing fillet, fillet is not generated. � If any part gets narrower than the outline width of the area, it behaves

according to the setting in board.rsc. If any figure cannot exist after correcting, chamfer is not generated and an error message appears. (Please refer to the Note-Fillet.)

Resource File <parameter.rsc>

Item Keyword Value Default/ If omitted

Common Procedure Artwork.FilletChamfer.process Generate/Delete Generate Fillet Radius Artwork.Fillet.radius 0<Real value <=19900(mm) 1.0 Specify Min Radius Artwork.Fillet.checkminradius on/off off Min Radius Artwork.Fillet.minradius 0<Real value <=19900(mm) 1.0 Tanget Arc and Arc Only Artwork.Fillet.target All/ArcOnly All Chamfer Cut Length Artwork.Chamfer.cutlength 0<Real value <=19900(mm) 1.0 Specify Min Length Artwork.Chamfer.checkminlength on/off off Min Length Artwork.Chamfer.mincutlength 0<Real value <=19900(mm) 1.0

<pad.rsc/footprint.rsc>

Item Keyword (XXX=Footprint or Pad)

Value Default/If omitted (In( ), value for pad)

Common Mode XXX*filletChamferMode Fillet/Chamfer Fillet Procedure XXX*filletChamferProcess Generate/Delete Generate Fillet Radius XXX*filletRadius 0<Real value <=19900(mm) 1.0 (0.1) Specify Min Radius XXX*filletCheckMinRadius ON/OFF OFF Min Radius XXX*filletMinRadius 0<Real value <=19900(mm) 1.0 (0.1)

Generate chamfer Delete them by Frame Select

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Tangent Arc and Arc Only

XXX*filletTarget All/ArcOnly All

Chamfer Cut Length XXX*chamferCutLength 0<Real value <=19900(mm) 1.0 (0.1) Specify Min Length XXX*chamferCheckMinLength ON/OFF OFF Min Length XXX*chamferMinCutLength 0<Real value <=19900(mm) 1.0 (0.1)

1-3 Improvement of inputting tangent arc Improvement of inputting tangent arc

Summary In PWS, there is a function to make the following tangent arc. When you select a circular object and line, the function connects them with tangent arcs, and the line is trimmed. It is also possible to generate an area between tangent arcs at the same time. In Rev.8, this function is available in Board Designer. It may be very effective for flexible PCB design. <Effective tool> � Board Outline Tool � Artwork Tool � Panel Tool

Function <Operation> 4. Select Input � Line, Arc, or Input � Documentation � Line, Arc.

Improved

Reference circle

Reference line Originating point

Arc

Reinforcing area

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And select Double Tangent Arc from Pointing Mode. 5. Set the radius.

The value should be larger than the radius of reference circle. Otherwise it is impossible to select a reference circle that has a larger radius than this setting. The originating point is the point where the two object are crossed, the reference line and the circle whose radius is the value you set here and whose center point is the center point of the reference circle. The reference line is trimmed at this originating point. The originating point is used as the connecting point of arc and reference line.

6. If the reference circle is included in a padstack, select the layer on which the reference circle is.

7. If you want to generate a reinforcing area, turn Generate Surface on. The property of reinforcing area Property Property/value to refer

Layer The layer where the reference line is on. Outline width The outline width of the reference line. Paint. width The paint width of the reference line. Paint angle The angle is defined as follows (red arrow).

8. Select a reference circle on canvas. You may select arc or tangent arc of the following objects. � Line � Area � Meshplane � Component area � Height Limit Area � RulesByArea � Round hole

4 3

2

1

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� Pad � Pad included in a padstack � Hole included in a padstack

9. Select a reference line on canvas. It is impossible to select a line as a reference line if; � The line touches the reference circle. � The distance from the center point of the reference circle to the

line is the value you set as Radius. <Direction of arcs and trimming> Where you click on the reference line defines the direction of arcs and the trimming.

Note � The arcs are generated with round pen type. � If the line cannot be edited, it cannot be a reference line. � When select a reference line, edge point only (Start/End point) can be

selected. � If you select a line contains more than two points for a reference line, the

edge side is trimmed regardless of where you click.

5

6

Yes No

Click1 Click2 Trimmed

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1-4 Construction Line command Construction Line command

Summary The new command Construction Line allows you to generate line that works as an assistant line when you create figures. Construction line are generated on document layer of active layer. <Effective tool> � Board Outline Tool � Artwork Tool � Panel Tool

Function To launch the command, Utility � Construction Line, or click the icon. <Drag> This mode allows you to input a line as dragging it.

New

A

B

C

D

E

F

<Input/Edit Tool Box>

Pitch = 3

Generate Count = 2

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A: Select Reference Segment If this setting is on, the angle of the reference segment is used when construction line is input. the first click selects a reference segment, and the second click inputs a construction line. If this setting is off, the first click inputs a line. B: Horizontal To input a horizontal construction line, turn this on. C: Offset To input offset line(s), turn this on. Set the direction, pitch, and the generate count.

Direction Plus: Generate offset line above the horizontal line. Minus: Generate offset line below the horizontal line. Both: Generate offset lines above/below the horizontal line.

D: Vertical To input a vertical construction line, turn this on. E: Offset To input offset line(s), turn this on. Set the direction, pitch, and the generate count.

Direction Plus: Generate offset line on the right side of the vertical line. Minus: Generate offset line on the left side of the vertical line. Both: Generate offset lines on the both sides of the vertical line.

F: Rotate To input a construction line with rotating, turn this on. Set the angle to rotate. NOTE : � If Select Reference Segment is set on, the fillet line is recognized as

follows (the red parts).

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<2 Points> This mode allows you to specify the number and the pitch of construction lines between the specific two points. A: Generate Count Specify how many lines you want to generate. B: Pitch If you generate more than one line, specify the distance between each construction lines. C: Snap to Data If you turn this on, the 1st and 2nd click are snapped to a line segment. The target should be; � Area � Line � Component Area � Height Limit Area � RulesByArea � Meshplane D: Angle Mode � Horizontal Line To input horizontal construction line, select this mode. � Vertical Line To input vertical construction line, select this mode.

A

B

CD

E

F

Click 1

Click 2

Pitch = 3

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� Parallel Line To input parallel line between any two points, select this mode.

� Parallel to Snapped Segment = ON If Snap to Data is ON, this mode generates construction line that parallels to the line segment to which your click is snapped. If both your 1st and 2nd click are snapped to lines, the construction line parallels to the 1st line you clicked.

� Parallel to Snapped Segment = OFF This mode generates vertical construction line to the line between two points you click.

� Specify Angle To input construction line with specified angle, select this mode. NOTE : � The pitch is referred if Generate Count is more than one. � Snap to Data can be toggled any time. � If Select Reference Segment is set on, the fillet line is recognized as

follows (the red parts). (Please see the NOTE for Drag mode.) <Delete All> Delete all construction lines on active layer. NOTE : If a construction line is moved or copied to data layer from document layer, it cannot be deleted with this command. <Broken Line> You can choose the line type for construction line. � Table

Specify the document line property (Artwork.DocumentLineTable) that is loaded from parameter.rsc.

� Specify Broken Line ON : Input solid line. OFF : Input broken line.

Resource file parameter.rsc The first keyword is “Artwork”, and the second one is “ConstuctionLine”. <Drag>

Parameter Value If omittedSelect Reference Segment specifybasis on/off off Horizontal Line generatehorizontal on/off off

Dash1 Dash2

Spacing

Dash1 Dash2

Spacing

Dash1 Spacing

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Offset dohoroffset on/off off Direction hdirection plus/minus/both plus Pitch horpitch 0<Real value <=19900(mm) 1.0 Generate Count horcountdrag 0<Integer <=19900 1 Vertical Line generatevertical on/off off Offset doveroffset on/off off Direction verdirection plus/minus/both plus Pitch verpitch 0<Real value <=19900(mm) 1.0 Generate Count vercountdrag 0<Integer <=19900 1 Rotate dorotate on/off off Rotation Angle rotateangle 0.0<Real value<360.0 45.0 <2 Points>

Parameter Value If omitted Generate Count countbetween 1<Integer <=19900 1 Pitch pitchbetween 0<Real value <=19900 1.0 Snap to Data datasearch on/off off Angle Mode kindbetween horizontal/vertical/

parallel/specifyangle horizontal

Parallel to Snapped Data paralleltodata on/off off Abs. Angle absangle 0<=Real value <180 0.0

1-5 Improvement of Generate Offset Figure Improvement of Generate Offset Figure

Summary Formerly, when generating an offset figure for closed figure, it can't generate offset figure across start/end points. From Rev.8 it can generate offset figure across them.

Start Point of the line

Improved

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Function When specify the section, Another is available to change the section. Then an offset figure is generated for the start/end point.

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Chapter 2 Placement/Wiring

2-1 Star Point design 2-2 Star Point design routing 2-3 Auto Surface correction (Templates) 2-4 "Embedded Router" supports Templates

2-1 Star- Point design Star-point design

Summary Star-point functionality allows you to connect different nets without DRC error at the same position. To realize this functionality, a component called “Star-point component” is used.

Function � It is possible to specify the different nets to connect at the same

position in the schematic. � DRC error does not occur when connecting the specified different nets. � It is possible to route the specified different nets into the star-point

while on-line DRC is ON. � DRC error occurs when the specified different nets are connected

outside the star-point. � It is possible to define a component pin as a star-point during layout.

Design flow 10. Register CDB

6. Register a footprint. Pin The star-point pins consist of one padstack and virtual pad(s). A single padstack is used as a pin, and the other virtual pads are used as the other pins. They are placed overlapping at the same position. Inner-layer component attribute Component area is unnecessary for a star-point component.

Footprint attribute Value placeLayerNo 0

7. Register a function and pin assignment. If different nets are connected at the same position in layout, but they should be separated in the schematic, it is necessary to register function and pin assignment. If five nets are connected at two positions separately;

New

Virtual pads

Padstack

<In the case of 4 pins>

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8. Register a part Part Kind Printed Part Pin count Specify the number of different nets to connect together. It is necessary to register parts for each number of pins. Pattern Part Type To define the part as a star-point component, the attribute should be set.

Part attribute Value patternPartType star_point

11. Design schematics. Use a star-point to connect different nets. NOTE: Use star-point component that has as many pin as you need to connect. Connect all star-point pin to net and do not leave any pin no-net.

12. Place star-point in layout Place star-point component in layout. It is possible to place it on the component pin. Therefore the component pin works in the same manner as a star-point. NOTE about through hole : It is possible to use through hole padstack as a star-point. If this star-point is placed on a component pin which is also a through pin, the holes are duplicated. In this case, it is necessary to replace the star-point with another padstack which is “through” and “no-hole” manually. “Through” and “no-hole” padstack does not have a hole but it enables the connection between layers. Board Designer recognizes this as connected even though it is not connected when board manufacturing. Please use this padstack with caution. Currently there is no way to check it by Board Designer.

13. Move star-point pin between layers If necessary, move star-point pin between the layers.

14. Route pattern into a star-point.

GND1, GND3, GND4

GND2

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DRC/Land status <Setting environment – board.rsc> The following parameter should be set for star-point design. board.rsc

Parameter Value If omitted starPointDesign on/off off <DRC> Clearance/short errors are ignored if the conductive figure of a star-point net approach/overlaps with other star-point nets within the star-point area. The following table shows the manner of DRC for the specified different nets within the star-point area. Layout area/in-component Line Area/meshplane Pad Pad in padstack

Line No err Short err No err No err Area/meshplane - Short err No err No err Pad - - No err No err

Layo

ut

area

/in-

com

pone

nt

Pad in padstack - - - No err Example; Line against line Area against area <Land status> The land status changes automatically if the net connects with a star-point that the net belongs to.

No error No error No error

Error

Error Error Error Error

N2

N1 N4N3

N2

N3N4N1

In the case of using line The land status of layer 2 changes to“Connect”.

In the case of using area in a mixed layer The land status of layer 2 changes to“Thermal”.

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2-2 Star-point design – Routing Star-point design – Routing

Summary This chapter describes the manner of routing functionality such as Input Wire, Input Area, and Area DRC etc. to support star-point design

Area DRC/Clearance check <Function> Star-point component (star-point) enables a connection between different nets. Area DRC should ignore a clearance/short error if the different nets are specified to connect to the same star-point. Area DRC is ignored in the following case; � Pin – Pin within star-point � Pin within star-point – Pattern of different net to connect to that star-point � Pattern – Pattern that are different nets and connect to the same

star-point

N1

N2

N3N4 In the case of using area in a mixed layer

The land status of layer 2 and 3 changes to“Thermal”.

New

Pin of netA Pin of netB

Pin of netA Pin of netB

netA

Line (netA) Line (netB)

ErrorNo Error

Error

Area Line

Error

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� Pin on which a star-point is placed – Pattern of different net to connect to

that star-point <Note> � Performance may get worse in the case of setting star-point. � When you place a star-point at the position where the lines causes short,

the DRC error mark does not disappear. � If you place a star-point on another star-point, DRC error occurs. � Regarding star-point, Area DRC supports “Normal Clearance” and

“In-component”.

On-line DRC during Input Wire <Function> Input Wire supports the following case; � Input line on a star-point � Input line into a pin on which a star-point is placed. � Input via on a star-point � Input via on a pin on which a star-point is placed

If a SMD pin and star-point are placed together, the SMD pin is treated as a star-point.

Star-point SMD pin

No Error

Star-point (netA, netB)

SMD pin (netB)

Line (netA)

netA netB

netA

netB

It is possible to input a line of netA

Line (netB) Star-point (netA, netB) SMD pin (netA)

netA netB

Via

Star-point (netA, netB) SMD pin (netA)

Line (netB)

Via

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<Note> � The program see the whole of the line to determine if a star-point

connects to an existing line of a different net. Therefore in the following situation, on-line DRC happens to allow you to input wire crossing on the existing line.

� If a pattern is spread by Spread mode, the pattern does not take account

of a star-point. � On-line DRC – Resist does not take account of star-point. � Shape – SemiAuto does not take account of star-point.

On-line DRC during Input Area(Conductive) <Function> Input Area supports the following case; � Input area on a star-point � Input area on a star-point on that a pattern of a different net has already

routed. � Generate thermal line � Input area on a pin on which a star-point is placed.

Line (netA) Line (netB)

netA, netB

netA netB

netA

Pad of netB

Padstack of netA

Area of netB

Padstack of netA

Line (netB) Star-point (netA, netB) SMD pin (netA)

netA

netB

When the area of netB is generated, the clearance is kept from the area of netA.

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Correcting land status <Function> Correcting land status supports the following case; � Star-point padstack - Star-point pin within the same star-point When a padstack and a pin within the same star-point are placed at the same position, the land status should be unconnected. � Star-point – Component pin When a component pin and a star-point are placed at the same position, the land status should be unconnected. � Star-point – Pattern When a star-point and pattern are connected together, the land status should be connected. � Pin on which a star-point is placed – Pattern When pin on which a star-point is placed and a pattern are connected together, the land status should be connected. <Note> � If a star-point and a line are not connected directly, the land status is not

corrected. Please refer to the following illustration.

Unconnected Land Padstack in star-point

Star-point (padstack) SMD (padstack) Unconnected Land

Star-point (padstack)

Line Connected Land


Line (netA)

SMD pin (padstack netB)

Connected Land

Star-point

Line

SMD pin The line does not connect to thestar-point. Therefore the landstatus of the star-point is not“Connected”.

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Area DRC/Open Thermal <Function> Area DRC/Open Thermal detects thermal that does not connect to conductive area enough. This check function is available for a star-point and conductive area. In the above example, the area and pad on layer 2 are different nets, but the land status should be thermal. Area DRC/Open Thermal checks if they connect correctly.

Query Data <Function> The following information is added to Query Data – Object Info – Pin. � Star Point � Star Point Net Name

On-line Component DRC <Function> On-line Component DRC (Comp. – Cond.) allows the following case; � Place a star-point on a normal component pin

*normal component : component that is not a star-point component, and has a net to connect to a star-point

� Place a normal component pin on a star-point


Area (netB)

Pad (netA)

Star-point Normal component

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� Place a star-point component pin on a star-point component pin � Place a normal component pin on a normal component pin on that a

star-point is placed � Place a star-point on a conductive object <Limitation> If a star-point component and normal component are moved together, DRC error occurs when they are placed on another component.

Edit Pattern Comp. <Function> Make Figure into Pin and Release Figure from Pin now support virtual pad.

Error

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13. Click Preview and check it . If the check is OK, Click Generate.

2-3 Auto Surface Correction Template Area

Summary You can generate area in conductive layer, by referring “template area” in non-conductive layer. This conductive area shape is automatically corrected, in case input the objects on this area. If you input line on this area, area shape will be changed to keep the clearance. And if you move the line, area shape will be changed, too.

New

<Plough & Heal (Line) >

<Plough & Heal (Component) >

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Operation 1. Select Utilities � Template Area � Template Area Settings.

Specify Template Area Layer from the dialog.

You can specify the cut out parameters by this dialog. Please see “Parameters” section.

2. Select Utilities � Input/Edit Toolbox in Placement/Wiring Tool. Click Input Area from the Toolbox. And then Input Area to the Non-conductive layer.

3. A: Click Change Attribute from the Toolbox. And click the Area is input by 1.

B: The Template Area settings dialog is displayed. Push the left button from the mouse and select Append Row from

the assist menu. Specify Conductive Layers that generates the area and the Net name from the dialog.

Moreover specify the priority order. Note : If the priority order duplicated , a warning message appears.

C: And when you want to change the cutout parameter, click Cut Out Parameters and change the parameter.

A

B

C

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4. Select Utilities � Template Area � Generate Conductive Area.

5. Select Utilities � Template Area � Auto Correct Area. When you edit pattern or move component, the area automatically is corrected.

Parameters You can specify the following parameters. They are same as Area parameters.

� Conductive Layer … Effective Layer � Don’t Generate Island Pattern � Generate Inner Area � Clearance To Resist � Circular Object Processing � Line Corner Processing � In-component Temp. Net Pattern = Inhibit � Add Clearance � Addition Val. � Thermal Process � Thermal line output � Width(Thermal Line) � Start Angle (Thermal Line) � Output Count (Thermal Line) � Pin (Thermal Process) � Via (Thermal Process) � In-Comp(Thermal Process) � Merge Distance.

Note : These parameters were set by Utilities � Template Area � Template Area Settings are handled as default value for Template Area. They can be changed by the Change Attribute dialog.

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� Report …. Output parameters that were set to a Query Window when generate the conductive area.

2-4 "Embedded Router" supports Template Auto Surface Correction

Summary As Embedded Router, Template Area is supported.

Therefore Surface is automatically corrected when Embedded Router enters wire.

Necessary Conditions Please check on Utilities � Template Area � Auto Correct Area.

Improve

< Before Routing > < After Routing >

Template

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Chapter 3 Interface

3-1 Support Footprint by "igesin" 3-2 Support Footprint by "igesout" 3-3 dxfin supports footprint 3-4 dxfout supports footprint 3-5 Standard ASCII I/O

3-1 Support Footprint by “igesin” Import IGES data to Footprint library

Summary Importing IGES data to Footprint Library is possible from Rev.8. But the support is only by a batch command. The GUI doesn't exist in Rev.8. Basically, the spec is same as “igesin” for PCB/PNL.

Different points from “igesin” for PCB/PNL The following is different point from “igesin” for PCB/PNL. � Segment Line� Area conversion Function for PC Board Shape,

Layout area and Keep-out Area

Regarding PC Board shape layer and Layout area layer are ignored.

� Segment Line� Constraints Area Conversion Function for

Height Limitation Area

Regarding PC Board shape layer and Layout area layer are ignored.

� All Figures to Document Layer Conversion Function

Regarding Document layer is ignored because Footprint layer doesn’t have document layer.

� Footprint New Creation Function

When the specified Footprint doesn’t exist, it is newly created.

New

IGES File

IGES � CR-5000 Conversion(igesin)

Footprint Library

Parameter File

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< Regarding Dimension Line>

� It is converted to the dimension line shape of Components Manager. � The data that is relating to user defined layer is output to the specified

layer. � The data that is relating to other layer type (LIMIT) is not output.

< Regarding TEXT data>

� It is converted to the TEXT shape of Components Manager. � The data that is relating to symbol mark layer, resist layer, metal

mask layer and user defined layer is output to the specified layer. � The data that is relating to other layer type is not output.

Operation

The way of startup igesin.exe [parameter] [ Mandatory parameter ] -m <Processing Mode name> -r <Input IGES file path name>

-o <Output CR-5000 database path name> -p:lay <Input IGES LEVEL Number data>

-p:type <Output CR-5000 layer type> -p:name <Output CR-5000 Layer name> -p:ftpname <Output footprint name> [ Optional parameter ] -p:reset <Reset mode> -p:view <Input IGES VIEW number data>

-p:tol <Tolerance value for line connecting> -e <Output error file path name>

-w < Output log file path name > -V

39

Example:

igesin.exe -p:type LIMIT –p:ftpname abc -p:lay 3 -r sample.igs

-o sample.ftp -p:view 1 –p:name Inh-wir-A

� IGES data file name sample.igs

� Output FTP file name sample.ftp

� IGESLEVEL number Level 3

� IGESVIEW number View number 1

� Output Footprint name abc

� Inhibit layer Inh-wir-A

� Conversion layer type Convert Surface, Dimension line and TEXT to Height

Limitation Layer

� Tolerance ±0.00001

� Log/Warning file name Standard output

� Error message file name Error output

Limitation Conversion to Conductive layer, Hole/Variant hole layer and Component area layer is impossible.

40

3-2 Support Footprint by “igesout” Export IGES data from Footprint library

Summary Exporting IGES data from Footprint Library is possible from Rev.8. But the support is only by a batch command. The GUI doesn't exist in Rev.8. Basically, the spec is same as “igesout” for PCB/PNL.

Details Function You can specify the Footprint layer that outputs to iges. The Footprint layer you can specify is Conductive layer, Non-conductive layer and Hole layer. Multiple CR-5000 layers can be output for one iges layer. But one CR-5000 layer can't be output for multiple iges layers with one time. < Regarding conversion of figures > When a Padstack is output, the connected pad is output to iges. When a Pad is output, only the outline is output.

New

IGES File

IGES � CR-5000 Conversion(igesin)

Footprint Library

Parameter File

41

Operation

The way of startup igesout.exe [Options] Basename [ Mandatory parameter ] <Basename>

-p:ftpname <Output footprint name> [ Optional parameter ] -r <Reference file name>

-o <Output file name> -p <parameter filename> -e <Output error file path name>

-w < Output log file path name > -V

[ When making a parameter file ]

The following is a sample when the parameter file for igesout is created.

igesout.exe -m mkparam -r sample.ftp -o parameter.prm

� Reference file name sample.ftp

� Output parameter file name parameter.prm


� Error Message file name Error output

Example: The following is a sample when the parameter file for igesout is output. igesout.exe -r sample.ftp -o out.igs -p parameter.prm –p:ftpname footA � Reference file name sample.ftp

� Output file name out.igs

� Reference parameter file name parameter.prm

� Reference footprint name footA

42


� Error Message file name Error output

Limitation • The “igesout” can't output “pin number”. • Footprint name that can output by one time is only one.

If footprints are specified at multiple times, the last one is output.

3-3 dxfin supports footprint dxfin supports footprint

Summary It is possible to import DXF data into footprint. The function is basically the same as the current dxfin.

Function <Parameter file – Layer mapping> It is necessary to prepare a parameter file. The layer mapping is defined as follows.

CR-5000LayerName : DxfLayerName

CR-5000LayerName DxfLayerName layer:system:outline: PC Board shape layer layer:system:outlineDrawing: Document layer of Board shape layer layer:system:hole: Hole layer layer:system:layout: Layout area layer layer:cond:Layer Name: Conductive layer layer:condDrawing:Layer name: Document layer of conductive layer layer:nonCond:Layer name: Non-conductive layer layer:nonCondDrawing:Layer name: Document layer of non-conductive layer NOTE : Do not set the grayed-out layer names. They are not available for importing to footprint. <Data correction> Data correction is different from that for PCB conversion. If there is a object that can not be input to the specified layer, it is ignored.

Layer Area Line Character Conductive layer An area included in

another area is converted into a cutout.

No correction. No correction.

Improved

43

Symbol mark layer Resist layer Metal mask layer

An area included in another area is converted into a cutout.

No correction. No correction.

COC area layer Converted into an area.

Ignored. Ignored.

Hole layer Only object that can be converted into circle is converted into round hole.

Only object that can be converted into circle is converted into round hole.

Ignored.

Variant hole layer No correction. No correction. Ignored. Keepout layer An area included in

another area is converted into a cutout.

No correction. Ignored.

Undefined layer No correction. No correction. No correction. <Operation>

dxfin.exe [option] basename –p:ftpname footprint_name � Required parameter

basename Specify a DXF file name without the extension. If this basename is used for a data to be written to, the program searches in the order of panel (.pnl) � PCB (.pcb) � footprint (.ftp). -p:ftpname Specify a footprint name for the data you import into a footprint library.

NOTE: Before executing, prepare a footprint library and a parameter file.

Limitation Layer Limitation

Hole layer Round shape object only can be imported.Keepout area Area and line only can be imported. Variant hole layer Area and line only can be imported. COC area layer Area only can be imported.

44

3-4 dxfout supports footprint dxfout supports footprint

Summary It is possible to export DXF data from footprint. The function is basically the same as the current dxfout, however the following functions are not supported. � Block Mode � Reference Name Output Mode

Function <Parameter file – Layer mapping> It is necessary to prepare a parameter file. The layer mapping is defined as follows.

CR-5000LayerName : DxfLayerName : color : ColorName : mirror : MirrorName

CR-5000LayerName DxfLayerName layer:system:outline: PC Board shape layer layer:system:outlineDrawing: Document layer of Board shape layer layer:system:hole: Hole layer layer:system:layout: Layout area layer layer:cond:Layer Name: Conductive layer layer:condDrawing:Layer name: Document layer of conductive layer layer:nonCond:Layer name: Non-conductive layer layer:nonCondDrawing:Layer name: Document layer of non-conductive layer It is possible to map more than one footprint layers to one DXF layer, but it is not possible to map one footprint layer to more than one DXF layer.

Improved

Footprint Footprint DXF DXF

45

<Color setting - ColorName> It is possible to specify the color. 19. Default parameter file A default parameter file is produced as follows. NOTE : “White” is specified in case of that;

� The color is not set in color.rsc. � dispftp.rsc and color.rsc are not be loaded.

20. Edit parameter file To edit the parameter file, write a color name that is set in color.rsc. If it is necessary to specify a color that is not set in color.rsc, write the color number for DXF data (1<=integar<=255). If you write an invalid color name or color number, “White” is specified. <Figure Conversion Processing> � Pad Pad is converted into an object that has outline only. � Padstack Connected pad only is converted into DXF. <Operation>

dxfout.exe [option] basename � Required parameter

basename Specify the file name to be imported/exported. -p:ftpname footprint_name Specify a footprint name to be exported.

NOTE: Before executing, prepare a footprint library and a parameter file.

DisplayAttributes 8 { COND_A 5 0 e 45 90 55 y COND_INNER7 0 f 45 90 5 n COND_B 2 0 e 45 90 5 n RESIST_S_A 5 0 e 45 90 5 n RESIST_P_A 6 0 e 45 90 5 n

・・

####################################################### # # Color resource file common for CDB, layout, CAM # ####################################################### ZPCB 3 { 0 black "Black" 1 white "White" 2 red "Red" 3 green "Green" 4 blue "Blue" 5 yellow "Yellow" 6 magenta "Magenta" 7 cyan "Cyan"

・・

# Default parameter file created by DXFOUT. layer:cond:condA: condLayer_A:color:Yellow layer:cond:condB:condLayer_B:color:Red layer:nonCond:Symbol-A:Silk-A:color:Blue layer:nonCond:Symbol-B:Silk-B:color:White

・・

dispftp.rsc

color.rsc (Windows ver.)

The color is specifiedfrom the number indispftp.rsc throughcolor.rsc.

46

Limitation � It is not possible to output pin number object. � If broken line, phantom line, or double phantom are output in the setting of

outlineMode:wid or outlineMode:off, the line type is ignored. � It is possible to specify one footprint name in one execution.

3-5 Standard ASCII I/O Change made from Rev.7 to Rev.8

Summary Following items are changed or added to each ASCII I/O information from Rev.7 to Rev.8 <PCF> and <PNF> common � Dimension lines related information � Bond wire information output <PCF> � Wiring inhibit or permit property � Area automatically revise property <PNF> � Child panel information output <FTF> � Dimension lines standard value information for each footprint � Bond wire information output <RUF>, <CDF>, <PKF>, and <MRF> � No change

Improve Add

47

Chapter 4 CR-5000 Common

4-1 Database Version control programs 4-2 Improvement of display performance 4-3 Expanded licensing structure 4-4 Installation 4-5 Enhancement of tool customization 4-6 Improvement of API Tools 4-7 Improvement of the speed when displaying DFM hierarchy 4-8 BD-Viewer 4-9 Enhancement of the way for creating Postscript data 4-10 Improvement of Print dialog 4-11 Enhancement of Plot functions 4-12 Unification of each error dialog 4-13 Environment settings for plot by non-root user (Only support for UNIX)

Board Designer Rev9 New Features

4- 1 Database Version control programs

Automatic version up of Panel data

Summary Panel Design Tool will automatically update the version of panel file when opening following environment variable is set.

The tool will only update selected PNL data. (Child board or child panel is not updated.) The tool will only update version from Rev.7 or Rev.8.

Rev9 to Rev8 Version Down Program

Summary When the database version is in Rev.9 and need to down grade to Rev.8, following program is provided to convert the data. New attributes and internal data structure may not be converted to Rev.8 data.

Detail Command

[ Option ] -m nobackup -m recursive -V -e <output_error_filename> -w <output_warning_filename> For example; When doing version down the Rev9 database ABC.pcb and

ABC rul without backup file

ZCRDB_VERSIONUP=Auto

New

zdb9to8.exe [Option] <Filename>

zdb9to8.exe -m nobackup ABC

New

49


Limitation Attribute Conversion

Data Property After converted to Rev8

Max Stub Net Object Default setting Stimulus

Stimulus Pin Pin Swap

Electrical Net Pin Pair Wiring Width Stack Pinpair Max Wire Length Pinpair Min Wire Length Pinpair Max Delay

Pin Pair Group

Pinpair Min Delay Pinpair Max Wire Length Pinpair Min Wire Length Shield Net Shield Gap

Electrical Net

Stimulus Path Path Bus Bus Differential Pair Differential Pair Net Class Net Class Electrical Net Class Electrical Net Pin Pair

Delete

Pin Pair Group Electrical Net Pin Pair Release from Pin PairGroup

Note : Pinpair Net name of Net property and Net group are handled as

Differential pair at Rev8 Placement/Wiring Tool. But the property “DifferentialPair” was added from Rev9. This program will not convert differential pair in Rev.9 into Rev.8.

Note : In Rev9 with E-net design environment = ON, all nets will belong to E-net. Therefore E-net with single net will be generated in the design. This program will also convert the E-net that has only 1 net.

4- 2 Improvement of display performance

Improved area display in certain case

Summary There is a slight improvement of area display performance in the following

case. • Displayed layers have many windows on area. • Layer display is set to solid.

Rev.9 will skip display of above windows when they are small enough to ignore.

Enhance

50


4- 3 Expanded licensing structure

New license format to improve security

Summary New encryption key is added in license file to exclude illegally copied licenses in the black market, and to exclude bug in the license file.

FLEXlm version Following is a table of FLEXlm versions required for Rev.9.

Note : Name of license program has been changed from FLEXlm to FLEXnet.

This document will use FLEXlm.

Application Name FLEXlm Version

Required SENTINEL Driver Version

License Server (lmgrd,zuken,lmutil,lmtools)

V10.8.0.6 5.42.1 (REDAC_DONGLE)

Rev.9.0 SD/BD V10.8.0.2 5.39.2 (CR Dongle)

Rev.8.0 SD/BD V9.2 5.39.2 (CR Dongle)

Lightning 9 CADSTAR 10

V10.8.0.6 5.42.1 (REDAC_DONGLE)

FEATURE ZX0501 zuken 9.000 permanent 10 B010907007EB4518A567 \

VENDOR_STRING=b99e662f20becc61e522358d933ed08a SIGN="01DF \

BEF9 4EA0 B582 081D B098 BED3 9533 B37A BDE4 2298 0F5F 1CD4 \

8BDD 9685 0711 2EB6 3278 9F6D 1B81 BDB0 742D DE7C B408 66DC \

BE23 B098 3278 1B81"

Enhance

51


4- 4 Installation

Delete Lightning Files from Rev.8.030

Summary In Rev.8.030, installation added “ZSIEROOT” to registry and zsie directory under install directory. This provided functionality to run Lightning SI-Epilog and/or SI-Prolog from CR-5000. The installation has changed in SD/BD Rev.9. The registry “ZSIEROOT” will no longer be registered during installation and files/directories related to zsie will be deleted.

Detail This change is only for Windows Platform, as HP-UX and Solaris platform did not provide Lightning tools interfaces in Rev.8.030. Process of deleting Electrical Edit related files will run depending on the situation of SD installation.

SD Revision Delete ZSIE directory? Comment Not Installed Yes Rev.9.0 will not use Electrical Editor

related files under ZSIEROOT. Before Rev.9.0 No Leave the files to run “SI-Prolog” from SD.

Rev.9.0 or later Yes SD/BD Rev.9.0 do not refer to files under ZSIEROOT. No problem to delete files.

Install Floor Planner Files on Windows

Summary A tool to start Lightning Floor Planner from SD is added from Rev.9. The process of staring Lightning Floor Planner will share some of setting with BD. Therefore install/uninstall procedure need to consider cases for install status of SD and BD.

Detail <Database Server> From Rev.9, System Designer will install Database Server (ozserver) when Floor Planner option is selected during installation. With this change, SD will also stop Database Server while installing SD just as BD. In addition, when SD is already installed, installation of Database Server alone from BD CD-ROM is not possible. In case of using SD and Database Server, it is required to install SD with Floor Planner option.

New

Official release at Rev10

New

52


<Install Resource File> Some of customizable files are shared between SD and BD. There are 4 ways of handling of existing resource files in si 1. Create backup file xxx.rsc.bk and install (incremental backup) 2. Leave existing resource file (Install xxx.rsc.new file) 3. Leave existing resource file (Do not install) 4. Install new resource file (when the file does not exist) milar way as

revision up installation.

Limitation <Uninstall Rev.8 Board Designers> Since Rev.8 Board Designer does not consider the installation of System Designer with Floor Planner option, uninstall process of Rev.8 Board Designer will delete necessary settings from Rev.9 System Designer Floor Planner.

Uninstalling BD revision

Installed SD revision

Operation of Floor Planner

8.010 9.0 Cannot Operate Correctly 8.030 9.0 Cannot Operate Correctly 9.0 9.0 No Problem

Install Floor Planner Files on UNIX

Summary A tool to start Lightning Floor Planner is added to SD. Floor Planner will share some of files with BD. Therefore install/uninstall procedure need to consider cases for install status of SD and BD.

Detail <Database Server> From Rev.9, System Designer will install Database Server (ozserver) when Floor Planner option is selected during installation. With this change, SD will also stop Database Server while installing SD just as BD. In addition, when SD is already installed, installation of Database Server alone from BD CD-ROM is not possible. In case of using SD and Database Server, it is required to install SD with Floor Planner option. <Install Resource File> Some of customizable files are shared between SD and BD. There are 4 ways of handling of existing resource files in similar way as revision up installation. 1. Create backup file xxx.rsc.bk and install (incremental backup)


New

53


2. Leave existing resource file (Install xxx.rsc.new file) 3. Leave existing resource file (Do not install) 4. Install new resource file (when the file does not exist) Files which are not for customize will be overwritten during installtion.

Limitation Uninstall Rev.8 Board Designers Since Rev.8 Board Designer does not consider the installation of System Designer with Floor Planner option, uninstall process of Rev.8 Board Designer will delete necessary settings from Rev.9 System Designer Floor Planner.

Uninstalling BD revision

Installed SD revision

Operation of Floor Planner

8.010 9.0 Cannot Operate Correctly 8.030 9.0 Cannot Operate Correctly 9.0 9.0 No Problem

Duplicate Backup Files Following files will have 2 backup files created during version upgrade from SD/BD Rev.8 to SD/BD Rev.9, since both SD and BD will create backup when they are upgraded.

$ZCSROOT/info/jpn/figure.rsc $ZCSROOT/info/eng/figure.rsc

4- 5 Enhancement of tool customization

Customizes functions for Library Tools

Summary There are many requests asking to introduce customize functionality to various editor tools with canvas. From Rev.9, CDB editor tools with canvas will support customize function. The customize function for CDB editors will employ new GUI supported customize interface and they are available in following tools. • Footprint Editor • Pad Canvas Editor • Template Definition Tool (for Library Viewer)

The new customization will support following items. • Keymap • Menubar • Toolbar

New

54


Note : - Customize function for BD and BP will remain the same with Rev.8. - CLUI commands are not supported

Customize environment file Each tool has resource files under following directories. The name of customize resource files are “cmacro.rsc”. Program Environment and Project Environments are editable by Administrative users only.

Footprint Editor Padstack Canvas Editor Template Definition Tool

Note : - These files are not designed to be shared between different tools. - Customization will be automatically saved to the file when command is

defined in the editor.

Reference priority of customize definition Definition Environment (Override of definition)

There is a section in each customize dialog that displays in which environment does the customized definition exist.

The mark is in order definition environment from User/Project/Program environment. The mark means the following.

Customize Environment Resource file directory Program Environment $ZCSROOT/info/custom/foot/ Project Environment $CR5_PROJECT_ROOT/zcs/info/custom/foot/ User Environment $HOME/cr5000/cs/custom/foot/

Customize Environment Resource file directory Program Environment $ZCSROOT/info/custom/pad/ Project Environment $CR5_PROJECT_ROOT/zcs/info/custom/pad/ User Environment $HOME/cr5000/cs/custom/pad/

Customize Environment Resource file directory Program Environment $ZCSROOT/info/custom/lvte/ Project Environment $CR5_PROJECT_ROOT/zcs/info/custom/lvte/ User Environment $HOME/cr5000/cs/custom/lvte/

User Environment > Project Environment > Program Environment

O = Defined X = Undefined

55


When more than one customize definition exists, tool will determine which definition to follow according to priority explained above. Unit of override is different by customize target. Following is the unit of override in Rev.9.

Key map customize function

Summary There is new GUI based Keymap customize function available.

Operation You can start customize editor for each items from Menu [Environment] [Customize].

Keymap Editor 1. Select the environment to edit. (Displayed only for Administrative users) 2. Select the short cut key to edit the command definition. 3. Click on Set Keymap button.

4. Select Command from the list to apply for the key.

2

3

New

Keymap = Each Keymap Menubar = Entire Menu Toolbar = Each Toolbar

1

56


Menu bar customize function

Summary There is GUI based Menubar customize function available. It can easily customize menu bar.

Operation You can start customize editor for each items from Menu [Environment] [Customize] [Menubar].

Menubar Editor 1. Select the environment to edit. (Displayed only for Super user) 2. Select the location in the menu structure to insert new menu. 3. Click on icon in the dialog.

Create Menu Item When this item is selected, following diagram will appear. Label the menu and select the command to apply.

New

2 3

1

57


Create Cascade When this item is selected, following diagram will appear. Label the cascade and define Icon and Mnemonic key if needed. Then new branch will be created in the menu.

Note : Mnemonic --> Short cut key for menu bar.

Toolbar customize function

Summary There is GUI based Toolbar customize function available from Rev.9. It has 3 functions.

• System Toolbar customize (Standard Toolbar) • User Defined Toolbar creation and customize • Floating and Docking of Toolbar (Windows Only)

Operation You can start customize editor for each items from Menu [Environment] [Customize] [Toolbar].

Toolbar Editor 1. Select the environment to edit. (Displayed only for Super user) 2. Click New… button to add new toolbar to the environment. 3. Select name of the toolbar in the left section of the dialog. 4. Select Create Button icon to add command icon. 5. After adding new command, select Edit icon to change Icon, Label,

Tool tip, and Active Display.

2

3

4

5

New

1

58


Button Arrangement

Normal = Icons are placed in a line. X columns = Icons will be placed with specified columns.

Note : Template Editor has vertical toolbar, however this is impossible to customize.

Float and Dock of Toolbar

It is possible to drag the toolbar and make it float and merge back to 4 sides of editor window. This is available only in Windows OS version. Replaced with this function, command “Separate or Merger Toolbar” that was used to make tool bar is no longer used in Footprint Editor, Padstack Canvas Editor, and in Template Definition Tool.

Note : It requires to dock and float the tool bar in order to switch vertical and

horizontal orientation.

4- 6 Improvement of API Tools

ZCC Enhancement

Summary There is new function to control Widget Item and List Item to make them

enable or disable in the customized tool.

User commands can be grayed out by item.

Enhance

59


4- 7 Improvement of the speed when displaying DFM hierarchy

Improvement of the displaying speed

Summary At Unix server and PC client environment, there is the case that the hierarchy indication on DFM is slow. It causes interrupt for their designing. Therefore Rev9 improves the speed. And it is improved to display the child board name when the hierarchy display is “OFF”.

Note : When the hierarchy display is “OFF”, the mark (angry face mark) isn't displayed

even if the unused area value is bigger than the specified value.

4- 8 BD-Viewer

Viewer tool for Board Designer

Summary There are several viewer tools for Board Designer design data. With strong demand from the market and new strategy to expand CR-5000 in to the market, we will bring out new BD Viewer.

New

< Rev 8 > < Rev 9 >

Child Board Name

Enhance

60


Installation

Summary Not yet decided how would the tool going to be provided. With the provided installer, setup tool will finish install/uninstall of program to PC. BD-Viewer is designed for Windows 2000 and Windows XP environment only. Installation of BD-Viewer needs to be done by Administrative user.

Note : Installation of CR-5000 Data Server is not necessary. BD-Viewer runs

independently from CR-5000 environment. Note : When System Folder already has following files, you can select “Ignore”

during installation. - mfc71.dll - msvcr71.dll - msvcp71.dll

Functionality

Summary BD-viewer will have following functionalities. Many of them are look and feel GUI similar to Board Designer. - Reference Board/Panel/Footprint data - Layer Display Setting - Layer Order - Display Setting for Net - Footprint Display Option - Canvas Display Options - Search by Net/Ref-Des/Pin - Data Request - Measure - Add Comment - Edit Comment - Reference from Comment List - Reference Same Design - Print

Detail Reference Board and Footprint data BD-Viewer can read board data and footprint library. From footprint library file, BD-Viewer can reference Footprint objects. There are 3 ways to open file. - Menu --> Open - Drag & Drop - Command line

New

New

Canvas

Toolbar

Panel Menu

Output Window

61


Note : BD-Viewer supports database after Rev.7. Database Rev.6 or before can’t be opened.

Layer Display Setting There are 2 display modes and they are Width or Paint. Default color setting is transferred from board design. For FTP file, viewer will first refer to “%ZCSROOT%\infor\dispftp.rsc”. If the file doesn’t exist, viewer will apply default setting. Layer Order Priority to display layer can be changed from Layer Order dialog. The setting is applicable while the file is opened. It will be cancelled after the file has been closed. Display Setting for Net Display settings for nets are available for board design. Turn ON check mark to apply each setting to the net. Default color setting is carried over from board design. Changes made in viewer are effective while the file is open.

(Install Path)\viewer.exe (Data Path)\xxx.pcb

62


Footprint Setting Option Following display options are available when referring to Footprint Library. - Pin Number - Pin Reference Point - Padstack Reference Point Canvas Display Options Following options are available. Status of ON/OFF can be saved. These option settings will be saved in “_bdviewer_.ini” file under same folder as viewer.exe. If it fails to save the file, settings will be cancelled. Error message will not be displayed even when file is not saved.

Note : Grid setting ON/OFF is dependent on board setting.

(Install Path)\_bdviewer_.ini

Display Coordinates

Drawing Area/Origin Display Grid Display Scale

Display Pin No.

63


Select by Net/Ref-Des/Pin In the viewer window, there is panel menu to list components, pin and nets. Selecting objects from this panel will highlight. If Zoom check box is ON, then viewer will zoom in to the target object.

Note : This function is available only for PCB.

64


Query Data Click on objects to report data on the canvas. To see more detail, display Output Window. Query will search object from displayed layers with priority of Layer Order. Use “Next” from assist menu to search for duplicated object. And use “Another” to search for duplicated figure within same object. Query Data will search for following figure types. - Text - Area - Surface Area - Line - Mesh Plane - Ref-Des (Symbol) - Round Hole - Oblong Hole - Square Hole - Pad - Linear Dimension - Angle Dimension - Diameter/Radius Dimension - Leader Select “Escape” to cancel data selection. Measure Measuring function is provided at same time as Query Data. Shortest distance will be reported between 1st pick and 2nd pick. Followings are target of measure function.

Target Figure Measurement Location Line Entire Line, Closest Segment, Segment Center Area Entire Area, Closest Outline or Window Mesh Plane Entire Area, Closest Outline, Window or Mesh Round Hole Outline, Center Oblong Hole Outline, Center, Diagonal Line through Center Square Hole Outline, Center Pad Outline, Center, Each Figures in the Pad

1st pick 2nd pick

65


Input Comment Input comment from Menu --> Edit --> Input Comment. Comments can be copied, moved and deleted from assist menu. This comment data will be saved as xxx.msb file under same directory with design data. If comments can’t be saved, tool will report error. This file can be referred and edited by BD-Viewer only. There are Undo and Redo operations for comments. Redo will cancel “Undo” operation.

(Data Path)\xxx.pcb (Data Path)\xxx.msb

66


Reference Same Design BD-Viewer will only lock board design file and footprint library file while opening. Once the file is read, it is possible for other users to open same data. This will allow multiple users to refer same design. BD-Viewer can’t open data when it is locked by other BD tools. When users access at same time, some user may find data locked. In this case, wait for a while and retry when the data is not locked. Print / Print Preview There is simple Print and Print Preview function in BD-Viewer. Comments can be copied, moved and deleted from assist menu. There is no predefinition for output page. Control of output page is done by individual printer settings.

67


4- 9 Enhancement of the way for creating Postscript data

Postscript data amount reduction

Summary In Rev8, when the line data is output as the postscript format, the construction points of the line outline are outputted and then data for painting are outputted. Therefore the output data amount is huge. At Rev9, the line width and construction points of the line are outputted. Rev8 outputs points that construct the outline of the line, but Rev9 outputs construction points of the line. The result can reduce amount of the postscript data.

< Rev8 > < Rev9 >

Operation The function requires the setting of “plotter setup”. 1. Please start up the Plotter Configuration Tool from [Programs] [CR-5000 Board

Designer] [Utilities] [Plotter setup].

The dialog has a “Set Detail” menu.

2. Please select [Set Detail5] and select “ON” to “Volume of data reduction”. <When specifying by batch>

Enhance

psdrv.exe -r <CR-5000 intermediate data> -o <Output file name> -p:reduce on

68


Other effective Tools • Plotter setup • Board Designer/Board Producer • Package Synthesizer • Library Viewer • CDB Figure Viewer • Plot Tool • Document Designer • Gerber In • CAM Check Tool • BD Viewer • System Designer

Note 1: Target objects are line, slot hole, text and dimension line. Note 2: The option is effective only for Postscrip

Note 3: When the square dash line includes the next elements, the dash

shape may be different from the intermediate data. • Horizontal/Vertical line continues to Diagonal line or Arc line • Line width are same width

Intermediate data

Postscript data

The start of the dash is different because Horizontal line and Diagonal line are handled as different line

69


Font Output

Summary When the postscript is outputted, text data can be outputted as text. But the font is not the one that is used by Board Designer ($ZLOCALROOT/zsys/font, $CR5_PROJECT_ROOT/local/zsys/font/user). At Rev9, defining the font to postscript and adjusting the text shape between Board Designer and postscript. But there are limits to the Font that postscript interpreter can recognize. Therefore when you set the Font name in the Plotter setup, the font name that postscript can recognize is listed.

Operation The function requires the setting of “plotter setup”. 1. Please select [Set Detail3] and set “ON” to “Plot use font”.

And define the Font name

On Board Designer Editor

<Defined the Font> < Rev8 >

Output PostScript Data

Enhance

70


<When specifying by batch> For example: when the default setting is the next, (Courier is for 1 byte and Ryumin-Light-H is for 2byte)

When you define different fonts for both 1 byte and 2byte,

Other effective Tools • Plotter setup • Board Designer/Board Producer • Package Synthesizer • Library Viewer • CDB Figure Viewer • Plot Tool • Document Designer • Gerber In • CAM Check Tool • BD Viewer • System Designer

Note 1: When you specify both –p:label and –p:font, the font of –p:label is ignored.

Note 2: When 2 bytes font is included in the intermediate data, you can not

specify 2 byte font for postscript Note 3: When the user font is defined by postscript, the “userfont.rsc “ is

required. The “uesrfont.esc” can be made by Font Manager

psdrv.exe -r <CR-5000 intermediate data> -o <Output file name> -p:font on

psdrv.exe -r <CR-5000 intermediate data> -o <Output file name> -p:font on,Times,GothicBBB-Medium-H

1byte Font Name 2bytes Font Name

71


4-10 Improvement of Print dialog

Re-available “Apply” button

Summary The “Apply” button in the Print dialog has deleted by unification of GUI in Rev7. But some of customers performed the plot tool without closing the dialog by Apply button. From Rev7, the dialog always closed when it was performed. So they requested the "Apply" button at Rev9, the “Apply” button is come back into the dialog.

Add

72


Support for Project Resource

Summary At the Print dialog, it supports Read/Write of the parameter in $HOME/ue/plotter.rsc. Many customers wish the supporting of Project resource. In Rev9, it supports Project resource. The priority of the resource file is updated by this support.

< Rev8 > $HOME/cr5000/ue/plotter.rsc Used it only

<Rev9 > $HOME/cr5000/ue/plotter.rsc High $CR5_PEOJECT_ROOT/zue/info/plotter.rsc $ZUEROOT/info/plotter.rsc Low Note : At Rev8, the parameter was always written and read. But at Rev9,

the plotter.rsc is read when the print dialog is started up. Therefore the parameter may be different from the previous parameter. If you saved the previous parameter, you can get the same.

Enhance

Same function as the "Save As" button in Rev8

Added

73


4-11 Enhancement of Plot functions

Support for Pin Number/Name plot

Summary The Plot Tool can plot reference designator. But Pin number and name can not be output. At Rev9, pin number/name can be output.

<When specifying by batch> For example: When outputting Pin number for pins of the A side components

Reference : Please see online-help or the usage by "zplot.exe –help” for details.

Enhancement of Reference designator plot

Summary At Plot Tool, when you specify to output Ref-des, you can output them according to each components angle at Rev9. And also you can specify the components you want to output Ref-des. <When specifying by batch>

Add

zplot.exe sample.pcb –p:pin A

Enhance

74


For example: When outputting Ref-des with the component angle

For example: When outputting Ref-des for “COMP1” on A side

Reference : Please see online-help or the usage by "zplot.exe –help” for details.

Enhancement of load parameter file (.plp)

Summary When you read the parameter file for the plot tool from [File] [Read Parameter File], the layer order for each page always is reset at Rev8. From Rev9, it is kept. In other words, the layer order belongs to the order that is described in parameter (.plp).

< Rev8 > < Rev9 >

zplot.exe sample.pcb –o sample.pld –p:reftext A:CC/angle

zplot.exe sample.pcb –p:reftext A –p:targetcomp COMP1:reftext

Enhance

Cunductive-1*Layer 2 { "BOARD/data:width:1/1:off" "on" "WIR1/data:width:1/1:off" "on" "Symbol-A/data:width:1/1:off" "on" "MetalMask-A/data:width:1/1:off" "on" "Resist-A/data:width:1/1:off" "on" "WIR2/data:width:1/1:off" "on" "WIR3/data:width:1/1:off" "on" "WIR4/data:width:1/1:off" "on" }

The display order for layer name is same as the one that load the PCB layer

The order in Rev9 belongs to the one that is described by parameter.rsc

75


Other effective Tools • Plotter setup • Board Designer/Board Producer • Package Synthesizer • Library Viewer

Note 1: The “Hole” and the “Hole in padstack” are always displayed at the bottom layer regardless of the parameter file.

Note 2: When the parameter file doesn’t have all layer settings, firstly layer

names that are described by the parameter file are displayed and then other PCB layer names are displayed.

Import Net display color by zplot

Summary At plot tool, already net display color can be imported. At Rev9, the function that imports net color is added to the batch program “zplot”.

Details The parameter for the option –p:import is as follows.

Option (for importing net color) -p:import [#1]/[#2] Parameter (for single page specify) Import : “[#1]/[#2]”

Note 1 : At the parameter of performing continuously, the parameter [Import]

can not use. [#1] …. “net” (The item can not ignore) [#2] …. “SD” Import SD net color (when you ignore the item, “SD” is used) “BD” Import BD net color

Reference: The "SD" net color gets from RUL. And the "BD" net color gets from PCB.

<For example: When importing the “SD” net color>

Add

zplot.exe sample.pcb –o sample.pld –p:import [#1]/[#2]

zplot.exe sample.pcb –o sample.pld –p:import net/SD

76


Note 1 : The color that is specified by the net name specify (-p:net/Net) option is ignored. The color that is imported from the display color is used.

Note 2 : The option/parameter [import] effects when the option (-p:net/Net) is

specified.

Note 3 : The display color refers to plotter.rsc and converts to pen color and pallet color for plot. Therefore the correspondence between colors for display and for plot needs to set by [Import Net display colors].

Note 4 : The plot tool can not read in the parameter even if the parameter

including the [Import] parameter for single specify

Expanding of restrictions for the text counts

Summary Until Rev8, if PCB has the text data that is the over 65535 characters, when the data is printed out, it is aborted. Therefore the over 65535 characters are handled as the restriction. But the internal process is updated and the data can be printed out from Rev9.

Enhance

77


4-12 Unification of each error dialog

Checking each error on the Verify Check Result dialog

Summary At DRC, MRC, EMC adviser, and ADM, you can confirm each results on the Verify Check Result dialog for ADM.

< DRC > < EMC Adviser > < ADM >

< Verify Check Result dialog >

Operation The Verify check result dialog starts up by [Module] [Verify check result] from menu bar. The next describes the operation when you import DRC/MRC and EMC adviser error. < Import check result into the Verify check result dialog > 1. Select [File] [Import BD Result] from the menu bar of the Verify check result

dialog.

Note : The result is not automatically updated. So you need to perform above operation to reflect the current error after you re-check some checks.

Enhance

78


< Reflect confirmed check result to each error dialog > The confirmed check result is meaning the “Comment” and the “Solve” (e.g. Modify, Ignore etc) you set. 1. Select [File] [Export BD Result] from the menu bar of the Verify check result

dialog.

< Exit the dialog> 1. Select [File] [Exit] from the menu bar of the Verify check result dialog.

Details The order of displaying error messages is as follows.

1. ADM Check Itesms 2. Area DRC 3. Component DRC 4. Area MRC 5. EMC Advisor

Each error message is stored in the next files. These files are existing under <PCB file name>.chk folder. The folder is automatically created at the folder where the same PCB file exists when

you perform a check tool.

Relation Tool (Command) • Area DRC • Component DRC • Area MRC • EMC Advisor

The order of displaying error message

79


4-13 Environment settings for plot by non-root user (Only support for UNIX)

Plotter settings by non-root user

Summary When you set the plotter environment on UNIX OS, the root permission was required because the process like spooler setting etc requires the root permission. Therefore there is a request that want to set the plotter environment by non-root user when the root permission is not allowed for CAD manager or when system manager doesn't want to update the spooler setting. At Rev9, it supports for this enhancement request. (BD-14679)

Details When the non-root customer starts up the Plotter Configuration Tool, the following message is displayed.

Note : The following settings can not be done by non-root user.

(Append/Modify) • Spooler setting • Setting a printer model file • Setting it as default output location

(Delete)

• Delete spooler • Delete a printer model file

Enhance

Checking a user : XXXX Plotter Configuration Tool was started by an ordinary user. An ordinary user can not set it concerning the spooler to need super user rights.

The menu [Edit] is not grayed-out even if the non-root user

80


The next table summarizes the difference between root user and non-root user.

Root user Non-root user

Rev8 or older Rev.9 Rev8 or older Rev.9 Spooler setting OK OK NG NG Creation of a shell program for plot (/local/zsys/bin/post?.sh)

OK OK NG OK

Creation of a setting file for plot (Files under /local/zsys/etc/)

OK OK NG OK

81

Chapter 5 PCB Library

5-1 Support of constraint DB - drout, drin, drlist 5-2 Design Rule Edit GUI


5- 1 Support of constraint DB - drout, drin, drlist

Support properties according to the expanded Design Rule database

Summary The Design Rule database is expanded by integration of constraint.

The next table is a property list is added by Rev9. “drout”, “drin” and “drlist” support for the properties.

<Pin Pair Rule>

• Pin Pair Max Length • Pin Pair Min Length • Pin Pair Max Delay • Pin Pair Min Delay • Bus Name

<Default Rule>

• Max Zo • Max Xtalk • Pin Pair Max Delay • Pin Pair Max Length • Pin PairLength Tolerance • Max Overshoot • Max Skew Delay • Min Impedance • Pin Pair Min Delay • Pin Pair Min Length • Max Stub Length • Stimulus

Note 1: When the property is undefined, it is not output. Note 2: When the E-net environment is “OFF”, they are not output.

<Electrical Net>

• Electrical Net Name • E-net Max Total Length • E-net Min Total Length • E-net Max Via Count • Layout Guide • Max Stub Length • Max Xtalk • Max Overshoot • Max Zo • Min Zo • Max Delay • Max Skew Length

Enhance

84


• Max Skew Delay • Min Delay • Topology • Max Length • Min Length • Shield • Shield Net Name • Shield Gap • Stimulus • Period • Rise Time • Voltage Amplitude • Xtalk Type • Xtalk Max ParallelLength • Ground Prohibit • Max Wire Capacitance • Xtalk Intensity • Grouping Net • Pin Pair Rule

Note 1: When the property is undefined, it is not output. Note 2: When all properties are undefined, E-net names are not output, either. Note 3: When the E-net environment is “OFF”, they are not output.

<Net Class>

• Net Class Name • Max Total Length • Min Total Length • Pin Pair Max Length • Pin Pair Min Length • Max Skew Length • Shield • Shield Net Name • Shield Gap • Shield Wiring Width Stack • Max Stub Length • Priority Layer Mode • Priority Wiring Layer1 • Priority Wiring Layer2 • Same Net Clearance • Same Net Parallel Length • Max Delay • Max Zo • Min Zo • Max Fanout Via Count • Period • Duty • Rise Time • Voltage Amplitude • Max Xtalk • Xtalk Type • Xtalk Max ParallelLength • Xtalk Intensity • Ground Prohibit

85


• Max Wire Capacitance • Voltage • Max Voltage • Min Voltage • Phase • Potential Difference Table • Net Note 1: When the property is undefined, it is not output. Note 2: When all properties are undefined, Net class names are not output,

either. <Electrical Net Class>

• Electrical Net Class Name • Max Zo • Max Xtalk • Max Delay • Max Length • Max Skew Length • Max Overshoot • Min Delay • Min Length • Max Stub Length • E-net Max Total Length • E-net Min Total Length • E-net Max Via Count • Shield • Shield Net Name • Shield Gap • Stimulus • Period • Rise Time • Voltage Amplitude • Xtalk Type • Xtalk Max ParallelLength • Ground Prohibit • Max Wire Capacitance • Xtalk Intensity • Electrical Net

Note 1: When the property is undefined, it is not output. Note 2: When all properties are undefined, Electrical net class names are not

output, either. Note 3: When the E-net environment is “OFF”, they are not output.

<Differential Pair>

• Differential Pair Name • Max Zo • Max Xtalk • Max Delay • Max Length

86


• Max Skew Length • Max Overshoot • Max Skew Delay • Min Zo • Min Delay • Min Length • Topology • Differential Pair Space • Electrical Net • Differential Pin Pair • Differential Net Pair Note 1: When the property is undefined, it is not output. Note 2: When all properties are undefined, Differential pair names are not

output, either. Note 3: When2 electrical nets are same, one of them is output.

Note 4: The differential pin pair is output “Pin name1 –Pin name2” as the format. Note 5: The differential net pair is output “Net name1 –Net name2” as the format. Note 6: When the E-net environment is “OFF”, they are not output.

<Path>

• Path Name • Max Delay • Max Length • Max Skew Length • Max Skew Delay • Min Delay • Min Length • Electrical Net

Note 1: When the property is undefined, it is not output. Note 2: When all properties are undefined, Path names are not output, either. Note 3: When the E-net environment is “OFF”, they are not output.

<Bus>

• Bus Name • Max Zo • Max Xtalk • Max Delay • Max Length • Max Skew Length • Max Overshoot • Max Skew Delay • Min Delay • Min Length • Stimulus • Electrical Net • Path

Note 1: When the property is undefined, it is not output. Note 2: When all properties are undefined, Path names are not output, either. Note 3: When the E-net environment is “OFF”, they are not output.

87


5- 2 Design Rule Edit GUI

Design Rule Edit Tools

Summary There are 3 types of Design Rule Edit Tools in CR-5000 products different from situation they are used. They are A. Design Rule Library from PCB Design / Manufacture Common Tool B. Design Rule Editor from BD / PP / PS C. Design Rule Editor from DFM Minor changes are made for type B and C. B. Section for Design Rule Name is added. C. Sections for Design Rule Database path and Design Rule Name are added.

Enhance

This sample picture doesn't have the design rule name. When the data was updated by “Update File Version” tool, it would be same as the left picture.

88

Chapter 6 Design Preparation Tool

6-1 Support of constraint DB - Forward Annotation 6-2 Update Component from CDB


6- 1 Support of constraint DB - Forward Annotation

Specifying the properties that reflect from SD by the resource file

Summary The Pinpair that is set by BD can not reflect to SD by Backward Annotation. Therefore the Pinpair information is deleted after Forward Annotation is performed. Of course, the topology that is indicated by “Pinpair neighbor's flag” is also deleted. The spec is the same at Rev9. But our customers have to set Pinpair information on BD again after performing Forward Annotation. Rev9 can specify properties that reflect from SD for getting rid of this. It is specified by the resource file. At “Pinpair neighbor” property isn’t updated when the property is not defined by SD.

Details The resource file is as follows. $ZPLSROOT/info/dsnrule.rsc $CR5_PROJECT_ROOT/zpls/info/dsnrule.rsc $HOME/cr5000/pls/dsnrule.rsc

The next is a sample format. The “DsnRule*Pin” section specifies regarding Pin property.

Enhance

DsnRule*Pin {

("driverKind" CLEAR)

("ICX_SERIES" CLEAR)

("ICX_PORT_TYPE" CLEAR)

("enetSeries" CLEAR)

("pinComment" CLEAR)

("placementGroup" CLEAR)

("decoupleDist" CLEAR)

("powerPinGroup" CLEAR)

("Stimulus" CLEAR)

("nominateddriver" CLEAR)

}

Property Name

When the specified property value isn't transferred from SD, it is done according to the next setting. KEEP …..Not delete CLEAR …Delete

90


Note : Properties that can be specified are limited. Please confirm dsnrule.rsc from Online help before you specify it.

Keeping “Pinpair neighbor's flag”

Summary The “Pinpair neighbor's flag” is kept by Forward Annotation even if the definition is not on SD. This property can be kept regardless of resource file “dsnrul.rsc".

6- 2 Update Component from CDB

Keep In-component figure

Summary There was a problem in updating Padstack, Pad, and edited general figures from update utilities. Though there are options to keep existing Padstack, Pad, and general figures in update utilities in BD, under certain conditions, these options to keep existing data were ignored. This problem is solved by the improvement of the internal process.

Detail Problem in former versions There are 2 cases when keep in-component object option is ignored. Reset “Excluded” Pad status in the Padstack Excluded status for non-conductive Pads in the Padstack were cancelled even when option to keep in-component Padstack is ON. This occurs when changes in number of layer or relation of non-conductive layer to board layer was made by update utilities. Reset Pad and edited figures When entire pad figure or general figure is deleted from the certain layer, option to keep in-component Pad figure and general figure are ignored. This update condition was stated as limitation in online help. This is revised and update utility will keep the figure deleted after footprint library update. Above 2 problem existed in following utilities. - PCB Technology / Component Update Tool - Update from CDB Library command - Swap Components command (Footprint Reset mode) - Footprint Spec Name Reflection program

Enhance

Enhance

91


Following is internal update flow and how to read the table. Each step corresponds to columns from left to right.

1. Memorize FTP Lib. figure before update. (Local library) 2. Memorize current footprint figure on the board. 3. Copy the current footprint condition to the buffer area. 4. Read updated FTP Lib. 5. Compare 1 and 4 and see whether if figure is added or deleted. If

the Pads or general figures were newly added, then reflect the change. No changes are reflected for Padstack.

6. Whether to keep the Pin Ref. Point or not.

1. Padstack

No Footprint before update

Data condition on the board

Data copied to the buffer

Footprint after update

Result:

Data on the board after update

Keep pin reference point?

1

Yes

2

Yes

3

Yes

4

Yes

5

Yes

6

No

7

Yes

8

No

9

Yes

R I I

S I,R

Reference Object Reference Object & Instance No Object Deleted Object

Instance Object General Figure Instance Symbol Mark

R R R R R

R R R

I IR I R

R I I I

R

R R

R

R

R R R R R R R R R R

1 2 3 4 5 6

92


10

Yes

11

Yes

12

Yes

13

Yes

14

Yes

15

Yes

16

No

2. Pad





Result: Data on the board after update


1

Yes

2

Yes

3

Yes

4

Yes

5

Yes

6

No

7

No

8

No

9

Yes

R R R R R R R

R R R R R

R R R R

R R

R R

R R R R R R R R R

R R R R R R R R

R R R I R I IR

R R R R R

R R R R

I IR I R

R I I I

R R

R

R R

R R R R R R R R R R

1 2 3 4 5 6

93


10

Yes

11

Yes

12

Yes

13

Yes

14

Yes

15

Yes

16

No

3. Symbol Mark







1

No

2

No

4. General Figure (Edited)







1

No

2

No

3

Yes

4 Yes

S S S

R R R R R R R R R

R R R R R R R

R R IR R I R R R I

R R R R R R R

R R R R R

R R

R

R R

R

R R R R R

R R R

I IR I R

R I I I

1 2 3 4 5 6

1 2 3 4 5 6

94


5

Yes

6

No

7

No

8

No

9

No

10

No

11

No

12

Yes

13

Yes

14

Yes

15

Yes

16

No

R R

R

R R

R R R R R R R R R R

R R R R R R R R

R R R R R R

R R R I R R I I II,R

R R R R R I I,R

R R R I I,R

R R R R

R R

95

Chapter 7 PC Board Shape Edit Artwork

7-1 Support of dimension line without dimension arrow 7-2 Unified specification of duplicated hole 7-3 Interactive design/Function to check DB consistency


7- 1 Support of dimension line without dimension arrow

Adding the dimension variation

Summary Currently there is the following variation at dimension line. In Rev9, moreover adding another variation of dimension line And ZFC also supports this mode.

• Linear Dimension • Diameter/Radius Dimension • Angle Dimension • Leader • Linear Dimension (Without Arrow) This is new

Operation

1. Select [InPut] [Documentation] [Dimension].

2. Click . The panel menu appears.

A

B

C

E

Add

Horizontal Vertical

B. Specifying Angle • Horizontal • Vertical • Parallel • Perpendicular

A. Specifying input value (User-defined, Length, Width, Height, Thickness,

Diameter, and Radius)

C. Specifying the position of the dimension text

E. Specifying the angle of the dimension line

D

D. Specifying the tolerance value

97


Other effective Tools • Footprint Editor

7- 2 Unified specification of duplicated hole

Unified specification of duplicated hole between Drill Tool and Hole drawing

Summary The drill tool can skip duplicated hole. But the hole drawing doesn't have the same function. Therefore when you create drill data with “Skip Same Point” mode and draw the hole drawing, hole count are different between drill data and hole drawing. In Rev9, adding the same parameter “Skip Same Point” to the parameter of hole drawing.

< Hole Drawing >

< Drill Tool > [Options] [Drill Option-Settings]

Enhance

“Skip Same Point”

98


Other effective Tools • Panel Tool

Note : When you create drill data without “sort” mode on drill tool, hole count between the drill data and the hole drawing may not be same count even if you set "ON" to the parameter.

<Case 1> At drill tool, the parameter “Skip Same Point” works consecutive same size holes. But at the hole drawing, the parameter always work because of the hole drawing doesn’t have sort mode.Therefore hole count may not be same count.

<Case 2> Slot hole and Square hole are expressed at drill tool. Therefore they don’t recognize as same position even if they are same position and same size.

<Case 3> At hole drawing, when the parameter “Symbol Type” is Pad and the appropriated pad doesn't exist, it is not counted.

99


7- 3 Interactive design/Function to check DB consistency

Adding the check DB consistency

Summary When objects are input, edited or deleted, the check function automatically works. And if the illegal object is found, the tool is aborted forcibly and the next dialog is displayed. At that time, the details is stored into “.lock”file. You can find the illegal data at early stage. Until Rev8, when the customer edited the illegal data at Artwork tool, the next dialog was displaying.

You will recover the database file according to the above message. The recoverChk.html describes the next.

Note : If you don’t need this check or don’t want to work it, please set the next environment variable value. The check becomes invalid.

ZPMS_DB_CHECK=skip

New

When the database check file exists, it is also copied.

・When the target is PCB file. copy a.pcb.lck tozuken\a.pcb.lck

・When the target is PNL file. copy a.pnl.lck tozuken\a.pnl.lck

*When the OS is UNIX please use “cp” command.

100

Chapter 8 Floor Planner Placement/Wiring

8-1 Floor Plan Design Flow 8-2 Correction Process between PCB-RUL 8-3 Constraint Database Unification 8-4 Hierarchical Reference of net rule 8-5 Area DRC 8-6 Component DRC 8-7 Rebuild Electrical Net command 8-8 Topology 8-9 Synchronized Selection 8-10 Synchronized Selection from Design Rule Editor 8-11 Active 45 routing command 8-12 Copper Ratio Distribution 8-13 Edit Interstitial Via 8-14 Divide Board 8-15 Cross Glass 8-16 Abolition of “bdplist” 8-17 Control Layer Setting Columns 8-18 Standard ASCII I/O (Rev8 Rev9)


8- 1 Floor Plan Design Flow

Starting Lightning Floor Planner from SD

Summary There are Floor Plan tools for CR-5000 (BD optional module, Lightning Realize, P.R.Editor). These tools require steps in order for circuit designer to simply try floor planning. It took following steps Rev.8. - Output Net list. - Generate New Board with complete sets of design rule and components. - Convert BD data into Lightning data from Lightning I/F. - Start Lightning floor planning. Rev.9 System Designer will provide tool to start Lightning Realize or P.R.Editor for floor planning. Following is a flow of design data using the floor plan tool. In order to start the floor planning tool, SD will first create temporary BD board data and then create CTF file for Lightning. This process is done from Floor Plan Startup Tool.

Circuit

Conversion Program

Floor Plan data

Floor Planner (Lightning Realize)

Circuit Design Board Design

Floor Planner Startup Tool

Board Design

Case II Temporary design environment is

applied to floor plan data.

Board Design

Continue with generated

Board Design

New Board Generation

Board Design

Generate Board Design and import

placement information

Case I Case when same design

environment is applied to floor plan data.


New

102


Operation Floor Plan Startup Tool is to support starting floor plan. What was done manually by designer is now guided by the tool. 1. Start the utility from System Designer Utility or Design File Manager. 2. Set up the startup tool then execute. Following settings are needed. - Circuit Name - Design Rule Name - Board Shape and Layout Area size 3. Set temporary package and footprint if some parts don’t have complete

information in Master Library. In this case, create the temporary library just for floor planning.

103


3-a. Assign temporary package name. 3-b Assign temporary footprint name. 4. Start floor planning with Lightning Realize or P.R.Editor. Tool to start from this dialog is defined in resource file.

104


Limitation Limitations of applying Floor Plan flow are as follows. - Cannot apply operation using “Temporary Part and Footprint” from

New Board Generation and from Forward Annotation. - Cannot update design against divided board design. - See online help, “Floor Plan Startup Tool” for additional limitations.

Floor Plan Startup Tool

Summary There are several functionalities in the flow to start to floor plan. This section explains detail of operation for Floor Plan Startup Tool. There are 3 situations to use Floor Plan Startup Tool. Case A Start floor plan from scratch. (Floor Plan Board Generation) Case B Update existing floor plan data. (Forward Annotation) Case C Start the floor plan tool with existing design. See description for case A, B, and C.

Detail Floor Plan Startup Tool dialog As explained in the floor plan flow, startup tool generate board data first and covert it to Lightning floor plan data. 1. Output net list (A, B)

When Floor Plan Startup Tool is started from Sheet Editor, net list is automatically generated. When it is started from DFM, select whether to output net list or use existing one. The process to generate net list is same process as running Netlist Processor for circuit design. If the circuit has error and fail to output net list, startup tool will report error.

Sheet Editor Design File Manager

Generate new net list

New

105


2. Update Schematic Change and Start Up (ON A, B ; OFF C)

When this check is ON, tool will either generate floor plan board or update existing board before starting the floor plan tool. When this is OFF, tool will start floor plan with existing floor plan board.

3. Design Rule Name (A)

For floor planning board, design rule can be a temporary rule. In case of applying same design rule as actual board design, it is possible to continue the design after floor planning is complete. To apply this operation, it requires a setting in floorplan.rsc file. ( floorplanBoardCheck = Off Case I)

In case of applying temporary design rule, component placement information can be applied to the actual board when the board is generated. ( floorplanBoardCheck = On Case II)

When the board is generated with “floorplanBoardCheck = On” board cannot be opened by Wiring/Placement module.

4. PC Board shape/Layout Area (A)

The size of board and layout area can be either copied from existing design or specify width and height.

5. Set Set up tool (A and B)

To start floor plan from the scratch, set up the tool from dialog A. To update the design, set options in dialog B.

Case A Case B

106


Directory and file structure This is a structure of circuit design and Floor Plan data. If floor plan data structure don’t exist, tool will automatically create them. 1. xxx.pcb and xxx.rul is generated with xxx.ctf file rule. 2. If the xxx.ctf (Lightning constraints) file doesn’t exist under floor plan

directory structure, tool will copy the xxx.ctf file to floor plan directory structure and apply it to floor plan data.

Resource File Parameters for startup tool are defined in resource files with following priority. 1. $HOME/cr5000/ue/info/floorplan.rsc

2. $CR5_PROJECT_ROOT/zue/info/floorplan.rsc 3. $ZUEROOT/info/floorplan.rsc. Here are examples of parameters. - Read destination file readDestination: Off #On - Unit of generating board unit: mm # mm/inch/mil/micron - Start up tool type (Realize or P.R.Editor) floorplanTool : Realize #P.R.Editor - Temporary design flag. ( floorplanBoardCheck ) floorplanBoardCheck : On #Off

1

2

Floor Plan data fromCircuit Design

XXX

floorplan

bd

XXX.cir

ext

XXX.pcb

XXX.rul

hotstage

data

XXX

XXX.ctf

XXX.ctf

XXX.ruf

XXX.ndf

107


Temporary Component Assignment dialog

Summary During generation of floor plan board, some part may not have complete package and/or footprint defined. As long as part objects are registered in part library, it is possible to run floor plan tool with temporary package and/or footprint objects. If such part is used in the circuit, Floor Plan Startup Tool will opens dialog to assign temporary package and footprint object to the part. These temporary setting can be updated once after master library has officially defined package and/or footprint to the part.

Detail When there is more than 1 part without package or footprint defined in the master library, following dialog will appear after executing Floor Plan Startup Tool. <Temporary Component Assignment> In the dialog, assign temporary package name and/or footprint name to the incomplete part. Then start “Temporary Package Editor” or “Temporary Footprint Editor”. When temporary package or footprint is defined for the floor plan board, temporary CDB library is generated under following directory structure. In addition, “xxx.csv” file is saved with temporary library to store assignment of package and footprint objects for the board. After library condition is changed in Master or Temporary CDB, select Refresh from the View to update the mark. <Priority of library reference> Assignment dialog will refer to library in following priority. If same object is found in both CDB, master CDB is referenced.

Does not exist in Master CDB

Exist in Master CDB Printed Part

Exist in Temporary CDB

Need to assign temporary object

Master CDB > Temporary CDB

New

108


<Search Dialog> When search dialog is opened from component assignment dialog, package and footprint will refer to part information and filter existing object names in master library and temporary library.

Note : Package without footprint definition cannot be searched. Pin count is not fixed.

To register temporary component objects, select Open from assist menu. This will open Temporary Package Editor or Temporary Footprint Editor.

Search for Package Search for Footprint

Assign temporary object name and start edit tools for the object.

109


<Temporary CDB location and Component Assignment CSV location> When temporary object is generated, it will be stored under following path from circuit design. Temporary component assignment is saved along with libraries.

Temporary Package Editor

Summary Similar to Package Editor, Temporary Package Editor has limited functions to assign necessary attributes for the packages.

Detail Start the editor from Temporary Component Assignment dialog. Set followings in the editor. - Package Type - Footprint Spec Name (Select Only) - Footprint Name - User defined attributes Then save and quit the editor. Return to the assignment and select Refresh to update the relation. If the footprint is not in master or template library, tool asks if you want to register the footprint.

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110


When the package is saved in the temporary library, mark changes to mark. In addition, package will have attribute assigned to tell that it is temporary package.

Temporary Footprint Editor

Summary In the same manner as setting the package, set footprint object name in the Temporary Component Assignment. Temporary Footprint Editor has shaved functionality compare to Footprint Editor. This is to utilize Parametric Registration and limit the information so that designer can save time to register temporary footprint.

Detail <Reference a Master Footprint Library> Temporary Footprint Editor will automatically refer to master footprint library and copy Footprint Layer Definition, Pad objects, and Padstack objects to temporary footprint library every time start the editor.

Note : If layer with different attribute but same layer name exist between master library and temporary library, tool will report copy error.

New

111


<Package Type> When the editor starts, it refers to package type if defined. Then automatically starts parametric generation dialog according to the package type. (Package type AXIAL, RADIAL DTP, QTP, SMD-CONNECTOR, INS- CONNECTOR, SMD-OTHER, INS-OTHER, and Undefined will open Select Shape dialog. CHIP will open 2-TERM-CHIP or 3-TERM-CHIP) <Parametric Generation> There is a difference in Parametric Generation from Rev.8. Parametric Generation can apply Pad for terminals. There are 4 changes made to support pad terminal. - Pad placement layer - Pad parameter radio button - Pad name definition cell (Entries change according to package type.) - Term (terminal object) pull down list

Note : Some labels in dialog had changed word “Padstack” to “Term” (terminal) due to support of pad terminal.

DIP Type Package

DIP Parametric Generation

112


<Temporary Footprint Editor> Temporary Footprint Editor has limited functionality compare to Footprint Editor. Since the object is used temporarily, editor does not have function to edit or input objects. <Temporary Footprint Object> Just as temporary package object, footprint will have given an attribute to tell that it is a temporary footprint.

Report Temporary Component

Summary When the placement is done in Lightning Realize or P.R.Editor, design is brought back to BD. When temporary package or footprint is used in the design, it needs to be replaced with the one in master library. To find if there are any temporary objects on the board, the function is provided to report such objects.

Detail Start Query command in the Placement/Wiring Tool. In the PCB Data mode, select Temporary Component.

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113


Note : For components temporarily assigned in the Temporary Component Assignment dialog, part attribute is added with following attribute and value.

attribute name : temporaryMapping

value : pkg-ftpAB temporary package and A,B temporary footprint. pkg-ftpA temporary package and A side temporary footprint pkg-ftpB temporary package and B side temporary footprint pkg temporary package only ftpAB A,B side temporary footprint ftpA A side temporary footprint ftpB B side temporary footprint

Temporary Component Information Update Program

Summary When design is to be continued from floor planning, temporary component may exist in the design. They need to be updated when a proper component is ready in master library. A program is provided to replace the temporary component with the one in master library.

Detail Update program will compare component information with the one in the library and update to latest information in following cases. Following is an example of executing the program. In above case, the program will compare component information with library and update all package and footprint found in library. Then delete unnecessary package or footprint object from the board. If replacements for temporary objects are not found, they will not be updated.

Note : The program is almost equal to “Footprint Spec Name Reflection Program” (ftsback) except for following 2 cases

- When no package is specified in the part library - When no footprint is specified in the package library

In “Footprint Spec Name Reflection Program”, above 2 cases are reported as error, where “Temporary Component Information Update” report them as warning.

mpupdt.exe –m slim c:\data\sample

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Copy Component Placement Information

Summary Board Designer can import placement information from a floor plan design when generating a new board. This is to utilize the floor plan design information to board design.

Detail When a floor plan is designed with different design rule, or design in “Floor Plan Only” design mode (floorplanBoardCheck : On), designer may need to import placement information from floor plan design. When the board is generated for floor plan design in “Floor Plan Only” mode, generated board data cannot be opened by BD main modules. In this case, designer can copy placement information from the board. <Copy Component Placement Information> The program “Component Information Input/Output” program is added to the new board generation process and copy the placement information from the floor plan design. <Default PCB path for Component Placement> Copy Component Placement Information is automatically filled when the “xxx.pcb” and “xxx.rul” files exist at above relative path from “xxx.ndf” and “xxx.ruf”.

XXX

floorplan

bd

XXX.cir

ext

XXX.pcb

XXX.rul

XXX.ctf

XXX.ruf

XXX.ndf

Add

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What will be improved by Rev10?

Summary The reason why the Floor Planner officially supports from Rev10 is that it has a few problems. The problems are as follows.

• It can not register a new part as a temporary part • At registration of temporary footprint, the pin count is not

considered • It can not share the information (e.g. Library) with Lightning

Scenario • Constraints are removed • It can not input the board shape • It can not consider Layer counts(Add or Delete layer count) • The constraints can not be inherited

At Rev10, above problems are improved. Therefore current spec will have big difference from Rev10. There are other problems regarding to the operability.

Detail The following function will be added.

• Registration a new part information as a temporary part(Generic Part)

• It can edit the board shape • It can change the layer count (change the technology) • The pin count of the part is considered when the temporary

footprint is registered.(The pin count is automatically set on the parametric editor.)

• The project structure is changed. Please see the next page for detailes. (At Rev10, the update tool from the Rev9 project structure to Rev10 is not provided. So if you introduce to your customers this function at Rev9, also please inform this notice.)

116


Rev9xxxx

hotstage

templates

sd

scenario

bd

data

floorplan

xxxx.cir

pcb rul

simlib

xxxx ctf

hotstage

templates

scenario

bd

data

pcb rul

simlib

xxxx ctf

xxxx

ctf

The project tree already exists（BD, LT data）

The project tree is only for Floorplaner (BD,LT data)

The constraints is reset

They can not refer each other

Rev10xxxx

sd

xxxx.cir

hotstage

templates

scenario

bd

data

pcb rul

simlib

xxxx

ctf

ctf

They can use constraints and libraries each other

Unify to the project structure same as others

The plan is not be fixed It is a current plan

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8- 2 Correction Process between PCB-RUL

Correction Process

Summary Internal process is introduced to resolve problems of inconsistent PCB and RUL information. When net, component, or pin are added/deleted in the design, PCB and RUL will be inconsistent until designer performs B/A or F/A.

Detail Internal process will resolve the situation by updating RUL information. This process was planned to perform automatically, however due to technical difficulties, process runs only for following cases. • Rebuild Electrical Net • Opening PCB data. • Forward Annotation during Communication between SD/BD.

Followings are known functions that may be affected by inconsistent PCB and RUL. Rev.9 will use inconsistent status as they are (just like Rev.8). • EMC Advisor • Cursor Information Dialog • ZFC • Design Rule Editor (Net Object Dialog) • bd2ctf • ctf2bd • bd2hs • hs2bd • Lightning SI-Epilog • Topology (Internal Utility to set Topology)

Enhance

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8- 3 Constraint Database Unification

Electrical Net Design Environment

Summary Database for electrical net has extended in Rev.9 to adapt to Lightening design constraints. There are differences between E-net design and net design.

Detail Design Environment Electrical design environment becomes effective when either one of following condition is applied in the design. - PCB design already has E-net objects in the net object. - board resource file have following setting. Differences in Design Rule Following is a table to show differences in E-net design ON and E-net design OFF. ( --- Available , N/A --- Not Available , * --- Grayed out )

Functionality E-net Design ON

E-net Design OFF

Display of E-net N/A Generate Topology N/A Topology Style Attribute * Default Setting Display of Bus (Tree view, Functionality) N/A Display of Path (Tree view, Functionality) N/A Display of E-net pin pair (Tree view, Functionality) N/A Pin pair tree view Under E-net Under Net Pin pair neighboring flag ON/OFF Display of Differential Pair (Tree View, Functionality) N/A Create Differential Pair Function (Assist Menu) * Display of E-net Class (Tree View, Functionality) N/A Display of Net Class Reference and setting of new net attributes Reference and setting of E-net attributes * Reference and setting of new Pin attributes Reference and setting of Swappable attribute * Setting and deleting of Swappable attribute (Assist *

################################################# # Electorical-Net Flag [On/Off] useENet: On

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119


Menu) New attributes for Pin pair group New attributes for Pin pair Pin swap for swappable pins (Functionality) N/A Pin swap for swappable pins (Assist Menu) *

Limitation - Once the E-net environment is set for design, E-net environment can’ be turned

OFF in BD. - When you open Design Rule Editor from DFM with “UseEnet=On” in board.rsc

file, E-net will be assigned even when you do not save the data.

Additional of New Net Objects (Class)

Summary Following net objects exist in Rev.9. Names in blue are new net objects added in Rev.9 <Board Level> - Default settings <Net Objects> - Net group group - Net group - Net class - Electrical Net class - Bus - Path - Differential pair - Net <Pin Objects> - Pinpair group group - Pinpair group - Pinpair

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Default Settings

Summary New net object is added from Rev.9 called Default Settings. Default Settings defines attribute values for board level. The value defined for Default Setting is applied according to the prioritized reference rule for each attribute. All objects may refer to Default Setting value. This will work as template value for objects with same attributes. example - Max Stub Length This value is referred by Area DRC (Topology check) and Wiring command. Even if the value is not defined for E-net, commands will refer to default setting and apply the value. For detail of rule reference priority, please refer to online help.

Net Class and Electrical Net Class

Summary New objects are added from Rev.9 called Net Class and Electrical Net Class. Net Class and Electrical Net Class is template setting for net and E-net object. This means that: - Net and Net Class has same of attribute. - Electrical Net and Electrical Net Class has same of attributes. The difference is priority of rule reference.

Enhance

Enhance

121


Detail By becoming a member of Net Class or Electrical Net Class, default setting can be applied for members of the class. Effective Function For example: - DRC - Wiring Command example – Shield Gap The value is referred by Wiring command. For this attribute, there is fixed rule reference priority. According to above setting following settings are applied for Shield Gap. (When value is not defined for E-net.) SIGN159 = 3.000 SIGN164 = 1.000 SIGN165 = 2.000 (from Netclass2) SIGN525 = 2.000 (from Netclass2)

Limitation A net can become a member of 1 Net Class only. An E-net can become a member of 1 Electrical Net Class only.

Net > Electrical net > Net class > Electrical net class

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Bus and Path object

Summary Net object class call Bus and Path is added in BD database to adapt to Lightening database. Functions for Bus and Path by Rev.9 are as follows.

⋅ Displaying Bus and Path (They are set by Lightning) ⋅ Deleting the object ⋅ Changing of attribute value that each object already posses

Creating new Bus or Path is not supported.

Detail Here is brief explanation and sample of each object. For detail of Bus and Path, please refer to Lightening online help. <Bus> Bus is group of E-nets or Paths in bus connection. Member of this class can be either group of E-nets or group of Path example – Max Delay [ns] The value is referred by Area DRC. This value is used to check length of wire according to the board thickness and dielectric constant. [DRC for Pin pair] In case of checking delay of pin pair, DRC will refer values defined for Max Delay in following objects and apply minimum value found. - Pin pair - Electrical Net - Pin pair group - Bus - Differential pair - Electrical net class - Default settings

Add

E-net1 E-net2

Path

BusDelete operation only

123


Note : In Lightning, Bus can also retain pin pair group as member. In Rev.9 handling or display of pin pair group under Bus is not supported. The bus name will be shown after the pin pair group name under pin pair group branch.

<Path> Path object is kind of E-net group in sequential connection with passive component(s) in between. Currently, there is no function that refers to the value defined for Path attributes.

Differential Pair

Summary BD will support differential pair class from Rev.9 which already exists in Lightening. To adjust to this change, Pair Routing will also refer to differential pair net class objects in Net Objects dialog.

Detail New Differential Pair There are 2 ways to add member to differential pair. - Select 2 E-nets from Net branch and set as differential pair from assist menu. - Select 2 pins belonging to different nets in the same E-net. Note : Conversion of following settings will take place during data version

update. - 2 nets in 1 Net Group with parallel wiring setting. - Nets with Pair Net name

Note : Setting of Pair Net name in schematic will be converted to differential pair during new board generation.

Operation 1. Set Differential Pair In the Design Rule dialog, select 2 E-nets. Or select 2 pins from different nets under same E-net.

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124


2. Define Differential Net Pair and Differential Pin Pairs Edit differential pin pair and differential net pair by selecting Edit member from assist menu.

Effective Tool Differential Pair Routing command, which existed in Package module has now moved to Placement/Wiring tool. When using this Differential Pair Routing following spacing rule is referenced. <Operation> 1.Define Differential Pair Spacing Define a value for differential pair spacing.

125


2. Differential Pair Routing command Start Edit Differential Pair Routing and select nets to apply pair routing.

Limitation Setting differential pair nets - Topology for differential pair cannot be changed. It can only refer to. - E-net can be a member of 1 differential pair. - E-net can’t be a member of differential pair when it has topology defined. - Differential pair can’t be set in the Design Rule Editor started from DFM. - When FA is done, the differential pair settings will be gone.(Rev9.000R2)

Future Plan (At Rev10) Supporting Differential Pair Object by SD/DG.

Select Dif. Pair Net

Pull out pattern Pull in pattern

126


Pinpair in Net Object dialog

Summary Electrical net pin pair is added to the database. E-net pin pair is a pin pair going across nets within the same E-net. Here are functionalities in the Net Object dialog. - Add/Delete of E-net pin pair - Add or Delete pin pair at once - Pin swap becomes available for topology type Daisy and Bus. - Define Pin Swappable attribute for pin. - Define Stimulus and Driver Pin. - Pin Swap

Detail E-net pin pair will be listed under E-net in the Net tree and Pin pair tree.

Icon Pin pair type ・ Same net between 2 pins

・ Pinpair neighboring flag = OFF ・ E-net pin pair

・ Same E-net between 2 pins ・ Pinpair neighboring flag = OFF

・ Pinpair neighboring flag = ON ・ Without Stub

・ Pinpair neighboring flag = ON ・ With Stub

127


Add/Delete of E-net pin pair objects Just like pin pair setting in Rev.8, click the “Add/Del Pinpair” button to open dialog. Select pins to add pinpair and select pinpair to delete member. It is impossible to add or delete pinpair when Neighboring flag is ON. Pinpiar Neighboring flag Pin pair Neighboring flag is automatically assigned to pin pair when topology is set. Pin pair created with topology style setting will have “Pinpair neighboring flag” as ON. There is no way to change this value and they will be referenced by “Add/Del Pinpair” operation. - Add at once will add pin pair with “Pinpair Neighboring Flag” OFF. - Del at once will delete pin pair with “Pinpair Neighboring Flag” OFF.

Pin pair for E-net with topology style There are 2 cases for re-creating pin pair. 1. Topology is already defined for E-net When topology is changed, tool will automatically cancel existing pin pairs and create pin pair according to new topology style. 2. E-net has pin pair, but topology style has not been set When new topology is set, tool will automatically create pin pair and overwrite existing pin pair if same pin pair already exists.

128


Nominated Driver and Stimulus setting When performing simulation from BD, it is possible to set stimulus file name and driver pin in the Net Objects dialog. This will reduce step to run simulation with Lightning SI-Epilog. Stimulus file name must be selected from the list which is obtained from following directory files with “.stm” extension. Swappable pin setting Swappable setting is for Wiring command (rats nest display) to automatically reassign rats nest connection between pins with same “Swappable” group. example) Setting 2 Swappable value for daisy chain topology pins. Note : Swappable can be defined for pins in Daisy or Bus topology Enet.

Note : To avoid having same “Swappable” for non-neighboring pins after

“Swap Pin”, “Swap Pin” will be disabled when “Swappable” is defined. “Swappable” need to be cancelled by “Unset Swappable” to “Swap Pin”.

$HOME /red_data/templates/stimili/

Rats nest automatically swaps pin connection if same “Swappable” value is set.

Swappable_BLUE Swappable_ORANGE

Swappable setting for pins

129


Swappable Check Swappable Check will run internally and refer following points about selected group of pins. Pins can be set as Swappable when they meet all condition. - All pins belong to same net - Topology is Daisy Chain or Bus - Pin I/O attributes are same all pins - Pin I/O is not NOSWAP for all pins - Selected group of pins are adjacent Pin Swap The function to swap pin is available in Pin Attribute Table to change the pin pair for topology point of view. Select 2 pins in the table and select Swap Pin from assist menu. Pin swap is available for receiver pins in “Daisy” and “Bus” topologies. When pins are swapped, existing pin pair will be canceled and will be created with new combination of pin pair with swapped pins. When pin has “Swappable” defined, they can’t be swapped. example) Swapping P2 and P3

Pin pair P0 – J1 J1 – P1 J1 – J2 J2 – P3 J2 – J3 J3 – P2 J3 – P4

Pin pair P0 – J1 J1 – P1 J1 – J2 J2 – P2 J2 – J3 J3 – P3 J3 – P4

P1 P2 P3

P0 P4

J3J2J1

P1 P3 P2

P0 P4

J3J2J1

130


Pin Swap Check Pin Swap check will refer following points about 2 selected pins. Pins can be swapped when they meet all following conditions. - 2 pins belong to same net - Topology is Daisy Chain or Bus - Pin I/O attributes are same for both pins - Pin I/O is not NOSWAP for both pins (Not E-net series component pin)

Edit Differential Pin Pair

Summary After the Differential Pair is created in the Net Objects dialog, it is possible to edit the Differential Net Pair member and Differential Pin Pair member.

Detail Differential Net Pair and Differential Pin Pair are related. Change made in either group member would have effect on another group. To edit member, select Differential Net Pair or Differential Pin Pair then click Edit Member from the assist menu. This opens “Add/Del Differential Pin Pair*Differential Net Pair” dialog. Rule for creating Differential Pin Pair Select pin names from list 1 and list 2 to create differential pin pair. When you define a pin pair, you also define a net pair at same time. Once the net pair is decided, then you can only create pin pair with same net combination or pin pair with nets not already in the Differential Pin Pair List. Error is reported when selecting (1) same pin or (2) pins belonging to same net are selected from list1 and list2. Also when (3) pin pair with net name already used with different net pair.

New

131


(1) Same pin (2) Pins in same net (3) Net pair with “GREEN” already exists in combination with “SIGN973”.

Board Design Rule Editor Utilities

Summary Customize utility and Design Rule Check utility has adapted to new attributes in the database.

Detail Customize The utility has new items to control display and editing of net rules. Attributes for following classes are now available. - Default Seetings - Net class - Electrical Net class - Bus - Path - Differential Pair Design Rule Check Following new checks are performed for Electrical nets. - Check for Max/Min Total Length - Check for Max/Min Length (E-net) - Check for Shield, Shield Net definition.

Limitation - Design Rule Check does not check net rule values in hierarchical way. - Check is performed only for Net and Electrical Net (above check)

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132


8- 4 Hierarchical Reference of net rule

Hierarchical Reference of net rule

Summary There are design rules that may have more than 1 object to define the design rule value. From Rev.9, most of design rules will refer to values defined in the hierarchical objects and apply the value according to the predefined reference rule.

Detail There are 2 types of rules to reference the design rule. < Refer to most strict design rule value defined for objects > example) Area DRC -> Minimum Wiring Length for a Pinpair

DRC will refer to following objects and apply maximum value found.

- Pinpair - Pinpair Group - Bus - Default

example) Area DRC -> Maximum Wiring Length for a Pinpair

DRC will refer to following objects and apply minimum value found.

- Pinpair - Pinpair Group - Net - Electrical Net - Bus - Differential Pair - Net Class - Electrical Net Class - Default

< Refer to net object rule in the hierarchical priority > example) Area DRC -> Shielding -> Shield Net Name for a Net

DRC will refer to value in following order and apply the value found first.

- Net - Electrical Net - Net Class - Electrical Net Class

Note : For the hierarchical reference of design rule, refer to online help, “Board Designer – Edit Design Rule – Referring and Editing Design Rule Database – Net Object” and find reference rule for each attribute and object.

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133


Query Command report

Summary Query command will report design rule defined for the target item. The command will refer to rule value according to a hierarchical rule. If the value is not from to the target object, command will report which object does the applied value belongs to.

8- 5 Area DRC

Support of Electrical Net

Summary In Rev.9, electrical net will introduce the idea of Electrical Net Pinpair. There are 4 DRC rules that support Electrical Net Pinpair. • Max/Min Length Check • Max/Min Delay Check • Matching Check • Same Delay Check

These checks will support Electrical Net Pinpair similar to Pinpair.

Net or Subnet Net Electrical Net Electrical Net Rule

Pin Pin Rule

Enhance

Pin Pinpair Rule (Use “Send Pinpair Name” in Net Dialog)

Improve at Rev9.010

134


Detail When topology rule is defined for Electrical net, check will complete for connected terminal pinpairs. It was required to complete whole wiring of net when topology was set.

Limitation When terminal of pinpair is junction, either for 1 end or both ends, check can’t be performed. Example : Check between P2 and P4 : Possible (enet pinpair) Check between P4 and J : Impossible (enet pinpair) Check between P2 and J : Possible (pinpair)

Max/Min Length Check Max/Min Delay Check

Summary Check length and delay for pinpair between, P1 – P4.

Improve at Rev9.010

netA netB

P1 J (Junction)）

P2 (pin) P3 P4 (pin)

P1

P2 P3 P4 netA

netB Passive Compone

t

Enhance

135


Matching Check Same Delay Check

Summary Check for pinpair group, such as P1– P4 (Red line) and P1 – P5 (Blue Line).

5- 6 Component DRC

Support of Topology

Summary As a part of constraints (design rule) unification, the idea of topology will be supported by following Component DRC check item. • MaxTotalLength Check (Label had changed from “NetMaxLength” check)

When one of following topology type is set for the net, the check will calculate sum of pinpair distance according to the topology rule. • Star • Remote Star • Daisy Chain • Bus With following topology type setting, check will apply same check method as Rev.8, which is to add up unconnected net length. • H Tree • User Defined type

Improve at Rev9.010

P5

P1

P2 P3 P4netA

netBPassive

Component

Enhance

Enhance

136


Example Case1) Case2) Case1 ) Case2) Measured MaxTotalLength = 14 Measured MaxTotalLength = 13

Note : “MaxTotalLength” does not check “MaxTotalLength (E-Net)”.

Support of Electrical Net

Summary As a part of constraints (design rule) unification, the idea of Electrical Net Pinpair will be supported by following Component DRC check item. • PinPairMaxLength Check

Detail The “Manhattan Length” between target pinpair is applied for the check. Following is the error message displayed in the error report.

Note : The “NetPinPairMaxLength” check is left as it was in Rev.8.

(Do not reference rules in hierarchical priority.) This check is to maintain function for checking length of unconnected pinpair. This function was unique in the way that it didn’t require pinpair setting. We will revise this functionality again in future release.

Improve at Rev9.010

( 0 , 0 )

( 4 , -1 )

( 4 , 0 )

( 4 , 1 )

( 0 , 0 )

( 1 , 1 )

( 4 , -1 )

( 4 , 0 )

( 4 , 1 )

Enhance

137


Pinpair Wire Length Gauge

Summary Move Component command will display diamond shape gauges for all Pinpairs and all Electrical Pinpairs that component pin belongs to. In former revision, it showed gauge(s) only for pin(s) that had unconnected line (rats net) between moving component.

Detail <Gauge Line> The diamond shape gauge shows following. • Dash Line – Pin is within the range of maximum wire length. • Solid Line – Pin is outside the range of maximum wire length.

<Net with 2 pins> Gauge is also displayed when maximum length is defined for a net with 2 terminals. (Same as Rev.8 function, but this method will not refer to rule hierarchically.)

Note : When unconnected line (rats net) are turned off when moving components, the gauge will refer to the setting and it will also be turned off.

Additional information (At Rev 9.010) Support for displaying gauge for differential pair by the settings of Max Wire length.

Improve at Rev9.010 Enhance

Driver

Receive

r

Max Wire Length

When the receiver was moved

ドライバドライバ

最大配線長最大配線長

レシーバレシーバ

Driver

Max Wire Length

Receiver

When the driver was moved

Driver

Max Stub Length

Receiver

Max Stub Length

When the passive part was moved

138


8- 7 Rebuild Electrical Net command

Rebuild Electrical Net

Summary There are 3 changes in Rebuild Electrical Net command. • Generate electrical net consist from 1 net. • Panel menu is removed. Define the setting in resource file. • Command will merge differential pair.

Definition of Exclude Net Header for E-net

Summary The panel menu for Rebuild Electrical Net is now removed. Definition of prohibited electrical net name header is now in board.rsc file.

Note : This change is same for Package Synthesizer and Package Predictor.

Merge Differential Pair

Summary When E-net with differential pair setting is entirely merged to other E-net, differential pair will also be merged.

Detail The command will merge differential pair according to following rule. - Maintain more complete differential pair setting, more than incomplete

setting. (See table for help) - Maintain differential pair existing under absorbing E-net, more than

absorbed E-net.

################################################# # The character sequence which is not # used for Electrical Net Name. # When inputting more than one, divide by " "(space). noUseENetHeader: ""

Enhance

Enhance

Enhance

139


The next is thought as the other case.

n1 n2

n3n4

A B

C D B C

A D

n1 n2

n3n4

A

C

Before Rebuilding Electrical Nets

After Rebuilding Electrical Nets

Differential Pair

Ａ,Ｂ,Ｃ,Ｄ are independent electrical nets

Command has merged B to A and D to C.

- -

A CDifferential Pair

n1 n2

n3n4

A B

CD

B C

A D

n1 n2

A

- Ｃ

A Ｄ

Before Rebuilding Electrical Nets

After Rebuilding Electrical Nets

Differential Pair

Differential Pair

Ａ，Ｂ，Ｃ，Ｄ are independent electrical nets

Command has merged B to A.The differential Pair (n2,n3) doesn't have electrical net pair, so it is deleted.

n3n4

CD

Differential Net Pair

(n2, n3)

(n1, n4)

Differential Net Pair

(n1, n4)

None

140


Report Electrical Net Change

Summary After Rebuild Electrical Net command, tool will report changes made in the board. Following is a example of report.

###Rebuild Electrical Net###

Electrical Nets Deleted

+12V -12V AGND GND SIGN543 SIGN554 SIGN562 SIGN566 SIGN568 SIGN570

SIGN583 SIGN585 SIGN586 SIGN593 SIGN605 SIGN760 SIGN761 SIGN961

SIGN963 SIGN964 SIGN967 SIGN969 SIGN970 SIGN973 SIGN975 SIGN976 VCC

Nets Added to Electrical Net

Electrical Net Name: SIGN755

SIGN760

Electrical Net Name: GREEN1

SIGN973 SIGN976

Nets Deleted from to Electrical Net


SIGN593


SIGN543

Electrical Nets : Topology Info Deleted

SIGN973

Differential Pair with Changed Electrical Net Pair

Differential Pair Name: SIGN554-SIGN555

Before: SIGN554 SIGN555

After: SIGN525 SIGN555

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8- 8 Topology

Setting the Topology Style

Summary Topology is added as a new attribute for E-net. In Rev.9, topology uses same utility as Lightning. BD will create CTF file and hand it to Lightning utility to configure topology attributes against E-net.

Detail There are following topologies that can be specified. - Star - Remote Star - Daisy Chain / Bus - H Tree

Add

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Following priority is applied when referring to Pin IO. Nominated Driver > IO attribute in the Rule > IO attribute in Part Nominated Driver becomes effective when IO attribute is “BIDIRECT” for rule pin or part pin attribute. When it is ON, topology will consider that pin as OUTPUT pin. Rebuild Electrical Net It is advised to run Rebuild Electrical Net when you failed to create topology, especially after design had been changed. E-net Series setting Error is reported when the E-net Series setting is not properly set. Board Designer will create CTF file and pass it to create topology. Therefore BD needs to recognize correct E-net. Error Cases Topology style setting will report error in following cases. - More than 3 pins have same E-net Series - No pin belongs to net. - E-net has Power or Ground attribute. (E-net shouldn’t be Power or Ground net) - Cannot set Bus topology when E-net has Series component. - Topology cannot be changed for Jumper component and Star Point

component. - Component with destination is in the E-net.

Branch Point on Stub Pin

Summary There is an idea of “stub” in Lightning that allows placement of pin away from branch point and not applying transmission line in between. From point of view that branch point can be placed on stub pin without the stub segment, tool will recognize stub pin as branch point when more than 2 patterns are connected to the stub pin.

Enhance

Rule pin IO is passed from SD Part pin IO is defined in CDB

143


* Stub Pin …. Pin that belongs to pinpair that has stub attribute. * Stub Attribute …. Pin that belongs to pinpair that has stub attribute.

Example (Star Topology) (Daisy Chain Topology)

Branch point on Stub Pin Branch point not on Stub Pin

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Branch Point on Stub Pin

Branch point not on Stub Pin

Stub Pin

Normal Pin

( 1 , 1 )

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Unconnected Line Display

Summary To display relation of net connection, unconnected line will be displayed according to the topology which is defined for the net. • The tool will display unconnected lines for following topology types.

- Star - Remote Star - Daisy Chain - Bus

Detail The display of unconnected net line is based on following process flow. <Process Flow> 1. Construct unconnected lines between Stub Pins. (Unconnected line will be displayed between nearest Stub Pins.) 2. Consider result of process “1” as if they are connected pin pair and

calculate rest of unconnected lines with normal pins. Example of Unconnected Lines

Topology Style With no PatternPartial PatternWithout Junction

Partial PatternWith Junction

Daisy Chain/Buswith Pin Groups

Daisy ChainBus

Remote StarCase 2

Remote StarCase 1

Star

Starwith 2 DriversCase 1

Starwith 2 DriversCase 2

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PinGroup PinGroup


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Limitation Electrical Net Display of unconnected lines for Enet is not supported. The tool will handle topology per net. Loop Net When loop pattern exist in the net, the result may not be the closest unconnected line. Topology Error When connected pattern is violating the topology rule, unconnected line will be displayed between nearest pins.

Future Plan (At Rev9.010) For user defined style, it can display recognizing stub and brunch.

H-tree also is supported by Rev9.010. Star, Remote-star, Daisy chain and Bus were already supported by Rev9.0.

<Current> <Rev9.010>

Ａ

Ｂ

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Stub pin pair

Virtual Brunch Point

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Virtual Brunch Point

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DRC for Stub Length

Summary DRC for Stub length is available. This function is effective in Electrical Net design mode.

Detail DRC checks distance of stub, which is length of pattern from branch point. It will report error when Stub length is longer than rule length. Check will refer to following rule objects and apply most strict rule from the candidate. (Smallest value) - Enet - Enet Class - Board

Limitation Branch Point on Stub Pin When the Branch Point is on the Stub Pin, stub length is 0.

Swapped Stub Pin When stub pin is swapped with a pin without stub setting, all swapped pins will be checked by DRC. Therefore, pin without stub setting might have error reported.

Followings are example of target stub.

Improve at Rev9.010

Star Remote Star Remote Star

New

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DRC Error Mark for Topology

Summary DRC error will be marked at location where topology error exists. Error was marked on one of the pin that belonged to the topology net.

Detail DRC will mark topology error for following cases. • Unconnected pin exists in topology • Unconnected pin exist and pattern is pulled out • More than 2 branch points exist for single branch point in topology Example Star topology error

Limitation - There will be only 1 topology error marked for 1 net. - Primitive coordinate can no longer be found.


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Guide with Topology

Summary There is guide line shown to target object when wiring an unconnected net. The guide will now consider the topology and limit the target object to show the guide line. Target of guide line is selected from objects with unconnected line attached to it. Example Star topology

Limitation Target of guide Guide function will select target from conductive object (single object) that has unconnected line shown between the wiring pattern. It will not consider the swappable pins. Cases of not showing unconnected line When the unconnected line is not displayed, guide will act the same way as former revision. (Guide to closest conductive object with same net name.)

Marks to show permissible Stub Length

Summary Permissible stub length is shown with diamond figure around the stub pin and flag mark on the pattern.

Detail Stub length is shown in the following cases.

Improve at Rev9.010

Improve at Rev9.010

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Diamond Figure Diamond figure appears around the stub pin when no pattern is connected to this pin. The diamond figure shows maximum stub length from the pin. Figure is shown during wiring command before net is selected. Flag Mark Flag is shown either on the branch point within the range of stub length or at the maximum length from stub pin. When branch point is already decided, flag will be shown on that point. ** Branch Point ** There are 2 exceptional cases when pattern is considered as branch point. - Point where wiring width is changed - Via is considered as branch point in Area DRC Topology check.

Cursor information Topology Style

Summary There is new option in Cursor Information Dialog to show topology information about the selected net.

Detail Activate the function by following steps. 1. Start Input Wire command. 2. Select from assist menu, Cursor Information --> Display Topology

Information Following line is added to the cursor information. - Topology Style Cursor information is displayed for following 6 topology styles. When topology is different from following styles, it is not reported. - Star - Remote Star - Daisy Chain - H Tree - Bus - User Defined

Maximum Stub Length

Maximum Stub Length or

Branch Point

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Rats net display during moving component

Summary It is possible to tell if topology is set for the moving component or not by finding “T” mark. However, the relation of pin connection can’t be updated unless the component is placed. This function is going to display rats net while moving the component.

Detail The display of rats net is different between following topologies settings. Star , Remote Star , Daisy Chain , Bus Display of rats net will follow rules of unconnected nets. However, while moving the component, function will not refer to existing conductor and refer to component pin only. - Rats net is shown for entire net while moving. - Net color is applied. - T mark is placed at pin on the moving component.

H Tree , User Defined Same method as Rev.8. - Rats net is shown for 1 neighboring pin in the topology net. - White color is applied for rats net. - T mark is shown at center of rats net. Without topology setting Same method as Rev.8. - Rats net is shown between closest pin. - White color is applied for the rats net. - T mark is not shown as net does not have topology.

Future Plan (At Rev9.010)

Improve at Rev9.010

Rev. 9 Rev. 8

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A net is twisted

Rev. 9000 Rev. 9010

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T mark for topology net

Summary It is possible to show or hide the T mark by setting in parameter.rsc or from option dialog.

Rats net for Decoupling Capacitor/ESD components

Summary In Rev.8, rats net between parent component and decoupling capacitor or ESD components weren’t shown when they were generated in PCB design. In Rev.9, rats net will be shown between parent component (such as IC) and decoupling capacitor or ESD components. This will help placing these components with referring to the relations between components.

Detail There are 2 ways to define relations between parent and child component. Placement Group for Component Property When component property has same placement group, power and ground nets will have shown rats net between nearest pin of parent component and child component in same group. Placement Group for Pin Property When pin property has same placement group, power and ground nets will have shown rats net between same group pins while moving the component. For pins without placement group, nearest pin between parent and child component is shown with rats net.

Limitation Placement Group for ground pin is invalid.

Pin Property Component Property

Display.CompDragTMark : on #off

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Display control options for rats net

Summary There are 3 new options for controlling rats net. For 2 layer board, there is no VCC or GND layer, so they need to be connected with conductive patterns. To help this operation, rats net can be shown for VCC and GND nets as well.

Detail Followings are new option settings for rats net. It is possible to set from Environment -> Option or in parameter.rsc file. Display control for power and ground rats net - Display All - Decoupling Capacitor/ESD only - Hide Display control for power and ground mark Display control for topology mark

8- 9 Synchronized Selection

Component Group Selection

Summary In the Move Component command, when a parent component is selected to move, related child components will automatically selected and move along with parent component. This is to help designer move components comes in set or to keep relative position.

Detail In Rev.9, following cases are considered parent-child component. In these cases, components will be selected according to the panel menu in Move Command. - Design Rule – Comp. Object – Component has Placement Group Name

defined. - Design Rule – Net Object – Pin name has Placement Group Name

defined. - Decoupling capacitor is generated for IC component. (Placement Group

Name is defined by the tool.) - Selected component is group of ESD component.

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Move Component with same Placement Group Name When this option is ON, components with same Placement Group will be selected. For example, Another example, selecting IC1, IC2, or IC3 will select all 3 components in following case. Note : Component outside of Layout Area will not be selected. Do not Select from Child When this option is ON, selecting child component will not select parent component automatically. Move Selected Components When several parent components are already selected and start move component with dragging, component related to the component being dragged will be automatically selected.

IC1 IC2 IC3

Pin #1 with Placement Group A

Pin #8 with Placement Group A and Pin #1 with Placement Group B

Pin #8 with Placement Group B

Select Parent Comp. Child component is selected

Select Child Comp. Parent Component is

Select Child Comp. Don’t select Parent Component

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Area Select and Toggle Select Components Select status of same Placement Group components will link when target parent component or child component is selected by Frame selection or Toggle selection (Click + Shift key). Refer to “Cases of Component Selection”. Components Outside of Canvas View When the component is selected outside of canvas, tool will report message in message area and make BEEP sound. Cases of Component Selection Followings are possible cases of selecting Placement Group components. ^

A

- - -Parent Component( IC, Sockets, etc)

- - -Child Component(Decoupling Cap.

- - - Parent of and Child of

- - -Already Selected components

- - - Placement Group is set for component or pin. (Group Name “A”)

- - -Frame Select- - -Select

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Single Select and Toggle Select

[Comp. in Placement Group] : ON [Do Not Select from Child] : OFF

No Toggle Status before selection and select operation

Status after selection

1 OFF

2 OFF

3 OFF

4 OFF

5 ON

6 ON

7 ON

8 ON

9 ON

10 ON

11 ON

12 ON

A B A B

A B A B

A

B

A

BC C

AB

A

BC C

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Frame Select and Toggle Select [Comp. in Placement Group] : ON [Do Not Select from Child] : OFF For No.5 and No.16, “Select” will be applied when selection of toggle conflicts between “Select” and “Unselect”



1 OFF

2 OFF

3 OFF

4 ON

5 *

ON

6 ON

7 OFF

8 OFF

9 OFF

10 OFF

11 ON

A B

A B A B

A B

A B

A B

A B

A B

A B

に B

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No Toggle Status before selection and

select operation Status after selection

12 ON

13 ON

14 ON

15 ON

16 *

ON

17 ON

Single Select with Do not Select from Child

[Comp. in Placement Group] : ON [Do Not Select from Child] : ON



1 OFF

2 OFF

3 ON

4 ON

5 OFF

6 ON

7 ON/OFF

A A

A A

A A

A A

A B

A B

A B

A B

A B A B

A B

A B

A B

A B

A B A B

A A

BB

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8 ON/OFF

9 ON/OFF

10 ON/OFF

11 OFF

12 OFF

13 OFF

14

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15

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16

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17 OFF

18 ON

19 OFF

20 ON

21 OFF

22 OFF

A A A A

A B A B

A A A A

A B A B

A B A B

A B A B

A B A B

A B A B

A B A B

A

B

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Resource File Option setting for Placement Group can be defined in parameter file. . Parameter Comment default

Layout.MoveComp.placementcomp Comp. in Placement Group off

Layout.MoveComp.noselfromchild Do not Select from Child off

Limitation Following selection will group select components. - Component Selector - SD (Cross Probing) Other select functionality does not group select components.

Parent and Child relation

Summary In Placement Group, an idea of parent and child component is used for selecting component. Followings are detail of definition of parent and child components.

Detail There are 3 types of parent and child relations. - Decoupling Capacitor - ESD Components - Oscillator Circuit Components



23 ON

24 ON

Enhance

A B A B

A B A B

$ZUEROOT/info/parameter.rsc

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Decoupling Capacitor [Parent component] - Component with 3 pins or more. - Connect target pin and GND pin is connected with decoupling capacitor. <Connect target pin> A or B

A. Placement Group Name is defined for pin. Pin is connected with power or normal signal. (Not GND net) B. Placement Group Name is not defined for pin, but for Component. If Power pin exists in “Part Pin”, then Power pin becomes target. If above pin doesn’t exist, pin with Power Net becomes target.

[Child component] - Component has 2 pins. - One of pin is GND pin. - Net for GND pin matches with one of parent component pin. - Net for non GND pin matches with one of parent connect target pin. - Placement Group Name for non GND pin matches with one for connect target pin. ESD Components [Parent component] - Component has 2 or more pins. - Component attribute (in Comp.Object) “ESD Part” is blank or NO. - Connected with ESD Part. [Child component] - Component has 2 pins. - Component attribute (in Comp.Object) “ESD Part” is YES. - One of pin is GND pin. - One of pin has same Placement Group and net name with parent component pin. - Both pin has Placement Group name defined. Oscillator Circuit Components [Parent component] - Component with most pin in the OSC Placement Group [Child component] - All components belong to same Placement Group (Pin or Component) with

components that have Placement Kind “OSC” defined for component attribute.

Handling of Decoupling Capacitor

Summary In Rev.8, there were 2 different structures for decoupling capacitor. - Generate decoupling capacitor in SD and F/A to BD. - Generate decoupling capacitor in BD from Utility. These differences had problem in using EMC Advisor and placement utilities. This is unified so that both EMC Advisor and placement utilities will work for both cases. Detail is explained in “Parent and Child relation”.

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Limitation Add Decoupling Capacitor Rev.8 could have created decoupling capacitor with GND or POWER net on both pins. From Rev.9, pair of GND and POWER net can be assigned to decoupling capacitor. In addition, parent component must have 3 or more pins. In Rev.8, it could have been 2 pins or more. Arrange In case there are more than 2 parent components exist in same Placement Group, result of “Arrange” command will vary. Open Design Data BD will automatically upgrade decoupling capacitor structure to Rev.9 if data structure from Rev.8 is found. When decoupling capacitor already existed in Rev.8, relation of parent and child component will be lost after upgrade to Rev.9 data structure. Database Version Down Version down process will not convert decoupling capacitor from Rev.9 to Rev.8. Divide Board Decoupling Capacitor will not be imported to parent board when expanding the child board. Load Nesting in Divide command will not display (B) mark for decoupling capacitor. pcout Once the data structure is updated to Rev.9, output mode in Rev.8 mode will not include decoupling capacitor.

Before Arrange

P. Comp1

P. Comp2

Dec. Cap.1

Dec. Cap.2

Placement Group: GroupA

P. Comp1

P. Comp2

Dec. Cap.1

Dec. Cap.2


P. Comp1

P. Comp2

Dec. Cap.1

Dec. Cap.2


P. Comp1

P. Comp2

Dec. Cap.1

Dec. Cap.2


Result 1

Resutl3Result 2

Components in are example of related parent components and decoupling capacitors.

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ZFC No replacement function can be provided to refer decoupling capacitor from PCB. It is required to use new function and refer to decoupling capacitor in RUL file.

Place Decoupling Capacitor

Summary A function to place decoupling capacitor is added to Move Component command. This function is to place related decoupling capacitor next to power pin of selected component.

Detail Difference between “Arrange” command is that this command will place all related command next to power pin even when DRC error will occur. This is based on idea that decoupling capacitor will be adjusted to proper location after they are placed close to parent component. Target of this command is related decoupling capacitors not being placed in the Layout area.

Limitation - Placed components will be in parallel. (0 degree). - Placement of decoupling capacitor will only refer 1 parent component. - Placement will refer to Grid ON/OFF. - Components need to adjust placement after the command is executed as

command will disregard DRC error. - Components with location, angle, or place side lock will fail and report

error in the message field.

New

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Query Data command for Placement Group

Summary The name of query command option changed from “Decoupling Capacitor” to “Comp. in Placement Group”. In addition, new option is added for Search Target “Component”.

Detail PCB Data mode will report followings. - Decouling Capacitor, ESD Components, Oscillator Circuit Components - All decoupling child components related to parent component. - All ESC child components related to parent component. - Oscillator circuit components in group of Placement Group. - Components not belonging to above group. Object Info Component option will report following relations of component. - Decoupling Capacitor - ESD component - Oscillator Circuit

Limitation Panel Tool doesn’t report (Decoupling Capacitor) for components.

8-10 Synchronized Selection from Design

Rule Editor

Send selection from Net Objects dialog to Canvas

Summary Chances of referring to net object rules will increase as constraint design becomes key for high speed design. Reference from net objects to canvas will be available in Rev.9. In the Net Objects dialog, select and send object name from assist menu.

PCB Data Comp. in Placement Group

Object Info Component Comp. in Placement Group

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Detail The function will support following sending object selection. Send Net name Single net selection can be passed to command that controls net object. Multiple nets selection can be recognized by following commands. - Low Light - Query Command (Net and Enet) Send Pin name - Query command (Pin) Send Pinpair name - Query command (Pin) There are 2 additional options for sending selection from Net Objects dialog. *Query command for pin supports automatic zoom function. *Query command supports option to keep the canvas zoom ratio.

Reference Net Objects from Query Command

Summary Query command will have option to send selection to Net Objects dialog.

Detail Following objects will have option in the panel menu to send object name to Net Objects dialog. - Pin - Net - Subnet - Figure/Object - Enet

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Multiple Nets Selection from SD or Net Color Display

Summary Multiple nets selection can be cross probe from SD to BD. In a same idea, multiple nets can be also sent from Net Color Display dialog to receiving commands. Receiving commands are followings. - Low Light - Query Command (Net and Enet) In Rev.8, all commands can only receive 1 net at a time. Therefore, Net Color Display can only send 1 net at a time.

Opening Net Objects dialog directly from menu bar

Summary Access to the Net Objects dialog will be faster by selecting “Net Objects” in the menu, Module Net Object. In addition, dialog can hide behind the canvas and change size in order to increase the work space on the screen.

Limitation To open the Edit Design Rules (Board Design Rule Editor), the Net Objects dialog need to be closed. Following message will appear to confirm.

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8-11 Active 45 routing command

45 degree semi-auto routing

Summary The Active 45 routing command that Hot-Stage originally has is imported into Board Designer. The feature is as follows.

• Mouse trace routing Routing 45 degree pattern without clicking and according to the mouse trajectory

• Real time pushing Push aside other routes without making unnecessary space

The command brings about the reduction in design time.

Operation 1. Select [Edit] [Input Wire(Active45)] from the menu bar.

The next panel menu is displayed.

Enhance

A. Pair Layer … Generate Via by double-click and switch to the pair layer A

B

C

B. FromTo … Switch active layer

C. Width ….…Specify a Wiring width. When the [Fix Width] is "ON", it is wired by the specified width even if the wiring width is different from the design ruleD

D. Loop … [ON ] Loop pattern is possible Spread [None] Spread is not done [No Jog] Spread is done and doesn't make bend [Jog] Spread is done and makes bend Via … [ON] Spread via

E. Highlight SelectNet …. When the wire start or end, the selected Net , Terminal, and Via are highlight

[Change Padstack] … Change padstack for the via

E

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2. Specify each parameter from the panel menu. 3. Select the start point and move mouse.

Automatically, a pattern is entered according to the mouse trajectory.

4. Select [Data End] or [Command End] from the assist menu.

Note 1: The Spread mode requires Online-DRC is ON. Note 2: The “Via” can be specified when the Spread is “Jog”. Note 3: When the Snap Grid is “ON” and the Spread mode is “ON”, the clearance may be wide gap than the clearance in the rule. Note 4: When the Spread mode is “Jog” and the grid pitch is wide, the pattern may

not be 45 degree. Note 5: When the Spread mode is “Jog” and the pen type is square, the pen type

may change to circular shape Note 6: RulesByArea and Via grid are not supported. Note 7: The Spread is not effective while a temporary net is wired

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8-12 Copper Ratio Distribution

Add up Conductor Thickness

Summary To help see the distribution of copper over the board and all the layers, Cooper Ratio Distribution have mode to add up board thickness. It also calculates deviation of board thickness.

Detail Set board thickness In order for utilizing the new mode, it is necessary to set conductor thickness in Board Design Rule --> Board Spec and define Layer thickness. The tool will only add up thickness of conductors. Start the utility GUI and set following items. Grid X, Y Divide minimal rectangular area that includes Layout area with selected number. Tool will calculate copper area distribution based on lattice created by these grids. Add up Conductor Thickness Mode Select “Add up conductor thickness” mode from GUI. Under Target Layer, select layer number to accumulate thickness of conductor from layers. Specify Conductor Recognition Rate which determines whether if each lattice are to be considered as filled copper area or not. Result can be out put to CSV file to see which lattice has been recognized as conductor. Result and Calculation Result of Copper Distribution is displayed with color mapping in the GUI and in text format.

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There are settings for Color, Scaling, Via display, and Component area display. Following is a formula to calculate average thickness and standard deviation. Total Number of grids n= Grid X x Grid Y Each grid value to c[i] (I is 1 –n), values are - Average Value A = ( c[i]) / n - Distribution V = ( c[i] – A)^2) / n - Standard deviation = ( V )

8-13 Edit Interstitial Via

Edit Padstack From - To

Summary Function to edit “From – To” is enhanced and it has option to change only either “From” or “To” for multiple padstacks. When changing the layer, you can select “Fix” not to change From or To. If part of target padstack is violating drill rule (via rule), then edit command will report in the canvas that From-To is violating the rule. When all target padstacks are violating the rule, then command will report error in message line. Error message

Enhance

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8-14 Divide Board

Cut Height Limitation Area by Divide Area

Summary Divide area did not cut height limitation area in Rev.8. To move height limitation area to divide board, it was necessary to include entire height limitation area in divide area. This is changed so that divide area will cut height limitation area when Cut Mode for Area is ON.

Input New Divide Area

Summary To set place new divide area next to existing one, you can use Shift key to select the outline of existing divide area and create new divide area next to it. In Rev.8, new divide area can’t be placed when you select outline of existing divide area as it becomes mode to edit existing area.

Parent Board Child Board

Height Limitation Area

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Click

+ Shift

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171


Check Area Attributes when Expanding Divided Area

Summary Area objects can be merged when expanding divided area with Merge Area option ON. When merging, tool will check area attributes to determine if objects can be merged or not.

Detail Following objects and attributes are checked. When there is difference between checked areas, Expand command will keep areas separated. Height Limitation Area - Figure Height Rules By Area - Design Rule Stack - Wiring Width Stack - Default Padstack - Effective Layer - Qualified Padstack Template Area - Comments - Cut Out Parameters

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8-15 Cross Glass

Generate Cross Glass command

Summary Functionality of Generate Cross Glass has 2 modes. - Generate Offset

This mode will make offset figure covering the selected object figure. - Generate Crossing

This mode will make figure over cross point.

Detail

Condition of using the function - Target layer “Dielectric-N” which is between conductive layers “N” and “N+1”

needs to exist in the design. - Visible Layer setting need to be turned ON for conductive layers “N” and “N+1”. - Dielectric layer need to exist between 2 target layers Target Object - All figure types on conductive layer except for negative figures. Note : Function will search for all layers even when search mode is single. Note : Command will generate cross glass even when the target layer has visible

setting turned OFF.

Generate Cross Glass by area selection

Summary In Rev.8, cross glass was generated for location selected by the cursor. From Rev.9 area selection is supported so that it will reduce operation to place cross glass individually.

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Effective Mode - Generate Offset - Generate Crossing

Target all objects on conductive layer

Summary All objects on conductive layer will be a target to generate cross glass. This will reduce chance of having short between figures on conductive layers. Previous function had Effective Mode - Generate Offset - Generate Crossing Target Object All figure on conductive layers except for negative figures. - Line - Shield Line - Area - Shield Area - Mesh Plane - Text - Pad - Pad in Padstack

Do not generate over covered Cross Glass

Summary When generating cross glass is completely covered (overlapped) by existing cross glass, then command will not input cross glass for that area. Need larger cross glass --> Generate Already covered by larger cross glass --> Skip process Effective Mode - Generate Offset - Generate Crossing

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Cross Glass covering offset figure

Summary Generate offset figure will refer to actual overlapping figures and add offset to it. When “Generate Min. Rectangle” is ON, then command will calculate minimum rectangular cross glass to include offset figure. Effective Mode - Generate Crossing

Control Cross Glass generation for same net

Summary In a hybrid design, there is no insulator between conductive layers and to control connection. Option for to generate cross glass will give designer a control of same net connection. Effective Mode - Generate Crossing

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Exclude generation between specified layers

Summary An option to exclude from generating cross glass is added in panel menu. This option is effective for example, in case when insulator exists between 3rd and 4th layer. Effective Mode - Generate Offset - Generate Crossing

8-16 Abolition of “bdplist”

Abolition of “bdplist”

Summary The “blistp” (Board List Processor) was released by Rev7. And the abolition of “bdplist” was announced by the Rev8 revision up caution. From Rev9, please use the “blistp” (Board List Processor” instead of the “bdplist”.

8-17 Control Layer Setting Columns

Control Layer Setting Columns in Resource File

Summary There were several requests on defining default columns to display in Layer Setting dialog. In Rev.8, columns condition was cancelled after exiting Board Designer. From Rev.9, board.rsc file will have default setting to control display condition of Layer Setting columns.

Enhance

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176


Detail Display columns and their order in Layer Setting dialog can be controlled individually. board.rsc file Following is a sample setting in board.rsc file and corresponding column names. Order of listing in resource file controls column order from left to right. Layer Name Change Following Layer Names are changed in Rev.9 to differentiate from Data Layers. - [Doc.]Hatch Pitch - [Doc.]Angle Pitch - [Doc.]Object Settings

8-18 Standard ASCII I/O (Rev8 Rev9)

Addition of an item

Summary At “FTF”, “PCF” and “PNF”, the item for “dimension line without arrow” is added

The item name is “hideLine”.

layerSettingsColumns 2 { layerType off visible on color on dispMode on hatchPitch on hatchAngle on object off docVisible off docColor off docDispMode off docHatchPitch off docHatchAngle off docObject off priority off }

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Chapter 9 CAM Board List Processor

9-1 Check Aperture Violation – Integration of the way of operation 9-2 Improvement of Simulation Results Window operation 9-3 Improvement of RS274X analysis 9-4 Improvement of Manufacturing Rule Edit 9-5 Improvement of board List Processor 9-6 Enhancement of Photo/Drill plot by Plot Tool


9- 1 Check Aperture Violation –Integration of the way of operation

Integration of the GUI

Summary The Check Aperture Violation dialog becomes same as other dialog. Therefore the setting operation is integrated.

< Rev8 > < Rev9 >

Keeping the layer name order

Summary When the order of layer name list on the Check Aperture Violation is updated by “Change Order of Layer Name”, the Check Aperture Violation dialog displays the layer name according to the order.

Enhance

<Check Aperture Violation dialog > < Change Order of Layer Name >

Same Order

Enhance

180


Displaying the Layer comment as the layer name

Summary When you specify the “Show Comment as Layer Name” to “Layer Name” by [Environment] [Option], the Layer name in the violation figures list dialog also shows the Layer comment.

9- 2 Improvement of Simulation Results Window operation

Support for wheel mouse operation

Summary At the Simulation Results Window for “Check Aperture Violation” and “Check Hole Tool-code Violation”, the window operation (e.g. Zoom-Inetc) can be done by the wheel mouse operation. Wheel Operation None With “shift” key With “ctrl” key Rotating toward Up

Panning toward Up

Panning toward Right

Zoom-In

Rotating toward Down

Panning toward Down

Panning toward Left

Zoom-Out

Enhance

Enhance

181


9- 3 Improvement of RS274X analysis

Support for RS274X that includes the operator in AM parameter

Summary You can import RS274X format even if it is including the operator (+,-,x,/,=) in the AM parameter that is the definition section of Aperture. For example, at the next the result of $1x$2 substitutes to $5.

9- 4 Improvement of Manufacturing Rule Edit

Support for open with Read-only mode

Summary Some customers wish only the library manager can edit their library. The library manager does not want to edit them by designers. Therefore Rev9 supports what open the Manufacturing Rule library with Read-only mode. When the library does not have a write permission for the user, it is opened with Read-only mode.

Enhance

$5=$1x$2

Enhance

Grayed out

Firstly, this message dialog is indicated

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Board Designer Rev9 New Feature

9- 5 Improvement of Board List Processor

Consistency with bdplist

Summary Adding some functions and updating some specs the "bdplist" has to Board List Processor. Customer can move to Board List Processor from “bdplist” easily by this improvement. Supporting items are as follows.

• Expansion of output items of Component Group • Outputting Machine information is available (support for UNIX only) • Updating the process of output for empty value • Cancellation of the limit of text count in a line • Control the output list by Approval/Unapproval attribute

Expansion of output items of Component Group

Summary You can output “Component Group center coordination” and “Component

group property”.

Enhance

<Component group center coordinates> <Component group property>

Enhance

183


Outputting Machine information is available (support for UNIX only)

Summary At “bdplist” for UNIX, the next system texts supports to output next information. It is similar function as“uname” of UNIX command. From Rev9, the “bdplist” is abolished. But you can use the“.edf” file that is a parameter file for “bdplist”. At Rev8.030, their system texts didn't work even if the “edf” had the next system texts on Board List Processor. When the “.edf” file has the next system texts, Board List Processor output appropriate information according to them.

System Texts Output contents Sample $sysOS OS Name uname –s “HP-UX” $sysRelease OS Relese level uname –r “A.09.01” $sysVersion OS Version uname –v “C” $sysNode Node Name uname –n “host1” $sysModel Model Name uname –m “9000/750”

Updating the process of output for empty value

Summary When the output object doesn't have the value(the value is empty),there was the different result between Board List Processor and “bdplist”. At Board List Processor, it changes the handling same as “bdplist”. The output result changes from Rev8 to Rev9.

Property Value Before Rev9 Rev9 and later 1 Undefined --------- Default String Default String 2 Defined Undefined Empty String Default String 3 Defined Defined Defined value Defined value

Enhance

Enhance

184


Cancellation of the limit of text count in a line

Summary “bdplist” doesn’t have the limitation to output text count in a line. But Board List Processor was 256 texts in a line. Therefore the text was cut from 256th text at Board List Processor In Rev9, the limitation is canceled and the process becomes congruent with “bdplist”.

Control the output list by Approval/Unapproval attribute

Summary You can control outputting of part information by Approval/Unapproval.

Part objects has “Approved flag”

Add

... dataA dataB AAA BBB CCC

Until Rev8 Rev.9.0

... dataA dataB A ... dataA dataB AAA BBB CCC

The text was cut from 256th text All texts can be output

Enhance

185


Addition of “bdplist” compatible mode

Summary There was a different coordinates calculation process between Board List

Processor and “bdplist” as follows. Board List Processor considers view of each side. Therefore it can calculate A side and B side separately. But the mirror process is added to the coordinates calculation process purely at "bdplist".

Board List Processor … Rotation Scaling Offset Mirror “bdplist” ………………... Mirror Rotation Scaling Offset

You need to set a special environment variable value when you specify the “bdplist” mode. Normal GUI doesn’t have the menu. The environment variable value is as follows.

Supporting an optional angle for rotation

Summary Until Rev8, you specify a rotation angle with 90 degree unit. From Rev9, you can specify a rotation angle with any value.

Add

ZBLP_BDPLIST_MODE = ON

Enhance

< Rev8 > < Rev9 >

Free Angle

186


9- 6 Enhancement of Photo/Drill plot by Plot Tool

Available to update the PCB/PNL file name after reading photo/drill parameter

Summary At the Plot Tool, when you plot photo data or drill data, you can plot overlaying with PCB/PNL data. At that time, photo or drill parameter file you specify is read. In Rev8, they can be loaded including PCB/PNL file name that is described in the parameter file. And we can not update the PCB/PNL file name. It is just for reference. But at Rev9, we can update the PCB/PNL name on the dialog.

< Rev8 > < Rev9 > <When specifying by batch> For example: Specifying BD-sample.pcb by photo check program

For example: Specifying AAA.pcb by drill check program

Add

zphck.exe sample.phd –p:zphoto sample.php:width:2/2:BD-sample.pcb

zdrck.exe sample.drd –p:zphoto sample.php:width:2/2:AAA.pcb

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