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Compact Model based Efficient Methodology for Successful Technology Transfer
Compact ModelsCompact Models
Analysis and DiscussionAnalysis and Discussion
MotivationMotivationMethodology for Efficient Technology Methodology for Efficient Technology
TransferTransfer
ResultsResults
ResultsResults
A. N. Chatterjee1, V. N. Vanukuru1, and S. Parthasarathy1
1SRDC, IBM, Bangalore, IndiaE-mail: [email protected]
ConclusionsConclusions
1) J.K.C. Chen, M. Moslehpour, A.C.P. Lin, and B. Bayaraa, 2011 Proceedings of PICMET ’11,
2011
2) J.K.C. Chen, Chen Yu-Shan, and M. Hung, 6th International Conference on Service Systems
and Service Management, 2009en, Linear Networks and Systems (Book style). Belmont, CA:
Wadsworth, 1993, pp. 123–135.
Technological advancement in IC manufacturing continues to
increase in demand every year. Due to continued and rapid growing
market for IC industry, extension of semiconductor manufacturing
sites wafer fabrication (fab) is necessary. Large-scale firms have to
transfer the manufacturing technology from one fab to another or to
new sub-fabs. Fabrication technology transfer to alternate fabs is
required for several reasons [1] (e.g. lower operation cost,
increased peak demand, contingency plan for natural calamity, etc.).
One of key issues for the firms is to make sure the most efficient
and practical way for technology transfer [2]. The objective of this
research is to propose a systematical analysis methodology for
technology transfer in the IC-industry. This work is based on a case
study of recent technology transfer in RF IC fab.
( )( )mLWCC AVNCAP µ8.2−××=
{ }{ }
11
11
Im YQ
Re Y= −
1 1
221
L Imf Yπ
=
THE FABRICATION PROCESS
AFTER TECHNOLOGY TRANSFER HAS BEEN ABLE TO
ACHIEVE THE TARGET CA
VALUES. COLOR CODE: YELLOW (BML:
M1, TML: MT) BLUE (BML: M1,
TML: M1) GREEN (BML: M1, TML: M2) RED (BML: M2, TML: M2)
Comparison of measured CA
with CA predicted by the model for all the wafers.
THE INTER-SITE VARIATION OF CA IS WITHIN PROCESS
TOLERANCE.
COLOR CODE: YELLOW (BML: M1, TML: MT) BLUE (BML: M1,
TML: M1) GREEN (BML: M1, TML:
M2) RED (BML: M2, TML: M2)
Model Vs. Hardware correlation of inductor for
successful technology transfer
Model Vs. Hardware correlation
of inductor showing issues in
technology transfer
Compact model of an On chip inductor
We observe that the capacitance densities are very close to target. The standard
deviation of inter site data are well within the process tolerance. TCC (temperature
coefficient of capacitance) for V N capacitors are matching with reasonable degree of
accuracy. Thus, V N capacitor characterization for technology transfer does not show
any major fabrication issues.
Root cause analysis (using SEM) performed for variances in inductor fabrication
revealed an issue with the etch depth of the via connecting the two metals of the spiral.
Due to the randomness in the etching of via, contact between both the metals was not
proper on several sites/wafers.
•Used a case study of recent technology transfer in RF IC fab to demonstrate a compact model based efficient methodology
•High fidelity compact models for V N capacitors and inductors are used for hardware qualification.
•Very good hardware-model correlation for VNCAPs.
• Inductors show very poor hardware-model correlation and had to be diagnosed for process related defects.
•By applying a top down approach to process qualification, we were able to zero in on a specific process related defect during technology transfer to an alternate foundry.
CA is capacitance density (fF/ µm2), W is design width in µm, and L is design
length in µm. 2.8 µm is length used up by the contacts.
V N Capacitors
Inductors
V N capacitors are tested from 3 lots and 9 wafers.
Hardware data is collected from 24 devices, and each
device is tested on 10 sites. The VNCAP devices are
fabricated with the following metal layers: M1, M2, and
MT. A combination of these metal layers act as bottom
metal layer (BML) and top metal layer (TML).
Inductance and Q factor obtained from the S-
Parameter data sets are used as metrics for
comparison.
3) M. Erturk, et al., “Methodology and Design Kit Integration of a Broadband Compact Inductor Model,” in 2007 Workshop on Compact Modeling Santa Clara, California, U.S.A May 20-24, 2007
3
•Develop high-fidelity compact model
•Compute the process tolerance for all the devices
•Do multi-lot and multi-wafer testing of the devices
•Refer to the flow chart for details