arm overview

The ARM Architecture

T

H

E

A

R

C

H

I

T

E

C

T

U

R

E

F

O

R

T TM

H

E

D

I

G

I

T

A

L

W

O

R1 L

D

Day 9 Agenda

Introduction to ARM Ltd The ARM Architecture Programmers Model Instruction Set

39v10 The ARM Architecture

TM

2

2

ARM Ltd

Founded in November 1990

Spun out of Acorn Computers

Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor partners who fabricate and sell to their customers.

ARM does not fabricate silicon itself

Also develop technologies to assist with the design-in of the ARM architecture

Software tools, boards, debug hardware, application software, bus architectures, peripherals etc


TM

3

3

Intellectual Property

ARM provides hard and soft views to licensees

RTL and synthesis flows GDSII layout (Geometric database standard information interchange) soft views include gate level netlists

Licencees have the right to use hard or soft views of the IP


TM

4

4

ARM Partnership Model


TM

5

5

ARM Powered Products


TM

6

6

Agenda

Introduction

The ARM Architecture Overview Programmers Model Instruction Set


TM

7

7

ARM Nomenclature

ARM { x } { y } { z } { T } { D } { M } { I } { E } { J } { F } { -S }

x Family Y Memory Management/Protection Unit Z Cache T THUMB 16 - Bit Decoder D JTAG Debug M Fast Multiplier I Embedded ICE Macrocell E Enhanced Instruction (Assumes TDMI) J Jazelle F Vector Floating Point Unit S Synthesizable Version


TM

8

8

The ARM Architecture Evolution

Architecture Versions 1 and 2 -- Acorn RISC, 26-bit address Version 3 32-bit address, CPSR, and SPSR Version 4 half-word, Thumb Version 5 Processor cores ARM7TDMI (Thumb, debug, multiplier, ICE) version 4T, low end ARM core, 3-stage pipeline ARM9TDMI 5-stage pipeline ARM10TDMI version 5 CPU Core: co-processor, MMU, AMBA ARM 710, 720, 740 ARM 920, 940TM


9

9

The Core


TM

10

10

Simple Implementation of Data Path

Include the functional units we need for each instructionPC Instruction Add SumMemWrite

Instruction address

Instruction memoryAddress

a. Instruction memory5 Register numbers 5 5 Read register 1 Read register 2 Registers Write register Write data

b. Program counter3 Read data 1 Data Read data 2

c. AdderALU controlWrite data

Read data Data memory

16

Sign extend

32

Zero ALU ALU result

MemRead a. Data memory unit b. Sign-extension unit

Data

RegWrite a. Registers b. ALUTM


11

11

Building the Datapath

Use multiplexors to stitch them togetherPCSrc Add 4 Shift left 2 Registers Read register 1 Read Read data 1 register 2 Write register Write data RegWrite 16 Read data 2 ALUSrc 3 ALU operation MemWrite MemtoReg Address Read data M u x Add ALU result M u x

PC

Read address Instruction Instruction memory

M u x

Zero ALU ALU result

Sign extend

32

Data memory Write data MemRead


TM

12

12

Implementing the Control

Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Example: add $8, $17, $18 Instruction Format:

000000 10001 10010 01000 00000 100000 op

rs

rt

rd

shamt funct

ALU's operation based on instruction type and function code


TM

13

13

Instruction Decoding

Selecting the operations to perform (ALU, read/write, etc.) Controlling the flow of data (multiplexor inputs) Information comes from the 32 bits of the instruction Example: add $8, $17, $18 Instruction Format:

000000 10001 10010 01000 00000 100000 op

rs

rt

rd

shamt funct

ALU's operation based on instruction type and function code


TM

14

14

Control

e.g., what should the ALU do with this instruction Example: lw $1, 100($2) 35 op 2 rs 1 rt 100 16 bit offset

ALU control input 000 001 010 110 111 AND OR add subtract set-on-less-than

Why is the code for subtract 110 and not 011?TM


15

15

Implementing the Control0 M u x Add Add 4 Instruction [31 26] RegDst Branch MemRead MemtoReg ALUOp MemWrite ALUSrc RegWrite Read register 1 Shift left 2 ALU result 1

Control

PC

Read address Instruction [31 0] Instruction memory

Instruction [25 21] Instruction [20 16] 0 M u x 1

Read data 1 Read register 2 Registers Read Write data 2 register Write data

Instruction [15 11]

0 M u x 1

Zero ALU ALU result

Address

Read data Data memory

Write data Instruction [15 0] 16 Sign extend 32 ALU control

1 M u x 0

Instruction [5 0]


TM

16

16

The Core


TM

17

17

ARM9TDMI Core Features

Based on Harvard Architecture 32 Bit ARM Instruction set 16 Bit Thumb Instruction set 37 General Purpose Registers Supports Hardware and Software Debug Bi and Uni-directional connection to external Memory Systems Supports Co-Processor It uses 5 stage pipelining

Fetch, Decode, Execute, Memory and WriteTM


18

18

Agenda

Introduction The ARM Architecture Overview

Programmers Model Instruction Set


TM

19

19

Data Sizes and Instruction Sets

The ARM is a 32-bit architecture.

When used in relation to the ARM:

Byte means 8 bits Halfword means 16 bits (two bytes) Word means 32 bits (four bytes)

Most ARMs implement two instruction sets

32-bit ARM Instruction Set 16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode


TM

20

20

Processor Modes

The ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run FIQ : entered when a high priority (fast) interrupt is raised IRQ : entered when a low priority (normal) interrupt is raised Supervisor : entered on reset and when a Software Interrupt instruction is executed Abort : used to handle memory access violations Undef : used to handle undefined instructions System : privileged mode using the same registers as user mode


TM

21

21

The ARM Register SetCurrent Visible RegistersAbort Undef Mode SVC Mode IRQ Mode FIQ Mode User Moder0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr

Banked out RegistersUserr8 r9 r10 r11 r12 r13 (sp) r14 (lr)

FIQr8 r9 r10 r11 r12 r13 (sp) r14 (lr)

IRQ

SVC

Undef

Abort

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

r13 (sp) r14 (lr)

spsr

spsr

spsr

spsr

spsr


TM

22

22

Register Organization SummaryUserr0 r1 r2 r3 r4 r5 r6 r7 r8 r9 r10 r11 r12 r13 (sp) r14 (lr) r15 (pc) cpsr spsr spsr spsr spsr spsr

FIQ

IRQ

SVC

Undef

Abort

User mode r0-r7, r15, and cpsr

r8 r9 r10 r11 r12 r13 (sp) r14 (lr)





Thumb state Low registers

Thumb state High registersr13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr) r13 (sp) r14 (lr)

Note: System mode uses the User mode register set39v10 The ARM ArchitectureTM

23

23

The Registers

ARM has 37 registers all of which are 32-bits long.

1 dedicated program counter 1 dedicated current program status register 5 dedicated saved program status registers 30 general purpose registers

The current processor mode governs which of several banks is accessible. Each mode can access

a particular set of r0-r12 registers a particular r13 (the stack pointer, sp) and r14 (the link register, lr) the program counter, r15 (pc) the current program status register, cpsr

Privileged modes (except System) can also access

a particular spsr (saved program status register)


TM

24

24

Program Counter (r15)

When the processor is executing in ARM state:

All instructions are 32 bits wide All instructions must be word aligned Therefore the pc value is stored in bits [31:2] with bits [1:0] undefined (as instruction cannot be halfword or byte aligned).

When the processor is executing in Thumb state:

All instructions are 16 bits wide All instructions must be halfword aligned Therefore the pc value is stored in bits [31:1] with bit [0] undefined (as instruction cannot be byte aligned).

When the processor is executing in Jazelle state:

All instructions are 8 bits wide Processor performs a word access to read 4 instructions at once25


TM

25

Registers in ARM State


TM

26

26

Registers in THUMB State


TM

27

27

THUMB to ARM State Mapping


TM

28

28

Current Program Status Registers31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q f

J

U

n s

d

e

f

i

n

e x

d

I F T c

mode

Condition code flags

Interrupt Disable bits.I = 1: Disables the IRQ. F = 1: Disables the FIQ.

N = Negative result from ALU Z = Zero result from ALU C = ALU operation Carried out V = ALU operation oVerflowed

T Bit

Sticky Overflow flag - Q flag

Architecture 5TE/J only Indicates if saturation has occurred

Architecture xT only T = 0: Processor in ARM state T = 1: Processor in Thumb state

Mode bits

J bit

Specify the processor mode

Architecture 5TEJ only J = 1: Processor in Jazelle state


TM

29

29

PSR Mode Bit Values


TM

30

30

Agenda

Introduction The ARM Architecture Overview Programmers Model

Instruction Set


TM

31

31

Data processing Instructions

Consist of :

Arithmetic: Logical: Comparisons: Data movement:

ADD AND CMP MOV

ADC ORR CMN MVN

SUB EOR TST

SBC BIC TEQ

RSB

RSC

These instructions only work on registers, NOT memory. Syntax:

{}{S} Rd, Rn, Operand2

Comparisons set flags only - they do not specify Rd Data movement does not specify Rn

Second operand is sent to the ALU via barrel shifter.


TM

32

32

Instruction Encoding

[15:12] Destination register [19:16] 1st operand register [16] 0: Branch 1: Branch and Link [20] Set condition codes 0 = Do not set condition codes 1 = Set condition codes [24:21] Operation codes 0000 = AND-Rd: = Op1 AND Op2 0001 = EOR-Rd: = Op1 EOR Op2 0010 = SUB-Rd: = Op1-Op2 0011 = RSB-Rd: = Op2-Op1 0100 = ADD-Rd: = Op1+Op2 0101 = ADC-Rd: = Op1+Op2+C 0110 = SBC-Rd: = OP1-Op2+C-1 0111 = RSC-Rd: = Op2-Op1+C-139v10 The ARM Architecture

Assemble as AND Rd, Ra, Rb EOR Rd, Ra, Rb SUB Rd, Ra, Rb RSB Rd, Ra, Rb ADD Rd, Ra, Rb ADC Rd, Ra, Rb SBC Rd, Ra, Rb RSC Rd, Ra, RbTM

33

33

Instruction Encoding

[24:21] Operation codes 1000 = TST-set condition codes on Op1 AND Op2 1001 = TEO-set condition codes on OP1 EOR Op2 1010 = CMP-set condition codes on Op1-Op2 1011 = SMN-set condition codes on Op1+Op2 1100 = ORR-Rd: = Op1 OR Op2 1101 = MOV-Rd: =Op2 1110 = BIC-Rd: = Op1 AND NOT Op2 1111 = MVN-Rd: = NOT Op2 [25] Immediate operand 0 = Operand 2 is a register 1 = Operand 2 is an immediate value [31:28] Condition field

Assemble as TST Ra,Rb TEO Ra,Rb CMP Ra,Rb SMN Ra,Rb ORR Ra,Rb MOV Ra,Rb BIC Ra,Rb MVN Ra,Rb


TM

34

34

Condition CodesSuffix Description Equal Not equal Unsigned higher or same Unsigned lower Minus Positive or Zero Overflow No overflow Unsigned higher Unsigned lower or same Greater or equal Less than Greater than Less than or equal Always Flags tested Z=1 Z=0 C=1 C=0 N=1 N=0 V=1 V=0 C=1 & Z=0 C=0 or Z=1 N=V N!=V Z=0 & N=V Z=1 or N=!V

EQ

The possible condition codes are listed: Note AL is the default and does not need to be specified

NE CS/HS CC/LO MI PL VS VC HI LS GE LT GT LE AL


TM

35

35

Conditional Execution

Use a sequence of several conditional instructionsif (a==0) func(1); CMP r0,#0 MOVEQ r0,#1 BLEQ func

Set the flags, then use various condition codesif (a==0) x=0; if (a>0) x=1; CMP r0,#0 MOVEQ r1,#0 MOVGT r1,#1

Use conditional compare instructionsif (a==4 || a==10) x=0; CMP r0,#4 CMPNE r0,#10 MOVEQ r1,#0


TM

36

36

Conditional Execution and Flags

ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field. This improves code density and performance by reducing the number of forward branch instructions. CMP r3,#0 CMP r3,#0 BEQ skip ADDNE r0,r1,r2 ADD r0,r1,r2 skip By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using S. CMP does not need S. loop decrement r1 and set flags SUBS r1,r1,#1 BNE loop if Z flag clear then branch


TM

37

37

Multiply

Syntax:

MUL{}{S} Rd, Rm, Rs MLA{}{S} Rd,Rm,Rs,Rn [U|S]MULL{}{S} RdLo, RdHi, Rm, Rs [U|S]MLAL{}{S} RdLo, RdHi, Rm, Rs

Rd = Rm * Rs Rd = (Rm * Rs) + Rn RdHi,RdLo := Rm*Rs RdHi,RdLo := (Rm*Rs)+RdHi,RdLo

Cycle time

Basic MUL instruction

2-5 cycles on ARM7TDMI 1-3 cycles on StrongARM/XScale 2 cycles on ARM9E/ARM102xE

+1 cycle for ARM9TDMI (over ARM7TDMI) +1 cycle for accumulate (not on 9E though result delay is one cycle longer) +1 cycle for long

Above are general rules - refer to the TRM for the core you are using for the exact detailsTM


38

38

Multiply Accumulate

[15:12][11:8][3:0] Operand Registers [19:16] Destination Register [20] Set Condition Code 0 = Do not after condition codes 1 = Set condition codes [21] Accumulate 0 = Multiply only 1 = Multiply and accumulate [31:28] Condition Field MUL: Rd=Rm * Rs MLA: Rd = Rm * Rs + RnTM


39

39

Branch instructions

Branch : Branch with Link :

B{} label BL{} subroutine_label

31

28 27

25 24 23

0

Cond

1 0 1 L

Offset

Link bit

0 = Branch 1 = Branch with link

Condition field

The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC

32 M byte range How to perform longer branches?TM


40

40

Branch and Exchange

Branch and Exchange: BX{} Register

Exchanges to and from ARM and THUMB state If bit0 of Rn = 1, subsequent instructions decoded as THUMB instructions If bit0 of Rn =0, subsequent instructions decoded as ARM instructions

[3:0] Operand Register

[31:28] Condition Field


TM

41

41

The Barrel ShifterLSL : Logical Left ShiftCF

ASR: Arithmetic Right ShiftDestinationCF

Destination

0

Multiplication by a power of 2

Division by a power of 2, preserving the sign bit

LSR : Logical Shift Right...0

ROR: Rotate RightDestinationCF

DestinationDivision by a power of 2

CF

Bit rotate with wrap around from LSB to MSB

RRX: Rotate Right ExtendedDestinationCF

Single bit rotate with wrap around from CF to MSB39v10 The ARM ArchitectureTM

42

42

Using the Barrel Shifter: The Second OperandOperand 1 Operand 2Barrel Shifter

Register, optionally with shift operation

Shift value can be either be:

5 bit unsigned integer Specified in bottom byte of another register.

Used for multiplication by constant

Immediate value

8 bit number, with a range of 0-255.

ALU

Rotated right through even number of positions

Allows increased range of 32-bit constants to be loaded directly into registers

Result39v10 The ARM ArchitectureTM

43

43

Immediate constants (1)

No ARM instruction can contain a 32 bit immediate constant

All ARM instructions are fixed as 32 bits long

The data processing instruction format has 12 bits available for operand211 rot x2 8 7 immed_8 0

Quick Quiz:

Shifter ROR

0xe3a004ff MOV r0, #???

4 bit rotate value (0-15) is multiplied by two to give range 0-30 in steps of 2 Rule to remember is 8-bits shifted by an even number of bit positions.


TM

44

44

Immediate constants (2)

Examples:31 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0

ror #0 ror #8 ror #30

range 0-0x000000ff step 0x00000001 range 0-0xff000000 step 0x01000000 range 0-0x000003fc step 0x00000004

The assembler converts immediate values to the rotate form: MOV r0,#4096 ; uses 0x40 ror 26 ADD r1,r2,#0xFF0000 ; uses 0xFF ror 16 The bitwise complements can also be formed using MVN: MOV r0, #0xFFFFFFFF ; assembles to MVN r0,#0 Values that cannot be generated in this way will cause an error.TM


45

45

Loading 32 bit constants

To allow larger constants to be loaded, the assembler offers a pseudoinstruction: LDR rd, =const This will either: Produce a MOV or MVN instruction to generate the value (if possible). or

Generate a LDR instruction with a PC-relative address to read the constant from a literal pool (Constant data area embedded in the code). => =>

For example LDR r0,=0xFF LDR r0,=0x55555555

MOV r0,#0xFF LDR r0,[PC,#Imm12] DCD 0x55555555

This is the recommended way of loading constants into a register


TM

46

46

Load/Store Operation with Memory

[15:12] Source/Destination Registers [19:16] Base Register [20] Load/Store Bit 0 = Store to memory 1 = Load from memory [21] Write-back Bit 0 = No write-back 1 = Write address into base [22] Byte/Word Bit 0 = Transfer word quantity 1 = Transfer byte quantity39v10 The ARM Architecture

[23] Up/Down Bit 0 = Down: subtract offset from base 1 = Up: add offset to base [24] Pre/Post Indexing Bit 0 = Post: add offset after transfer 1 = Pre: add offset before transfer [25] Immediate Offset 0 = Offset is an immediate value [11:0] Offset Immediate or Register with amount of Shift SpecifiedTM

47

47

Single register data transferLDR LDRB LDRH LDRSB LDRSH

STR STRB STRH

Word Byte Halfword Signed byte load Signed halfword load

Memory system must support all access sizes

Syntax:

LDR{}{} Rd, STR{}{} Rd,

e.g. LDREQB


TM

48

48

Address accessed

Address accessed by LDR/STR is specified by a base register plus an offset For word and unsigned byte accesses, offset can be

An unsigned 12-bit immediate value (ie 0 - 4095 bytes).LDR r0,[r1,#8]

A register, optionally shifted by an immediate valueLDR r0,[r1,r2] LDR r0,[r1,r2,LSL#2]

This can be either added or subtracted from the base register:LDR r0,[r1,#-8] LDR r0,[r1,-r2] LDR r0,[r1,-r2,LSL#2]

For halfword and signed halfword / byte, offset can be:

An unsigned 8 bit immediate value (ie 0-255 bytes). A register (unshifted).

Choice of pre-indexed or post-indexed addressing


TM

49

49

Pre or Post Indexed Addressing?

Pre-indexed: STR r0,[r1,#12]Offset 120x20c

r0 0x5 0x5

Source Register for STR

Base Register

r1 0x2000x200

Auto-update form: STR r0,[r1,#12]!

Post-indexed: STR r0,[r1],#12Updated Base Register Original Base Register r1 0x20c r1 0x2000x200

Offset 120x20c

r0 0x5 0x5

Source Register for STR


TM

50

50

LDM / STM operation

Syntax: {} Rb{!}, 4 addressing modes:LDMIA / STMIA LDMIB / STMIB LDMDA / STMDA LDMDB / STMDB increment after increment before decrement after decrement before

IA LDMxx r10, {r0,r1,r4} STMxx r10, {r0,r1,r4}Base Register (Rb) r10r4 r1 r0

IBr4 r1 r0

DA

DB

r4 r1 r0 r4 r1 r0

Increasing Address


TM

51

51

Addressing Modes

{cond} Rn{!},{^} where: {cond} Two character condition mnemonic Rn An expression evaluating to a valid register number A list of registers and register ranges enclosed in {} (e.g. {R0,R2-R7,R10}). {!} If present requests write-back (W=1), otherwise W=0. {^} If present set S bit to load the CPSR along with the PC, or force transfer of user bank when in privileged mode.39v10 The ARM ArchitectureTM

52

52

Software Interrupt (SWI)31 28 27 24 23 0

Cond

1 1 1 1

SWI number (ignored by processor)

Condition FieldCauses an exception trap to the SWI hardware vector The SWI handler can examine the SWI number to decide what operation has been requested. By using the SWI mechanism, an operating system can implement a set of privileged operations which applications running in user mode can request. Syntax: SWI{}


TM

53

53

PSR Transfer Instructions31 28 27 24 23 16 15 8 7 6 5 4 0

N Z C V Q f

J

U

n s

d

e

f

i

n

e x

d

I F T c

mode

MRS and MSR allow contents of CPSR / SPSR to be transferred to / from a general purpose register. Syntax:

MRS{} Rd, ; Rd = MSR{} ,Rm ; = Rm = CPSR or SPSR [_fields] = any combination of fsxc MSR{} ,#Immediate

where

Also an immediate form

In User Mode, all bits can be read but only the condition flags (_f) can be written.54


TM

54

ARM Branches and Subroutines

B

PC relative. 32 Mbyte range. Stores return address in LR Returning implemented by restoring the PC from LR For non-leaf functions, LR will have to be stacked

BL

func1: : BL func1 : : STMFD sp!,{regs,lr} : BL func2 : LDMFD sp!,{regs,pc}

func2: : : : : MOV pc, lr


TM

55

55

THUMB

Thumb is a 16-bit instruction set

Optimised for code density from C code (~65% of ARM code size) Improved performance from narrow memory Subset of the functionality of the ARM instruction set Switch between ARM and Thumb using BX instructionADDS r2,r2,#10

Core has additional execution state - Thumb31

32-bit ARM Instruction

For most instructions generated by compiler:

Conditional execution is not used Source and destination registers identical Only Low registers used Constants are of limited size Inline barrel shifter not used

15

ADD r2,#1

0

16-bit Thumb Instruction39v10 The ARM ArchitectureTM

56

56

THUMB Instruction Encodings

[2:0] Destination Register [5:3] Source Register [10:6] Immediate Value [12:11] Op code 0 = LSL, 1 = LSR, 2 = ASR


TM

57

57


[7:0] Immediate Vale [10:8] Source/Destination Register [12:11] Opcode 0 = MOV, 1 = CMP, 2 = ADD, 3 = SUB


TM

58

58



TM

59

59

PUSH & POP Equivalent to STM & LDM

[7:0] Register List [8] PC/LR Bit, 0 = Do not store LR/Load PC, 1 = Store LR/Load PC [11] Load/Store Bit, 0 = Store to memory, 1 = Load from memory39v10 The ARM ArchitectureTM

60

60

Next Session

Exceptions System Design Memory Interface Synchronization Input / Output


TM

61

61

arm overview

Documents

subsequent instructions decoded

set condition codes

data processing instructions

thumb instruction encodings

user mode r0

condition code flags

alu alu result

condition field