arm cortex-m0 designstart processor and v6-m architecture

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  • 1

    ARM Cortex-M0 DesignStartProcessor and v6-M

    Architecture

    Joe BungoUniversity Program Manager Americas and Europe

    R&D Division

  • 2

    Agenda

    Introduction to ARM LtdCortex-M0 DesignStart Processor

    ARM v6-M Programmers Model

    ARM v6-M Exception Handling

    ARM v6-M Instruction Set Overview

    Pipeline

    Basic System Design

    Cortex-M0 DesignStart Design Kit

  • 3

    ARM Ltd

    Founded in November 1990 Spun out of Acorn Computers Initial funding from Apple, Acorn and VLSI

    Designs the ARM range of RISC processor cores Licenses ARM core designs to semiconductor

    partners who fabricate and sell to theircustomers

    ARM does not fabricate silicon itself

    Also develop technologies to assist with the design-in of the ARM architecture

    Software tools, boards, debug hardware Application software Bus architectures Peripherals, etc

  • 4

    ARM Connected Community 700+

    4

  • 5

    Huge Range of Applications

    Energy Efficient Appliances

    IR FireDetector

    IntelligentVending

    Tele-parking

    UtilityMeters

    ExerciseMachinesIntelligent toys

    Equipment Adopting 32-bit ARMMicrocontrollers

  • 6

    Ultra Low CostMobile phones

    ~100%market share

    How many ARMs Do You Have?

    Ultra Low CostMobile Computers

    5x 100%market share

    Smartphones

    3x 100%market share

    Ultra Low CostDigital TVs

    30%market share

    Ultra Low CostDisk Drives

    ~70%market share

    Ultra Low CostPC Peripherals

    30%market share

    Ultra Low CostMicrocontrollers

    15%market share

    Ultra Low CostCars

    5x 40%market share

  • 7

    Huge Opportunity For ARM Technology

    1998 2010 2020

    billion20+billion20+20+

    cores to date

    100+billion100+100+billion cores accumulated

    after next 10 yrs

  • 8

    Worlds Smallest ARM Computer?

    A CB

    Wirelessly networked into large scalesensor arrays

    University of Michigan

    Sensors, timers

    Cortex-M0 +16KB RAM 65nmUWB Radio antenna

    10 kB Storage memory~3fW/bit

    12Ah Li-ion Battery

    Wireless Sensor Network

    Cortex-M0; 65

  • 9

    Worlds Largest ARM Computer?

    4200 ARM poweredNeutrino Detectors

    Work supported by the National Science Foundation and University of Wisconsin-Madison

    70 bore holes 2.5km deep

    60 detectors per stringstarting 1.5km down

    1km3 of active telescope

  • 10

    From 1mm3 to 1km3

    1mm3 1km3

    10 $1000

    Mobile

    Embedded Consumer

    Mobile Computing Server

    Enterprise PC

    Home

    HPC

  • 11

    ARM Cortex Processors (v7)

    ARM Cortex-A family (v7-A): Applications processors for full OS

    and 3rd party applications

    ARM Cortex-R family (v7-R): Embedded processors for real-time

    signal processing, control applications

    ARM Cortex-M family (v7-M): Microcontroller-oriented processors

    for MCU and SoC applications

    Cortex-R4

    Cortex-A8

    SC300

    Cortex-M1

    Cortex-M3

    ...2.5GHzx1-4

    Cortex-A9

    12k gates...

    Cortex-M0

    Cortex-M4

    x1-4

    Cortex-A51-2

    HeronR

    x1-4

    Cortex-A15

  • 12

    Relative Performance*

    *Represents attainable speeds in 130, 90, 65, or 45nm processes

    Cortex-M0

    Cortex-M3

    ARM7 ARM926 ARM1026 ARM1136 ARM1176 Cortex-A8Cortex-A9Dual-core

    Max Freq (MHz) 50 150 184 470 540 610 750 1100 2000

    Min Power (mW/MHz) 0.012 0.06 0.35 0.235 0.36 0.335 0.568 0.43 0.5

    0

    500

    1000

    1500

    2000

    2500M

    ax

    Fre

    qu

    en

    cy

    (Mh

    z)

  • 13

    Agenda

    Introduction to ARM Ltd

    Cortex-M0 DesignStart ProcessorARM v6-M Programmers Model

    ARM v6-M Exception Handling

    ARM v6-M Instruction Set Overview

    Pipeline

    Basic System Design

    Cortex-M0 DesignStart Design Kit

  • 14

    Cortex family

    Cortex-A8

    Architecture v7A

    MMU

    AXI

    VFP & NEON support

    Cortex-R4

    Architecture v7R

    MPU (optional)

    AXI

    Dual Issue

    Cortex-M3

    Architecture v7M

    MPU (optional)

    AHB Lite & APB

  • 15

    Cortex-M0 DesignStart Processor

  • 16

    ARM Cortex-M0 processor

    features

    Full productoptions

    M0_DSimplementation

    Verilog core Flattened and Obfuscated

    AMBA AHB-lite interface

    ARMv6-M instruction set architecture

    NVIC Interrupt controller

    Interrupt line configurations 1 to 32 16 only

    Debug (SWD, JTAG) option

    Up to 4 breakpoints, 2 watchpoints

    Low power optimisations (ACG)

    Multiple power domain support with WIC

    Fast multiplier (1 cycle) option

    System timer

    Area (gates) 12k 25k 16K

    Cortex-M0 DesignStart Limitations

  • 17

    Agenda

    Introduction to ARM Ltd

    Cortex-M0 DesignStart Processor

    ARM v6-M Programmers ModelARM v6-M Exception Handling

    ARM v6-M Instruction Set Overview

    Pipeline

    Basic System Design

    Cortex-M0 DesignStart Design Kit

  • 18

    v6-M Data Types

    ARM v6-M is a 32-bit architecture.

    When used in relation to the ARM: Byte means 8 bits

    Halfword means 16 bits (two bytes)

    Word means 32 bits (four bytes)

    Doubleword means 64 bits (eight bytes)

  • 19

    Cortex-M0 Programmers Model

    The Cortex-M0 is designed to be programmed fully in C No need to write assembly code

    Full Thumb technology, and subset of Thumb2 16-bit and 32-bit instructions

    Set of processor core and memory-mapped registers are provided

    Forwards compatible with other M-profile processors

    In-order execution of instructions

    All instructions are treated as restartable Including LDM/STM

  • 20

    Cortex-M Differences

    Fully programmable in C

    Stack-based exception model

    Only two processor modes Thread Mode for User tasks

    Handler Mode for OS tasks and exceptions

    Vector table contains addresses

  • 21

    Cortex-M0 Memory Map

    Device 511MB

    Private Peripheral Bus1MBExternal Device 1GB

    External RAM 1GB

    Peripheral 500MB

    SRAM 500MB

    Code 500MB

    0x0000 0000

    0x2000 0000

    0x4000 0000

    0x6000 0000

    0xA000 0000

    0xE000 0000

    0xE010 0000

    Executable region for program code and data(vector table is fixed at address 0x0000 0000)

    Data Memory (code can also be placed here)

    External Peripherals (XN)

    External Memory

    External Peripherals (XN)

    Core Memory Mapped Register Space,i.e. NVIC (XN)

    XN execute never

  • 22

    Cortex-M0 Register Set

    All registers are 32 bits wide

    13 general purpose registers Registers r0 r7 (Low registers)

    Registers r8 r12 (High registers)

    3 registers with special meaning/usage Stack Pointer (SP) r13

    Link Register (LR) r14

    Program Counter (PC) r15

    Special-purpose registers

    xPSR shows a composite of the content of APSR, IPSR, EPSR

    Process

    r8

    r9

    r10

    r11

    r12

    sp

    lr

    r15 (pc)

    xPSR

    r0

    r1

    r2

    r3

    r4

    r5

    r6

    r7

    Main

    sp

  • 23

    APSR - Application Program Status Register

    Contains the Negative, Zero, Carry and OVerflow flags from the ALU

    IPSR Interrupt Program Status Register

    EPSR Execution Program Status Register

    Thumb code is executed

    012345678910111213141516171819202122232425262728293031

    The PSR Registers

    012345678910111213141516171819202122232425262728293031

    012345678910111213141516171819202122232425262728293031

    N Z C V

    ExceptionNumber

    T

  • 24

    xPSR Composite register of APSR, IPSR and EPSR

    IEPSR Composite register of IPSR and EPSR

    012345678910111213141516171819202122232425262728293031

    The PSR Composite Registers

    N Z C VExceptionNumber

    T

    012345678910111213141516171819202122232425262728293031

    ExceptionNumber

    T

  • 25

    Processor Mode Usage

    Processor mode may change when exceptions occur Thread Mode is entered on Reset

    Handler Mode is entered on all other exceptions

    Both modes have full access to all system resources No concept of privilege. Mechanism exists but has no meaning to M0

    ARM Cortex-M0 Processor

    ThreadMode

    Application Code

    HandlerMode

    Exception Code

    SVCPendSVFaults

    SysTick

    ExceptionReturn

    Reset

    InterruptsFaults

  • 26

    Agenda

    Introduction to ARM Ltd

    Cortex-M0 DesignStart Processor

    ARM v6-M Programmers Model

    ARM v6-M Exception HandlingARM v6-M Instruction Set Overview

    Pipeline

    Basic System Design

    Cortex-M0 DesignStart Design Kit

  • 27

    Supported Exceptions

    Reset Processor reset input is asserted

    HardFault Any type of fault occurred

    e.g. Bus fault or undefined instruction

    NMI Non-Maskable Interrupt occurred

    IRQs IRQ Interrupts occurred

    PendSV Software generated interrupt

    SVCall Execution of a SVC instruction

    SysTick Internal system timer caused interrupt

    Using Handler Mode

    Using Thread Mode

    Seven exception types are supported

  • 28

    Exception Properties

    Each exception has associated properties

    Exception number Identification for the exception

    Vector address Exception entry point i

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