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ARM Cortex-M0. CORTEX-M0 Structure Discussion 3. August 23, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. www.orchid-tech.com. Cortex-M0 Structure Discussion 3. Topics Today CORTEX-M0 Power Management CORTEX-M0 Fault Handling CORTEX-M0 Stack Structures - PowerPoint PPT Presentation

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  • ARM Cortex-M0August 23, 2012 Paul Nickelsberg Orchid Technologies Engineering and Consulting, Inc. www.orchid-tech.com

    CORTEX-M0 Structure Discussion 3

  • Cortex-M0 Structure Discussion 3Topics TodayCORTEX-M0 Power ManagementCORTEX-M0 Fault HandlingCORTEX-M0 Stack StructuresCORTEX-M0 SVC/WFE/WFI Instructions

  • Cortex-M0 Power ManagementOur discussion focuses on Cortex-M0 Power Management as distinct from additional power management features which may be implemented by a particular device vendor

    Cortex-M0 Power ManagementLow Power Instruction ExecutionSleep Mode SupportDeep Sleep Mode SupportWake-Up Interrupt ControllerWFE / WFI Instruction Support

    Device Specific Power ManagementPeripheral Power On/Off ControlPhase Locked Loop ControlPeripheral Clock Source ControlPeripheral Clock Rate ControlState Saving RegistersReal Time Clock FeaturesOn-Chip Oscillator Support

  • Cortex-M0 Power ManagementLow Power Instruction ExecutionApprox Current in mAApprox Speed in MHz

    Chart1

    2.32.24

    2.62.48

    2.92.72

    3.22.96

    3.53.2

    3.83.44

    4.13.68

    4.43.92

    4.74.16

    54.4

    5.34.64

    5.64.88

    5.95.12

    6.25.36

    6.55.6

    6.85.84

    7.16.08

    7.46.32

    7.76.56

    86.8

    8.37.04

    8.67.28

    8.97.52

    9.27.76

    Cortex-M0

    Cortex-M0+

    Sheet1

    Cortex-M0Cortex-M0+2

    22.32.24

    42.62.48

    62.92.72

    83.22.96

    103.53.2

    123.83.44

    144.13.68

    164.43.92

    184.74.16

    2054.4

    225.34.64

    245.64.88

    265.95.12

    286.25.36

    306.55.6

    326.85.84

    347.16.08

    367.46.32

    387.76.56

    4086.8

    428.37.04

    448.67.28

    468.97.52

    489.27.76

  • Cortex-M0 Power ManagementSleep Mode Stops Processor Clock

    Deep Sleep Mode Stops System Clock, Power off PLL, and Memory

    Mode Selection made using SCB RegisterCortex-M0 Power Modes

  • Cortex-M0 Power ManagementWFI Instruction Execution of WFI Instruction causes processor to immediately enter selected sleep modeWFE Instruction Execution of WFE Instruction causes processor to enter selected sleep mode if event bit is setExit Processor Exception If SLEEPONEXIT bit is set in SCB Register, processor enters selected sleep mode on return from exception to thread modeCortex-M0 Entry into Power Saving Modes

  • Cortex-M0 Power ManagementWake-Up from WFI or SLEEPONEXIT Upon receipt of Prioritized Interrupt, processor immediately resumes execution of instructionsWakeup from WFE Upon receipt of Prioritized Interrupt or external event signal, processor immediately resumes execution of instructionsWakeup using WIC Upon receipt of Wake-up Interrupt Controller Signal, processor immediately resumes execution of instruction. This feature is optional and when implemented usually applies to Deep Sleep wakeup onlyCortex-M0 Exit from Power Saving Modes

  • Cortex-M0 Power ManagementNormal Instruction ExecutionWFINormal Instruction ExecutionSleepIRQTimeFull PwrLow Pwr

  • Cortex-M0 Fault HandlingHARDFAULT Vector The HARDFAULT Vector catches processor faultsProcessor FaultsSVC Instruction Priority ErrorBKPT w/o DebuggerSystem Generated Bus ErrorAttempted execution of instruction in XN Memory AreaAttempted execution of undefined instructionAttempted load or store to unaligned addressProcessor Lockup (Double Fault) Occurs when Fault occurs in NMI or HARDFAULT Handler

  • Cortex-M0 Fault HandlingNormal Instruction ExecutionBad InstructionNormal Instruction ExecutionHardFaultRESETBad InstructionLock UpReset or NMI restarts processorHardFault Exception preempts all other exceptions

  • Cortex-M0 Stack StructureCortex-M0 Stack pushes data onto the stack from higher to lower addressesSP Here before InterruptSP Here after Interrupt

    SPContentSP + 0x1CPSRSP + 0x18PCSP + 0x14LRSP + 0x10R12SP + 0x0CR3SP + 0x08R2SP + 0x04R1SP + 0x00R0

  • Meaning and ImplicationsProcessor Architecture 8 Bit World to 32 Bit WorldProcessing Capability8 Bit Architecture32 Bit CORTEX-M0- Low Power Instruction Execution- Sleep Power Mode- Deep Sleep Power Mode- WFI / WFE Sleep Entry- Fault Handling

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