april 28th, 2011timing workshop, chicago paul scherrer institute limiting factors in switched...

April 28th, 2011Timing Workshop, Chicago

Paul Scherrer Institute

Limiting factors in Switched Capacitor ArraysSampling speed, Timing accuracy, Readout speed

Stefan Ritt

Stefan Ritt

Follow-up: Optimal Sampling Speed


Threshold

Theory (Nyquist): 1 GHz signal: 350 ps rise-time, 2 GSPS

Reality: Noise! (e.g. quantization noise of ADC) andtail of input power

350 ps

500 ps

Stefan Ritt

Measured Resol. Mod724, 14 bit, 100 MS/s


50

mV 100 mV 200

mV500 mV

Std

Dev (

ns)

5*T

C. Tintori

Stefan Ritt March 15th, 2011DPP Workshop PSI

Switched Capacitor Array

Shift RegisterClock

IN

Out

“Time stretcher” GHz MHz“Time stretcher” GHz MHz

Waveform stored

Inverter “Domino” ring chain0.2-2 ns

FADC 33 MHz

Stefan Ritt April 28th, 2011Timing Workshop, Chicago

Limits on sampling speed

vs. technology

Stefan Ritt

Inverter chain


RC-delay with TGRC-delay with TG Starved invertersStarved inverters

• Layout more compact• Used in DRS4 chip• TG in signal path• Parasitics of TG counts

• Layout more compact• Used in DRS4 chip• TG in signal path• Parasitics of TG counts

• Used in most designs• “Starving” trans. outside

signal path• Parasitics do not count

• Used in most designs• “Starving” trans. outside

signal path• Parasitics do not count

Stefan Ritt

Cpar = 5 fF Transmission Gates

Starved Inverters

0.25 UMC 3.7 GHz 13.0 GHz

0.25 UMC GAA

5.9 GHz

0.13 IBM 2.1 GHz 17.9 GHz

0.11 UMC 3.8 GHz 20.3 GHz

0.11 UMC HS 4.1 GHz 23.0 GHz

Achievable sampling speeds


• Starved inverters better than TG• Speed does not linearly scale with technology

(parasitics limited)• High speed (low Vt) option helps

• Starved inverters better than TG• Speed does not linearly scale with technology

(parasitics limited)• High speed (low Vt) option helps

DRS4DRS4

Stefan Ritt

Today highest sampling speed


130 IBM, J.-F. Genat, Clermont-Ferrand, Jan. 2011

Stefan Ritt

Interleaved sampling


• Fine tuning delays STURM chip (Gary): O(100 GSPS)

• For fixed interleaving, this can also be achieved by chip layout

• Alternative: Comparators with different thresholds

• Fine tuning delays STURM chip (Gary): O(100 GSPS)

• For fixed interleaving, this can also be achieved by chip layout

• Alternative: Comparators with different thresholds


Limits on analog bandwidth

Parasitics, bond wires, Ron of sampling cell

Stefan Ritt

PCB


• Detector (covered in next talks)• Connector (LEMO connector has a BW of ∼500 MHz)• Cable (RG58: 5 m has a -3db BW of 1 GHz)• PCB• Preamplifier• Chip package• On-chip bus• Analog cell switch• Storage capacitor

Signal Chain

Det.Chip

€

f3db =1

2πRC

Cpar


Influence on chip package

• Bond wire has ~2-3 nH and thus limits the BW to 2-3 GHz• Input inductance can be reduced by using bump bonding or stud bonding

200 m

75 m

WireWire

BumpBump

StudStud

Stefan Ritt

Effect of “write bus”


DRS3: 300 MHz with 2m width

Length: 3500 uWidths: 4x8u, 4x14u (beginning/end of bus)

Stefan Ritt

Influence on parasitics


DRS3: 300 MHz with 2u width

• Minimal write switch has ~10 fF parasitic capacitance• Write bus has resistance of ~0.05 Ohm/square

(0.013 Ohm square for 20k top metal option)→ 15 Ohm after 3 mm bus + bond wire (1.5 Ohm)→ 10 pF after 3 mm

• Minimal write switch has ~10 fF parasitic capacitance• Write bus has resistance of ~0.05 Ohm/square

(0.013 Ohm square for 20k top metal option)→ 15 Ohm after 3 mm bus + bond wire (1.5 Ohm)→ 10 pF after 3 mm

€

f3db =1

2πRC

DRS4DRS4

Stefan Ritt

• Write switch has a finite “on” resistance• Storage cap needs to be >10 fF for

reasonable kTC noise• Leakage current requires even bigger C

• Simulation• Cstore = 50 fF• UMC 0.25 um technology• Vdd = 2.5V• Minimal l• W = 0.25 um * N

• Note: N>1 adds parasitic to write bus!

Influence of write switch


wopt. ~ 6 um

-3db B

andw

idth

[G

Hz]

Stefan Ritt

• Smaller Cstore leads to higher bandwidth• But: kTC noise → 20 fF for 11 bits• Practical limit: ∼ 5 fF• Important: Leakage current!

• Worse with smaller technologies• Non-Gaussian distribution on chip• Worse for low Ron switch• Temperature dependent

Effect on sampling capacitor


G. Varner

€

vRMS =kT

Cstore

Stefan Ritt

Leakage current


• Leakage current: Must be small to get V<<1mV during readout

• Distribution has long tail• Either make C large or

keep storage time short

• Leakage current: Must be small to get V<<1mV during readout

• Distribution has long tail• Either make C large or

keep storage time short

G. Varner, 2010, Krakov

Stefan Ritt

Comparison between technologies


UMC 0.257 k

6 m opt.16 GHz

UMC 0.257 k

6 m opt.16 GHz

UMC 0.115 k

180 m opt.21 GHz

UMC 0.115 k

180 m opt.21 GHz

UMC 0.11 low Vt

4 k120 m opt.

37 GHz

UMC 0.11 low Vt

4 k120 m opt.

37 GHz

Ron [

k]

VDS [V]

dI/dU

N/1000

BW

[G

Hz]


Bandwidth DRS4 (1024 sampling cells)

Bandwidth is determined by bond wire and internalbus resistance/capacitance:

850 MHz (QFP), 950 MHz (QFN), ??? (flip-chip)

850 MHz (-3dB)

QFP package

finalbus width

SimulationMeasurement

Stefan Ritt

Bandwidth STURM2 (32 sampling cells)


G. Varner, Dec. 2009

Stefan Ritt

Optimal Chip Layout


Bond Pad

Bond Pad

32 sampling cellswrite+

write-

…


Limits on timing resolution

Matching – PLL phase jitter – Aperture

Stefan Ritt

• “Matching” (inverter-to-inverter variation by statistical limits in doping) is fixed over time and can be corrected

• PLL phase jitter is typical 25 ps can can be corrected for with separate timing channel (DRS4: 8+1 channels)

• Residual cell jitter caused by Vdd noise, short delay line is better

Typical SCA PLL


T Q

PhaseComparator

ExternalReference

Clock

Inverter Chain

loopfilter

down

1

2

sampling speed control

PLLup


Residual aperture jitter

Noise

Timing

• Vdd (GND) noise causes jitter• Effect worse if rise time is slow

(starving)• Typical values:

• 100 ps rise time for 1.2 V signal

• 5 mV noise• 32 cells• Jitter: 5 mV/1.2 V * 100 ps *

32 = 13 ps• Noise can originate off-chip

(e.g. running ADC)• Solution: Differential inverters,

LDO on chip• Disadvantage: More power

• Vdd (GND) noise causes jitter• Effect worse if rise time is slow

(starving)• Typical values:

• 100 ps rise time for 1.2 V signal

• 5 mV noise• 32 cells• Jitter: 5 mV/1.2 V * 100 ps *

32 = 13 ps• Noise can originate off-chip

(e.g. running ADC)• Solution: Differential inverters,

LDO on chip• Disadvantage: More power


Limits on readout speed

Analog-Digital readout, multi-buffer

Stefan Ritt

Readout time


N inputchannels

M outputchannels

treadout = N/M * nsamples * tsampletreadout = N/M * nsamples * tsample

Analog: tsample = 20 – 100 ns (external ADC 10-50 MHz)Digital: tsample = 5 – 10 ns * nbits / nlines

1024 samples, 10 bits, N=8, M=1 → treadout = 400 s32 samples, 10 bits, N=8, M=8 → treadout = 1.6 s

Analog: tsample = 20 – 100 ns (external ADC 10-50 MHz)Digital: tsample = 5 – 10 ns * nbits / nlines

1024 samples, 10 bits, N=8, M=1 → treadout = 400 s32 samples, 10 bits, N=8, M=8 → treadout = 1.6 s

Stefan Ritt March 25th, 2011FEE2010, Bergamo

ROI readout mode in DRS4

readout shift register

Triggerstop

normal trigger stop after latency

Delay

delayed trigger stop

Patent pending!

33 MHz

Stefan Ritt

“Multi-buffering” can reduce dead time for Poisson-distributed events

Multi buffering


Event is stored in first buffer

Event occurring duringreadout of first event is stored in second buffer

R: event rate [Hz] T: readout time [s]LT: “live time”N: Number of buffers

R: event rate [Hz] T: readout time [s]LT: “live time”N: Number of buffers

N LT

1 67 %

2 94 %

3 99.2 %

4 99.9 %

R = 1 kHz, T=400 s

€

LT = e−R ⋅T(R⋅T)i

i!i=0

N −1

∑

Cumulative distribution function for Poisson-distributed events:

Stefan Ritt

• Has to accommodate trigger delay

• High energy physics experiments require 100’s of buffered events

• CMS: Possible hit every bunch crossing at 25 ns, 155 bunch crossings before L1 trigger

• ILC: ∼3000 bunch trains ∼ 5 Hz

• TOF-PET: > MHz event rate

Storage Depth


CTACTA

ILCILC

→ Deep storage depth→ Many storage segments→ High event rate

→ Deep storage depth→ Many storage segments→ High event rate

Stefan Ritt

The vision for the future


ThePerfect Chip

Low number of input cellsLow number of input cells

DeepSampling Depth

DeepSampling Depth

Higheventrate

Higheventrate

Highchanneldensity

Highchanneldensity

Low powerLow

power

Manyanalogbuffers

Manyanalogbuffers


Cascaded Switched Capacitor Arrays

shift registerinput

fast sampling stage secondary sampling stage

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

• 32 fast sampling cells at 10 GSPS

• 100 ps sample time, 3.1 ns hold time

• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)

• Shift register gets clocked by inverter chain from fast sampling stage

• 32 fast sampling cells at 10 GSPS

• 100 ps sample time, 3.1 ns hold time

• Hold time long enough to transfer voltage to secondary sampling stage with moderately fast buffer (300 MHz)

• Shift register gets clocked by inverter chain from fast sampling stage


Typical Waveform

Only short segments of waveform are of interestOnly short segments of waveform are of interest


Dead-time free acquisition

• Self-trigger writing of 128 short 32-bin segments (4096 bins total)

• Simultaneous writing and reading ofsegments

• Quasi dead time-free• Data driven readout

• Ext. ADC runs continuously• ASIC tells FPGA when there is new data• Possibility to skip segments → analog

buffer for HEP experiments• Coarse timing from

300 MHz counter• Fine timing by waveform

digitizing and analysis in FPGA• 20 * 20 ns = 0.4 s readout time

2 MHz sustained event rate (ToF-PET)• Attractive replacement for CFD+TDC

coun

ter

latc

hla

tch

latc

hwrite

pointer

readpointer

digital readout

analog readout

trigger

FPGA

DRS5

planned for 2013

Stefan Ritt

• SCAs will more and more replace Q-ADC and CFG+TDCs

• New designs are in the pipeline for >3 GHz analog BW, multi-buffering and fast readout

• Current limitations areare well known and will bepushed further in nextgeneration of chips

Conclusions


april 28th, 2011timing workshop, chicago paul scherrer institute limiting factors in switched...

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