IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 58, NO. 5, MAY 2009 1617

Analysis of a Sigma–Delta Resistance-to-DigitalConverter for Differential Resistive Sensors

N. Madhu Mohan, Boby George, and V. Jagadeesh Kumar, Member, IEEE

Abstract—A direct resistance-to-digital converter (RDC) that issuitable for differential resistive sensors is proposed and analyzedin this paper. The RDC presented here provides a digital outputthat is linearly proportional to the parameter being sensed bya differential resistive sensor possessing either linear or inversecharacteristics. The RDC employs the sigma–delta analog-to-digital conversion (Σ–Δ ADC) principle and, hence, possesses allthe advantages and limitations of such an ADC. Analysis showsthat the proposed RDC has negligible sensitivity to variations incircuit parameters. Experimental results on a prototype built andtested gave a worst-case error < 0.15%, establishing the efficacyof the proffered RDC.

Index Terms—Differential resistive sensor, direct digital con-verter, resistance-to-digital converter (RDC), signal conditioning,sigma–delta (Σ–Δ) converter.

I. INTRODUCTION

D IFFERENTIAL resistive sensors are quite popular for themeasurement of physical variables such as displacement

and pressure. A typical differential resistive sensor possessestwo resistances. The value of one of the resistors of the sensor(for example, R1) will increase with the measurand, while thevalue of the other resistor (R2) will decrease. The values of theresistances of a differential resistive sensor possessing a linearcharacteristic can be expressed as [1]

R1 = R0(1 ± kx), R2 = R0(1 ∓ kx) (1)

where k is the transformation constant of the sensor and R0

is the nominal value of the resistor when x, which is theinput parameter being sensed, is zero. On the other hand, theresistance of a differential resistive sensor possessing an inversecharacteristic can be expressed as [2]

R1 =R0

(1 ∓ kx), R2 =

R0

(1 ± kx). (2)

To obtain a measurable output from a differential resis-tive sensor, a suitable analog signal conditioning circuit suchas a Wheatstone bridge is required. Modern instrumentationsystems are of the digital kind, as digital systems offer in-

Manuscript received June 21, 2008; revised December 18, 2008. First pub-lished February 6, 2009; current version published April 7, 2009. The AssociateEditor coordinating the review process for this paper was Dr. Izzet Kale.

N. M. Mohan and V. J. Kumar are with the Measurements and Instrumen-tation Laboratory, Department of Electrical Engineering, Indian Institute ofTechnology Madras, Chennai 600036, India (e-mail: vjk@iitm.ac.in).

B. George is with the University of Graz, 8010 Graz, Austria.Color versions of one or more of the figures in this paper are available online

at http://ieeexplore.ieee.org.Digital Object Identifier 10.1109/TIM.2009.2012949

Fig. 1. Proposed Σ–Δ RDC.

creased processing power and excellent user interface com-pared with their analog counterparts. An analog-to-digital con-verter (ADC) is required to interface the output from ananalog signal conditioner to a digital instrumentation system[3], [4]. It would be advantageous if the signal conditioningcircuit directly provides a digital output without the need foran intervening ADC. Such a signal conditioning circuit iscalled a direct digital converter. Direct capacitance-to-digitalconverters (CDCs), based on the principles of the relaxationoscillator [5] and the sigma–delta (Σ–Δ) ADC [6]–[8], thatare suitable for capacitive type sensors have been reported.Techniques that provide resistance-to-digital conversion usingan RC oscillator and timer-counter [9], resistance-to-frequency[10], and resistance-to-time [11] conversions are available forsingle-element resistive sensors. A method based on capaci-tor charging that is suitable for both single (half-bridge) anddifferential (full-bridge) resistive sensors is also reported [12].Methods that are suitable for differential resistive sensors basedon integrating-type ADC have also been reported [13]–[15].

A novel direct resistance-to-digital converter (RDC) that issuitable for differential resistive sensors is proposed [16]. Theproposed scheme, based on the principle of the popular Σ–ΔADC, accepts differential resistive sensors possessing eitherlinear or inverse characteristics and provides a linear digitaloutput that is proportional to the measurand being sensed by thedifferential resistive sensor. The analysis presented in this paperindicates that the proposed scheme is not affected by the non-ideal characteristics of components and that the sensitivity ofthe output to variations in the nominal values of the componentsis minimal. Parameters that decide the error in the output andthe critical components that dictate the accuracy of the outputare clearly identified.

II. Σ–Δ RDC

Fig. 1 shows the functional block diagram of the Σ–Δ-typeRDC that is suitable for a differential resistive sensor. TheRDC is made of a Δ-modulator, followed by an oversampler

0018-9456/$25.00 © 2009 IEEE

1618 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 58, NO. 5, MAY 2009

and a digital filter. The op-amp OA with capacitor CF inits feedback path and resistors R1 and R2 of a differentialresistive sensor, in combination with two single-pole–double-throw (SPDT) analog switches S1 and S2 serving as input, forman integrator. The free end of R1 is switched to +VR when S1 isin position 2 and connected to ground when S1 is in position 1.When S2 is in position 1, the free end of R2 is connected to−VR, while when S2 is in position 2, it is connected to ground.+VR and −VR are dc reference voltages of equal magnitudebut of opposite polarities. The output voi of the integrator isfed to a comparator OC whose output is “low” if voi ≥ 0 and“high” otherwise. The output of OC is given to the input of aD flip-flop whose binary output y controls switches S1 and S2.Switches S1 and S2 are set at position 1 if y = 1 and set atposition 2 whenever y = 0. The D-flip-flop output y, which isupdated (for example, at the leading edge) by a high-frequencyclock of time period TC , is also fed as input to a digital low-pass-filter (LPF)-based circuit, which extracts and provides asthe final output (1 − 2y|avg), where y|avg is the average valueof the LPF input bit stream y.

To start with, let voi < 0 and y = 1. Hence, switches S1

and S2 are set at position 1. R1 is connected to ground, andR2 is tied to −VR. voi ramps up with a slope of (VR/R2CF )until it becomes positive. Once voi is positive, the comparatoroutput becomes low. The D-flip-flop output gets updated atthe very next (leading edge of the) clock, and the output ytoggles (y = 0). When y = 0, switches S1 and S2 are setto position 2, grounding resistance R2 and connecting R1 to+VR. The current VR/R1 charges CF . Consequently, voi rampsdown with a slope VR/R1CF until voi turns negative, forcingthe output of the comparator to go high. The D-type flip-flopoutput gets updated on the next clock, making y = 1, bringingthe status of the circuit to its assumed initial condition, andhence, the entire cycle repeats continuously. When y = 1, thechange in integrator voltage for each clock period is Δvoi(1) =VRTC/R2CF . Similarly, when y = 0, the change in integratorvoltage for each clock period is Δvoi(0) = −VRTC/R1CF .After a finite number of clock cycles, for instance, N (periodT = NTC), the integrator output is

voi(N) =VRTC

R2CFN(1) −

VRTC

R1CFN(0)

where N(1) and N(0) are the numbers of clock cycles for whichthe output values of D flip-flop are 1 and 0, respectively, withinthe period T and N = N(1) + N(0). If N is sufficiently large,then the value of voi(N) has to be less than or equal to themaximum possible change in integrator voltage per clock cyclevoi(m), where

voi(m) = VRTC/(R1, R2)minCF (3)

and (R1, R2)min is the minimum among R1 and R2. Then

VRTC

CF

(N(1)

R2−

N(0)

R1

)≤ VRTC

CF

1(R1, R2)min

. (4)

On further simplification, we get(N(1)R1 − N(0)R2

)≤ (R1, R2)max (5)

where (R1, R2)max is the maximum of R1 and R2. Substitutingthe values of R1 and R2 of a differential resistive sensorpossessing linear characteristics, as given by (1) in (5), re-sults in (R0(1 ± kx)N(1) − R0(1 ∓ kx)N(0)) ≤ (R1, R2)max,leading to

R0

N

[(N(1) − N(0)

)± kxN

]≤ 1

N(R1, R2)max. (6)

For a very large value of N , the value of 1/N(R1, R2)max

becomes small, and hence

kx =[N(0) − N(1)

N

]= 1 − 2

(N(1)

N

)=

(1 − 2y

∣∣avg

).

(7)

(N(1)/N) is the average value y|avg of the bit stream y over theperiod NTC . Since the digital LPF-based circuit is designed toextract (1 − 2y|avg)—as mentioned earlier—its output is kx.Hence, for differential resistive sensors possessing linear char-acteristics, as given by (1), the proposed technique provides alinear digital output that is proportional to the quantity beingsensed. Very rarely, differential resistive sensors possess inversecharacteristics, as given by (2). It turns out that substituting thevalues of R1 and R2, as given by (2) in (5), also results in (7).Thus, the proposed method provides a linear digital outputthat is proportional to the measurand, even if the differentialresistive sensor follows an inverse relationship, as given in (2).The results of simulation studies and details of a prototype RDCbuilt and tested using off-the-shelf components are given in thesequel. The errors introduced due to various circuit parametervariations are analyzed next.

III. ERROR ANALYSIS AND DISCUSSION

It should be noted here that the proposed RDC is obtainedby suitably converting the 1-b quantizer (Δ-modulator) in aconventional Σ–Δ ADC. Hence, the proposed method will nec-essarily possess noise shaping characteristics, bandwidth limi-tations, and uncertainties, as detailed in IEEE Std. 1241–2005[17] and elsewhere [18]–[21]. Over and above the well-knownand well-established uncertainties, the RDC will possess addi-tional errors due to the modification itself. The possible errorsthat would arise due to the modification, such as introductionof switches and two reference voltages instead of one as in aconventional Σ–Δ ADC, are analyzed next.

Ideal conditions are assumed while deriving (3), (5), and (6).In a practical case, errors will be introduced in the output dueto the following factors: 1) difference in the magnitudes of thepositive and negative dc reference voltages; 2) offset voltages ofOA and OC; 3) on-resistances of the switches; 4) switch leakagecurrents; 5) op-amp bias current; and 6) stray capacitances. Thefollowing sections discuss in detail the effect of each parameteron the output.

A. Effect of Mismatch in DC Reference Voltages

The magnitudes of dc reference voltages +VR and −VR areassumed to be equal in deriving (5). However, in practice, there

MOHAN et al.: ANALYSIS OF A SIGMA–DELTA RDC FOR DIFFERENTIAL RESISTIVE SENSORS 1619

will be a small mismatch between them, and hence, in general,| + VR| = | − VR|(1 ± β), where β is the factor indicating theextent of mismatch. In such a condition, (5) gets modified as(N(1)(1 ± β)R1 − N(0)R2) ≤ (R1, R2)max.

Hence

±kx =[N(0) − N(1) ∓ βN(1)

N ± βN(1)

]

=

⎡⎣(

N(0) − N(1)

N∓

βN(1)

N

)1(

1 ± βN(1)

N

)⎤⎦ .

For (β(N(1)/N)) � 1 and neglecting (β(N(1)/N))2 andhigher powers of (β(N(1)/N)), we get

±kx =[(

N(0)−N(1)

N∓

βN(1)

N

)(1∓β

N(1)

N

)]

= (1−2y|avg) (1∓βy|avg)∓(βy|avg)±(βy|avg)2 .

The resulting relative error εVRis shown at the bottom of

the page.For full-scale reading, if y|avg → 1, then

εVR=

(1 − 2)(1 ∓ β) ∓ (β) ± (β)2 − (1 − 2)(1 − 2)

=(−1)(1 ∓ β) ∓ (β) ± (β)2 − (−1)

(−1)= 2β + β2

resulting in the error due to mismatch in dc referencevoltages as

% εVR= (2β + β2) 100. (8)

For the prototype developed, β was found to be 4 × 10−5,and the error in the output due to mismatch in dc referencevoltages works out to be 0.008%.

B. Effects of Offset Voltages of Op-Amp OAand Comparator OC

If the op-amp OA has an offset voltage ±vos, then thevoltages across the sensor resistances R1 and R2 become(+VR ∓ vos) and (−VR ∓ vos), respectively. This condition isequivalent to a mismatch of 2vos between the magnitudes ofdc reference voltages +VR and −VR. Thus, by taking β =2vos/VR, the ensuing error in the output can be computed using(8). For the prototype, op-amp OP07, which has a maximumoffset voltage of 25 μV, was used, resulting in a worst-caseerror of 0.004%.

The offset voltage of the comparator shifts its reference pointby the same amount from zero. As long as the offset voltage ofOC remains constant (comparator that has negligible offset drift

within one conversion period) during a complete conversionperiod, it has negligible effect on the final output.

C. Effects of On-Resistance of the Switches

In the proposed scheme, the on-resistance rON1 of switch S1

is in series with R1, while the on-resistance rON2 of switch S2

is in series with R2. It is equivalent to a change in the val-ues of sensor resistances R1 and R2 with new values (R1 +rON1) and (R2 + rON2), respectively. In this condition, (5) getsmodified as (N(1)R1 + N(1)rON1 − N(0)R2 − N(0)rON2) ≤(R1, R2)max, and hence, we have

(1−2y|avg)=±kx

[1

1+ rON1+rON2R0

]−

[rON1−rON2

R0+rON1+rON2

].

(9)

Comparison of (7) and (9) indicates that the switch on-resistances introduce a gain error and an offset in the output.If we employ identical switches for S1 and S2, then rON1 ≈rON2, and the offset will be zero. The gain error can bemade negligible by ensuring that R0 � (rON1 + rON2). Forthe prototype, MAX4680 switches (rON = 1.25 Ω) were used,resulting in a gain error of −0.42% and an offset of 0.05% withR0 = 600 Ω. The gain error and the offset, if present, can beeasily reduced by providing suitable compensation. In fact, thisis the only significant factor contributing to the errors in theproposed RDC, and therefore, care must be taken to minimizethis error.

D. Effects of Switch Leakage Currents

Leakage currents between nodes 1 and 2 of switches S1 andS2 flow from the dc reference sources to the circuit groundand hence do not charge or discharge CF . When S1 is atposition 1, leakage current IL1 exists between nodes 2 and A.In this condition, the resistance between nodes A and 1 isrON1. As rON � R0, a large portion of the leakage currentIL1 flows to circuit ground via node 1, and a negligibleamount—IL1[rON1/(rON1 + R1)]—compared with the sensorcurrent of (VR/R1), flows through R1. Similar conditions areapplicable for S2. Thus, in a practical situation, switch leakagecurrents have negligible effect on the output. For the prototype,the leakage current was 5 nA, resulting in negligible error.

E. Effect of Bias Current of the Op-Amp OA

Depending on its polarity, the op-amp bias current (IB) ofOA charges the capacitor CF in a given direction throughout atypical conversion time. The bias current manifests as a changein the charging currents as ((VR/R1) ± IB) and ((VR/R2) ∓IB) through the sensor resistances R1 and R2, respectively.

εVR=

(1 − 2y|avg) (1 ∓ βy|avg) ∓ (βy|avg) ± (βy|avg)2 − (1 − 2y|avg)

(1 − 2y|avg)

1620 IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT, VOL. 58, NO. 5, MAY 2009

Fig. 2. Differential resistive sensor elements with possible stray capacitances.Nodes A and C are connected to S1 and S2, respectively, while node B isconnected to the inverting terminal of the op-amp OA, as shown in Fig. 1.

It can also be represented as an equivalent change in the dcreference voltage +VR. Thus, it is equivalent to a mismatchbetween reference voltages, and the ensuing worst-case full-scale error due to the bias current of the op-amp OA can becomputed using (8) by substituting for β = (IB/VR)(R1 +R2) = 2(IBR0/VR). The effect can be made insignificant byselecting an op-amp with very low IB—satisfying the conditionIB � VR/R0—to realize OA.

F. Effect of Stray Capacitances

In practice, it may well be that the sensor unit is far fromthe signal conditioning unit and that the electrical connectionsbetween these units are made using shielded cables. Distributedcapacitances will exist between the live conductor of eachcable and its grounded shield. This effect can be representedby lumped stray capacitances, as shown in Fig. 2. Stray ca-pacitances CAG, CBG, and CCG exist from nodes A, B,and C, respectively, to ground. CAG charges to +VR when S1

is at position 2. Similarly, CCG charges to −VR when S2 is atposition 1. Whenever S1 is switched to position 1 and S2 toposition 2, the charge acquired by the corresponding capaci-tances CAG and CCG discharges to ground through the low-impedance path offered by the switch on-resistance. As longas the time-constant rON1CAG � R1CAG and rON1CCG �R2CCG, the stray capacitances CAG and CCG will have negli-gible effect on the operation of the circuit. As node B is alwaysat virtual ground, CBG will not charge or discharge during theoperation of the circuit.

IV. SIMULATION STUDIES

Before prototyping the circuit shown in Fig. 1, it was sim-ulated using OrCAD PSpice (version 9.0). Since a model ofthe digital filter AD1556 was not available, the low-pass digitalfunction of the AD15556 was realized by a switching andaveraging technique. The resistance of the differential resistivesensor was varied in a range of +50% of its nominal value of600 Ω, in steps of ±5%. To simulate the effect of the switchresistance (rON), a resistor of 1.25 Ω was included in serieswith the sensor resistances. The output was sampled after thesimulation was allowed to run for 200 ms to ensure that alltransients die out. First, the resistances were varied linearly,as given by (1), and the output and error for this case areshown in Fig. 3. A similar simulation was run for a sensor withinverse characteristics of the form given by (2), and the resultsare shown in Fig. 4. The circuit was again simulated with theswitch resistances suitably modified in order to determine theeffect of mismatch in rON. It was found that the worst possible

Fig. 3. Simulation results for a sensor with linear characteristics.

Fig. 4. Simulation results for a sensor possessing inverse characteristics.

error in the output for a mismatch of 100% was only 0.51%.Similarly, the magnitude of the reference voltages was alteredto understand its effect on the output. A 1% mismatch in theirmagnitudes produced a maximum variation of 4.12% in theoutput.

V. EXPERIMENTAL RESULTS

A prototype Σ–Δ RDC was built and tested in the laboratory.The reference voltage +VR was generated using the referencediode LM385-1.2 [22], which was buffered with a voltagefollower (op-amp OP07) [23]. −VR was obtained with thehelp of a unity gain inverter realized with a second OP07.The magnitude of −VR was trimmed to obtain a match (upto five digits) between +VR and −VR. SPDT switches wererealized with IC MAX4680 [24] (possessing low on-resistancerON = 1.25 Ω). A third OP07 served as the op-amp OA. Thevalue of the feedback capacitor was chosen as 0.33 μF tolimit the maximum change in the integrator voltage per clockcycle to be less than the slew rate of the OP07. An LM311 IC[25] served as the comparator (OC), and the CD4013 [26] wasemployed for the D flip-flop. To extract y|avg, the IC AD1556was employed. The AD1556 [27] implements a finite-impulse-response linear-phase equiripple LPF and a decimator. Themodulator clock frequency was chosen to be 20 kHz. A suitableprogram was written and burned into a PIC16F877A microcon-troller [28] to read the output y|avg from the AD1556, compute,

MOHAN et al.: ANALYSIS OF A SIGMA–DELTA RDC FOR DIFFERENTIAL RESISTIVE SENSORS 1621

Fig. 5. Output of D flip-flop (y) and integrator voltage voi, along with theclock signal recorded from the prototype.

Fig. 6. Experimental results of the prototype Σ–Δ RDC.

and then display (1 − 2y|avg) on a five-digit seven-segmentdisplay. A typical conversion time of the prototype Σ–Δ RDCwas 40 ms.

The prototype developed was tested with resistive sensorspossessing linear as well as inverse characteristics. It was foundto provide a linear digital output in both cases. Typical wave-forms obtained from the prototype are shown in Fig. 5. To testthe performance of the prototype RDC, transducer resistanceswere simulated using two precision decade resistance boxesfrom Otto Wolff, Germany, having a resolution of 1 Ω and anaccuracy of ±0.01%. The nominal value of the resistances wasselected as 600 Ω, and R1 and R2 were varied up to 300 Ωin steps of 6 Ω, to simulate a kx variation in the range of ±0.5,with increments of ±0.01. The output characteristic, along withthe percentage relative error of the prototype, is shown in Fig. 6.The worst-case error was found to be less than ±0.15%.

VI. CONCLUSION

An RDC that provides a direct digital output that is propor-tional to the parameter being sensed by a differential resistivesensor is presented. The topology of the RDC is obtained byincorporating the differential resistive sensor as an integral partof a first-order 1-b quantizer of a conventional Σ–Δ ADC.Hence, the proposed RDC has all the advantages and limitationsof a typical Σ–Δ ADC. The quantizer is controlled suitably,

and the form of the final digital output is chosen so thatthe RDC provides a linear digital output that is proportionalto the parameter being sensed by sensors possessing eitherlinear or inverse characteristics and is hence applicable to bothtypes of sensors without any change. The resolution requiredin applications involving differential resistive sensors seldomexceeds 16 b, which is easily achievable (the prototype builtand tested had a resolution of 24 b) with the present technique.The conversion speed of few hundred samples per second tofew tens of thousand samples per second that is achievablewith the Σ–Δ converter topology is more than adequate forapplications (distance and pressure sensing) concerning differ-ential resistive sensors. The effects of various circuit parameterson the performance of the RDC are analyzed and found tobe negligible or can be made so with proper selection ofthe circuit components. Simulation studies and experimentalresults obtained from a prototype built and tested establish thepracticality of the proposed RDC. The worst-case error of theprototype was found to be less than ±0.15%. This type of RDCis best suited for micromechanical systems type of applications.

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N. Madhu Mohan was born in Coimbatore, India,on March 21, 1970. He received the B.S. degree inelectronics and communication engineering from theUniversity of Calicut, Kerala, India, in 1991 and theM.S. degree (by research) from the Indian Institute ofTechnology Madras, Chennai, India, in 2003, wherehe is currently working toward the Ph.D. degreein biomedical instrumentation with the Measure-ments and Instrumentation Laboratory, Departmentof Electrical Engineering.

His interests include measurements, biomedicalinstrumentation, and virtual instrumentation.

Boby George was born in Kannur, India, onApril 30, 1977. He received the B.S. degree in elec-trical engineering from the Institution of Engineers,Kolkata, India, in 2001 and the M.S. and Ph.D.degrees in electrical engineering from the IndianInstitute of Technology Madras, Chennai, India, in2003 and 2007, respectively.

He is currently a Postdoctoral Fellow with the Uni-versity of Graz, Graz, Austria. His areas of interestinclude measurements, instrumentation, and virtualinstrumentation.

V. Jagadeesh Kumar (M’94) was born in Madras,India, on July 21, 1956. He received the B.E. degreein electronics and telecommunication engineeringfrom the University of Madras, Chennai, India, in1978 and the M.Tech. and Ph.D. degrees in electri-cal engineering from the Indian Institute of Tech-nology (IIT) Madras, Chennai, in 1980 and 1986,respectively.

He is currently the Head of the Department ofElectrical Engineering, IIT Madras, where he is withthe Measurements and Instrumentation Laboratory.

He was a BOYSCAST Fellow with King’s College, London, U.K., dur-ing 1987–1988 and a DAAD Fellow with the Technical University ofBraunschweig, Braunschweig, Germany, in 1997. He was a Visiting Scientistwith the Technical University of Aachen, Aachen, Germany, in 1999. Hetaught for a term at the Asian Institute of Technology, Bangkok, Thailand, inthe summer of 1999. He has published more than 40 papers in internationaljournals and presented more than 60 papers at various conferences. He is theholder of six patents. His teaching and research interests include measurements,instrumentation, and signal processing.