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AMBA AHB 2.0By Rashi AggarwalRoll no. 2012UGEC044
AMBA INTRODUCTIONThe ARMAdvanced Microcontroller Bus Architecture (AMBA)is an open-standard, on-chip interconnect specification for the connection and management of functional blocks insystem-on-a-chip(SoC) designsAMBA is a registered trademark ofARM LtdAMBA was introduced by ARM in 1996.
Evolution of amba protocolsAMBA protocols categorized into three generationsThe first generation -ASB and APB. ASB- for highperformance system modulesAPB- for low-power peripheralsthe second generation - came up with an advanced bus protocol for high-performance named as AHB (Advanced Highperformance Bus)third generation protocol which is the AMBA AXI namely the Advanced eXtensible Interface- supports high frequency as well as high-performance system designs for high-speed interconnect.
applicationsThe availability of SystemVerilog assertions for AMBA promotes this industry-wide participation.It is the most widely adopted industry standard for on-chip connectivity for IP products varying from; Memory Controllers, Interconnects, GPU's, CPU's.AHB supports system modules with high-clock frequency and high-performance.
Need of AMBA AHBThe multi-layer architecture acts as a crossbar switch between masters and slaves in AHB system.Acrossbar switchis aswitchconnecting multiple inputs to multiple outputs in a matrix manner. The parallel links allow the bandwidth of the interconnect to support the peak bandwidth of the masters without increasing the frequency of the interconnect.The AHB is a single-channel, shared busthen the AHB will be a 128 bit bus running at 400 MHz
Typical AMBA Based AHB system
Basic transfersRead Transfer
Data read without wait stateBefore third Positive edge of clock
Data written at second Pos edge of clock
Transfers with wait statesRead transfer
Data read after third Pos clock edge
Slave inserts wait states to enable additional timefor completion
Transfer to A & C in 0 wait stateTransfer to B with one wait state
Transfer type encoding
Transfer type example
4 beat readstarts2nd beat 3rd beatLast beatData read for thirdand last beat
4byte word in 4 beats => 4*4=16byte boundary
Example of 4 beat wrapping burst
Example of 4 beat incrementing burst
Example of 8 beat wrapping burst
Example of 8 beat incrementing burst
Example of undefined length
EARLY BUS TERMINATIONThe slave can determine when a burst has terminated early by monitoring the HTRANS signals Ensures that after the start of the burst every transfer is labelled as SEQUENTIAL or BUSY. If a NONSEQUENTIAL or IDLE transfer occurs then this indicates that a new burst has started Therefore the previous one must have been terminated.
Slave Address Decoding
Slave Transfer Response
HREADY wrt HRESP
Example of error response
Example of HRDATA & HWDATAProvide data onlyin final cycleHolds data fornext cycle also
conclusionsThe development of an Advanced Microcontroller Bus Architecture (AMBA) as an Advanced High-performance Bus (AHB)master slave was presented.It was built to increase the system performance by reducing memory access time during the reading and writing of information from and to the memorythe delay for the read and write operations is less than microprocessors and other memory controllers.With the reduced delay, the system speed is increased. So the system efficiency is increased Thus the system performance is improved to a greater rate by using AMBA AHB Bus.