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  • AMBA Level 2 MBIST Controller(L2C-310)

    Revision: r3p1

    Technical Reference ManualCopyright 2007-2010 ARM. All rights reserved.ARM DDI 0402E (ID030610)

  • AMBA Level 2 MBIST Controller (L2C-310)Technical Reference Manual

    Copyright 2007-2010 ARM. All rights reserved.

    Release Information

    The following changes have been made to this book.

    Proprietary Notice

    Words and logos marked with or are registered trademarks or trademarks of ARM in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

    Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

    The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

    This document is intended only to assist the reader in the use of the product. ARM shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

    Where the term ARM is used it means ARM or any of its subsidiaries as appropriate.

    Confidentiality Status

    This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

    Unrestricted Access is an ARM internal classification.

    Product Status

    The information in this document is final, that is for a developed product.

    Web Address

    http://www.arm.com

    Change history

    Date Issue Confidentiality Change

    30 November 2007 A Non-Confidential First release for r0p0

    04 April 2008 B Non-Confidential First release for r1p0

    19 December 2008 C Non-Confidential Unrestricted Access First release for r2p0

    01 October 2009 D Non-Confidential Unrestricted Access First release for r3p0

    03 February 2010 E Non-Confidential Unrestricted Access First release for r3p1ARM DDI 0402E Copyright 2007-2010 ARM. All rights reserved. iiID030610 Non-Confidential

  • ARM DDI 0402E Copyright 2007-2010 ARM. All rights reserved. iiiID030610 Non-Confidential

    ContentsAMBA Level 2 MBIST Controller (L2C-310) Technical Reference Manual

    PrefaceAbout this book ......................................................................................................... viiiFeedback .................................................................................................................... xi

    Chapter 1 Introduction1.1 About the MBIST controller ...................................................................................... 1-21.2 MBIST controller interface ....................................................................................... 1-31.3 RTL configuration .................................................................................................... 1-61.4 Product revisions ..................................................................................................... 1-7

    Chapter 2 Functional Description2.1 Functional overview ................................................................................................. 2-22.2 Functional operation .............................................................................................. 2-11

    Chapter 3 MBIST Instruction Register3.1 About the MBIST Instruction Register ..................................................................... 3-23.2 Field descriptions ..................................................................................................... 3-3

    Appendix A Signal DescriptionsA.1 MBIST controller interface signals ........................................................................... A-2A.2 Miscellaneous signals .............................................................................................. A-4

    Appendix B Revisions

    Glossary

  • List of TablesAMBA Level 2 MBIST Controller (L2C-310) Technical Reference Manual

    Change history ................................................................................................................................ iiTable 1-1 Cache controller MBIST interface signals ................................................................................... 1-4Table 2-1 Cache controller compiled RAM latency ..................................................................................... 2-4Table 2-2 MBISTADDR and MBISTDIN mapping for data RAM, 8-way ..................................................... 2-5Table 2-3 MBISTADDR and MBISTDIN mapping for data RAM, 16-way ................................................... 2-5Table 2-4 Writes for data RAM testing ........................................................................................................ 2-6Table 2-5 MBISTADDR and MBISTDIN mapping for tag RAM, 8-way ....................................................... 2-6Table 2-6 MBISTADDR and MBISTDIN mapping for tag RAM, 16-way ..................................................... 2-7Table 2-7 MBISTTX signals ........................................................................................................................ 2-8Table 2-8 MBISTRX signals ........................................................................................................................ 2-9Table 2-9 MBIST controller top level I/O ..................................................................................................... 2-9Table 2-10 Data log format ......................................................................................................................... 2-13Table 3-1 Pattern field encoding ................................................................................................................. 3-3Table 3-2 Go/No-Go test pattern ................................................................................................................. 3-5Table 3-3 Control field encoding ................................................................................................................. 3-5Table 3-4 Read latency field encoding ........................................................................................................ 3-6Table 3-5 Write latency field encoding ........................................................................................................ 3-6Table 3-6 Y-address field encoding .......................................................................................................... 3-10Table 3-7 X-address field encoding .......................................................................................................... 3-10Table 3-8 Required sums of X-address and Y-address fields for data RAM ............................................ 3-11Table 3-9 Required sums of X-address and Y-address fields for tag RAM .............................................. 3-11Table 3-10 Required sums of X-address and Y-address fields for data parity RAM ................................... 3-11Table 3-11 Enables field encoding .............................................................................................................. 3-12Table 3-12 Column width field encoding ..................................................................................................... 3-13Table 3-13 Cache size field encoding ......................................................................................................... 3-13Table 3-14 Way size field encoding ............................................................................................................ 3-14Table A-1 MBIST controller interface signals .............................................................................................. A-2ARM DDI 0402E Copyright 2007-2010 ARM. All rights reserved. ivID030610 Non-Confidential

  • List of TablesTable A-2 Miscellaneous signals ................................................................................................................. A-4Table B-1 Differences between issue C and issue D .................................................................................. B-1Table B-2 Differences between issue D and issue E .................................................................................. B-1ARM DDI 0402E Copyright 2007-2010 ARM. All rights reserved. vID030610 Non-Confidential

  • ARM DDI 0402E Copyright 2007-2010 ARM. All rights reserved. viID030610 Non-Confidential

    List of FiguresAMBA Level 2 MBIST Controller (L2C-310) Technical Reference Manual

    Key to timing diagram conventions ................................................................................................ ixFigure 1-1 Cache controller MBIST configuration without data banking ...................................................... 1-2Figure 1-2 MBIST controller wiring diagram ................................................................................................. 1-3Figure 1-3 Traditional method of interfacing MBIST ..................................................................................... 1-3Figure 1-4 Cache controller MBIST interface ............................................................................................... 1-4Figure 2-1 Cache controller MBIST and RAM interfaces ......